By

MEHARI GIDENA
(Lecturer)
_____________________________________________________________________________________

Adigrat University
College of Engineering & Technology
Department of Electrical & Computer
Engineering

APPLIED ELECTRONICS HOLISTIC EXAM

September 14/2014 G.C
_____________________________________________________________________________________

By
MEHARI GIDENA
(Lecturer)
_____________________________________________________________________________________
By Adigrat University By
MEHARI College of Engineering & Technology MEHARI
GIDENA Department of Electrical & Computer Engineering GIDENA
(Lecturer) (Lecturer)
_____________________________________________________________________________________
)
Holistic Exam: Applied Electronics I & II (Type multiple choices)
1. You are given a voltage divider transistor biasing with two DC power supply as shown
below with a specification β = 100, VBE = 0.7 (silicon NPN transistor) then the IC and VCE
of the transistor are respectively. (Hint: in the network below K stands for kilo Ohm)
A. 6.6 mA and 39.465 V C. 6.6 mA and -39.465 V
B. 6.6 A and 39.465 mV D. -6.6 mA and 39.465 V

2. Consider the common collector amplifier in figure below the overall voltage gain (Av) and
overall current gain (Ai) are respectively.(if necessary β=85, assume ro is extremely large
and neglect the source resistance 20 Ω in your analysis and base emitter resistance is
much smaller than (B+1)RE )
A) 2 and 9 C. 8.769 and 2
B) 1 and 8.769 D. 8.769 and 1

3. For the class –A power amplifier shown below the input DC power (Pi (DC)) and the output
ac power (Po (ac)) are respectively. (Consider maximum limiting conditions and β= 100,
VBE =0.7 and K stands for kilo Ohm)
A. 42.9 mW and 10 mW C. 42.9 W and 10 W
B. 10 mW and 42.9 mW D. 10 W and 42.9 W
4. The Bi-stable multivibrator shown below has a square wave output signal which varies b/n
Vp=20v and –Vp= -20 V and the input signal is Vin = Am sin 100t where Am is
adjustable peak value. The width of dual stable state region is (Assume R1=R2)
A. 20 C. 40
B. -20 D. 10

5. For the following CMOS logic circuit the logic function and size of each transistor (width to
length ratio) in the NMOS part are respectively.. (Assume symmetrical switching times are
desired and the switching times should correspond to the basic CMOS inverter.)
A. (ABC)’ and 3 C. ABC and 3
B. (A+B+C)’ and 2 D. (A+B+C) and 2
6. A bipolar junction transistor is a three terminal semiconductor device in which its operation
depends on the interaction of both electrons and holes. If the BJT is required to work
properly and sufficient amount of electrons or holes are to be injected from the emitter
region for NPN or PNP transistors the doping level of the collector must be
A. Smaller than the emitter C. the same as the emitter
B. Larger than the emitter D. smaller than the base
7. A study of transistor characteristic shows that the transistor operation is most linear when
the operation is restricted to the
A. Active region C. Cutoff region
B. Saturation region D. break down region
8. A PNP bipolar junction transistor has different types of charge carries in its emitter, base
and collector region. The type of charge carries in the emitter region are
A. Electrons C. ions
B. Holes D. Electron – hole pairs
9. In an NPN or PNP bipolar junction transistors the Emitter current is the sum of Base current
and Collector current ,i.e. IE= IB +IC and the Base current is very small when it is compared
with the Collector and Emitter currents. Why?
A. Because of Base is highly doped than Emitter
B. Because of Base is highly doped than collector
C. Because of Base is lightly doped than Emitter and collector
D. Because of Base is moderately doped
10. NPN bipolar junction transistor has different types of charge carries in its emitter, base
and collector region. The type of charge carries in the Base region are
A. Electrons C. ions
B. Holes D. Electron – hole pairs
11. One of the following is a three terminal device
A. MOSFET C. BJT
B. FET D. All

12. A transistor used to design a high gain and stable amplifier is

A. FET C. Zener Diode
B. BJT D. Thyristor
13. A special diode used for voltage regulation purpose is
A. LED diode C. Varactor diode
B. Photo diode D. Zener diode
14. One of the following diodes is used for light detection purpose
A. LED diode C. Zener diode
B. Photo diode D. Normal diode
15. A Zener diode operates in one of the following regions
A. Above reverse break down voltage C. Below reverse break down voltage
B. In the forward region D. A &B
16. If you need a DC voltage i.e. rectified and filtered from an AC voltage the sequence of
the rectifier and filter are respectively
A. First Filter and second rectifier C. first filter , second Mixer and then Rectifier
B. First rectifier and second filter D. None
17. The potential barrier between the P and N regions of a diode is due to
A. Depletion region C. Valence band
B. Conduction band D. A & B
18. The highest energy level at which excited electrons are found is
A. Valence band C. Forbidden band
B. Conduction band D. None
19. A voltage given as input for a particular ckt provides an output of 0.7 Volt during the
positive half cycle of the input and a full input voltage during the negative half cycle of
the input. This type of electronic ckt is
A. Clamper C. Clipper
B. Rectifier D. Regulator
20. An electronic circuit which produces an offset on to the input voltage is Known as
A. Rectifier C. Clamper
B. Clipper D. Regulator
21. On a semiconductor material an N- type impurity is doped. The majority carriers in this
material are
A. Electrons C. Electrons and holes
B. Holes D. None
22. The bond formed by electron sharing b/n the neighboring silicon atoms and dopants is
A. Ionic bond C. Covalent bond
B. Semi ionic bond D. None
23. At high temperature silicon is more stable than Germanium because
A. Silicon has high energy band gap
B. Germanium’s outer most shell electrons are found one step above silicon
C. Germanium is less temperature sensitive
D. A & B
24. One of the following is an Extrinsic semiconductor
A. Pure silicon C. boron doped silicon
B. Pure Arsenic D. single crystal silicon
25. It is a semiconductor property
A. As temperature increases conductivity increases
B. As temperature increases conductivity decreases
C. As doping level increases conductivity decreases
D. As temperature increases number of free electrons decreases
26. One of the following plays a crucial role in solid state electronics for IC manufacturing
A. Semiconductors C. Conductors
B. Insulators D. None
27. FET operates due to the field generated b/n the opposite particles in the channel or
substrate and gate regions. What type of field is generated to link the gate to the
channel
A. Magnetic field C. Electric charge
B. Electric field D. Magnetic strength
28. The problem occurred on the output signal when you operate a BJT transistor near the
cutoff region is
A. Signal will be clipped in the negative half cycle
 B. Signal will be clipped in the positive half cycle

C. Signal will be clipped in the negative & positive half cycles

D. None
29. What is the transistor biasing applied for the following scheme
A. Fixed base current biasing
B. Voltage divider biasing
C. Constant current biasing
D. Emitter stabilized biasing

30. For a common emitter configuration if the base –emitter junction is forward biased and
collector – base junction is reverse biased then the transistor is operating in
A. Active region C. Breakdown region
B. Saturation region D. Cutoff region
31. A robust amplifier property is
A. Large bandwidth C. small output impedance
B. Large input impedance D. all
32. Junction field effect transistor is a three-terminal device with one terminal capable of
controlling the current between the other two i.e. the drain current ID and the output
characteristic curve of the JFET is plotted as ID versus VDS for different values of VGS. So
FET is
A. Voltage controlled voltage source C. Current controlled current source
B. Voltage controlled current source D. Current controlled voltage source
33. A particular n- channel JFET transistor has the following output characteristics curve. For
linear amplification purpose the transistor should operate
A. Above VP and below VDSmax C. For VGS less than VThn
B. Below Vp D. A & C
34. For the n-channel E-MOSFET shown below the induced channel can be formed due to
A. Positive applied voltage VGS C. Electric field between gate and channel
B. Negative applied voltage VGS D. A & C

35. FET is a voltage controlled three terminal device which operates due to the electric field
produced between the gate terminal and the channel. From the voltage transfer
characteristics of the depleted MOSFET shown below as the input voltage decreases the
Drain current
A. Increases C. Constant
B. Decreases D. None

36. The JFET biasing configuration shown below is

A. Voltage divider biasing C. Self biasing
B. Fixed bias configuration D. None
37. The input resistance for the JFET amplifier shown below is
A. R1||R2 C. RS||R1||R2
B. R1||R2||rπ D. RS||RD||R2

38. The input to the circuit shown in Figure below is V in = 0.20 V. The current iL is
A. 0.75 mA C. - 7.5mA
B. -0.75 mA D. 75mA

39. Design an inverting op-amp circuit with a closed-loop voltage gain of Av = v O /v I =

−12. The current in each resistor is to be no larger than 20 μA when the output
voltage is −4.0 V.
A. R1=16.667KΩ and R2 =200KΩ C. R1=20KΩ and R2 =16.667KΩ
B. R1=200KΩ and R2 =16.667KΩ D. R1=200KΩ and R2 =1.667KΩ
40. Consider an ideal inverting op-amp with forward resistance Rf =100 k and Rin = 10
k .The ideal voltage gain and input resistance Ri are respectively
A. -10 and 10 KΩ C. -1 and 10 KΩ
B. 10 and 10 KΩ D. -10 and 100 KΩ
41. The condition that allows enough current to pass through the pn junction of a diode is
A. Forward bias C. Constant bias
B. Reverse bias D. stabilized current biasing
42. The depletion region width during reverse bias condition of a diode is
A. Narrow C. larger than the p-region
B. Wide D. larger than the n-region
43. To increase the level of conductivity in intrinsic semiconductor, pentavalent impurity atoms
are added. This process produces
A. Additional free electrons C. Equal free electrons and holes
B. Additional free holes D. None
44. The energy band gap for conductors is smaller than semiconductors. Why?
A. Because the ionization energy needed for conductors is smaller than semiconductors.
B. Because the ionization energy needed for conductors is larger than semiconductors.
C. The number of electrons at the outer most shell for conductors are small
D. A & C
45. The biasing scheme show below is
A. Reverse bias C. Fixed bias
B. Forward bias D. stabilized current biasing

46. The two types of field effect transistors are

A. JFET & BJT C. PNP BJT & JFET
B. JFET & MOSFET D. EMOSFET & NPN BJT
47. The following type of multivibrator is
A. Astable multivibrator C. Bistable multivibrator
B. Monostable Multivibrator D. None
48. The oscillation frequency of the following multivibrator is
A. 4.545 KHZ C. 45.45 KHZ
B. 0.4545 KHZ D. 454.5HZ

49. The output characteristics shown below

A. N-channel JFET o/p characteristics
B. P- channel JFET o/p characteristics
C. P- channel EMOSFET o/p characteristics
D. P- channel DMOSFET o/p characteristics
50. The type of channel that will be induced in a N-MOSFET after the biasing potential is
applied is
A. P-channel C. No channel
B. N-channel D. None
51. The output of the center taped full wave rectifier during the positive half cycle is
A. Vp C. Vp/2
B. 2Vp D. 4Vp

52. For the negative half cycle of the input the output in the diode circuit below is (Assume Rlim
is zero or negligible )
A. –Vp C. 2Vp
B. Vp D. -2Vp

53. The output during the positive and negative half cycle of the input for the following diode
circuit is
A. 2Vp-0.7 and -0.7 V C. 0.7 V and 2Vp
B. Vp-0.7 and -0.7 V D. 2Vp and 0.7 V

54. Using ideal diode model the output in terms peak voltage for the following diode circuit is
A. 10V C. 30 V
B. -30 V D. -10 V
55. The minimum load resistance for which the zener diode in fig. below will maintain
regulation is (Assume VZ=15 V, IZmin =1.75 mA and Izmax =60 mA and RL is variable
resistor)
A. 474.9Ω C. 400 Ω
B. 450 Ω D. 8.57 KΩ
R

450
+ +
RL
Vin 30 V D2 Vo
- -

56. The output of the following voltage summer op-amp is

A. (1+R2/R1){[R3/(R3+R4)]V2 + [R4/(R3+R4)]V1}
B. (1-R2/R1){[R3/(R3+R4)]V2 + [R4/(R3+R4)]V1}
C. (1+R2/R1){[R3/(R3-R4)]V2 + [R4/(R3+R4)]V1}
D. (1+R2/R1){[R3/(R3+R4)]V2 - [R4/(R3+R4)]V1}

57. It is not a property of ideal Op-amp

A. It has Large bandwidth C. It has small output resistance
B. It has large input resistance D. None
58. Op-amps are used
A. for voltage summation,
B. for Voltage scaling
C. As electronic integrators
D. as electronic differentiators E. all
59. Assume you need to have an Oscillator with oscillation frequency of fo = ½πRC in which
oscillation starts at R2/R1>2. What type oscillator you will use to demonstrate the above
fact.

A. Wien bridge Oscillator C. RC phase shift Oscillator

B. Hartley Oscillator D . Colipits Oscillator
60. A low pass filter is connected in series to an Amplifier. The amplifier amplifies a signal
received by an antenna and the filter will
A. Remove the low frequency component of the signal
B. Remove the high frequency component of the noise
C. Add a low frequency signal
D. Add a high frequency noise
61. The variable resistor setting in the potential divider circuit shown below is
A. 13.182 KΩ C. 5KΩ
B. 131.82 KΩ D. 10 KΩ

62. The emitter ,base and collector terminals of the NPN transistor shown below are
respectively
A. A, B and C C. B, C and A
B. C, B and A D. B, A and C
63. Consider the following fixed current biasing with Vcc = 4.5V, Ic = 25mA and R1 = 39
kΩ, then the base current Ib and the current gain AI are respectively. (Assume VBE
negligible)
A. 0.115 mA and 216.667 C. 0.0115 mA and 2166.67
B. 1.15 mA and 21.667 D. None

64. For the following BJT circuit with Ib = 20μA , Ic = 2mA, VCE =2 V and Vcc = 9V the value
of R1 and R2 are respectively (Assume VBE negligible)
A. 450 KΩ and 3.5 KΩ C. 450 KΩ and 35 KΩ
B. 45KΩ and 3.5 KΩ D. 4.5 KΩ and 3.5 KΩ

65. The output of the following op-amp amplifier is

A. Vout = -(0.1V1 + 0.2V2 + 0.4V3 + 0.8V4) C. Vout = -(0.1V1 + 2V2 + 0.4V3 + 0.8V4)
B. Vout = -(1V1 + 0.2V2 + 4V3 + 0.8V4) D. Vout = -(0.1V1 + 0.2V2 + 0.4V3 + 0.8V4)
 Rf = 8k
R1 = 80k
R2 = 40k
R3 = 20k
R4 = 10k

66. The output Z of the following logic gate circuit for an input of A=1 and B=0 is
A. 1 C. Don’t care
B. 0 D. A & C

67. For the logic gate circuit shown below with an input of A=1 and B=1 the output P and Q
are respectively
A. 1 and 1 C. 0 and 1
B. 1 and 0 D. 0 and 0

68. The Boolean expression for the output of the logic circuit shown below is
A. (A’ + B’)’ C. (A * B)
B. (A’ + B’) D. A & C
69. The internal resistance of an Ammeter should be very low in order to have
A. high accuracy C. maximum voltage drop
B. high sensitivity D. minimum effect across the meter current in the circuit
70. The minimum number of NAND gates required to implement the Boolean function Y= ADC
+(CD’E +AB’) is equal to
A. 3 B. 2 C. 4 D. 1
71. The early effect in a bipolar junction transistor is caused by
A. Fast turn on B. fast turn off
B. Large collector base reverse bias D. large emitter base forward bias
72. The Op-amp ckt shown below is
A. Electronic integrator C. Voltage subtractor
B. Electronic differentiator D. Voltage summer

73. The output impedance of the following common emitter amplifier is

A. RC ||ro C. RC||RB
B. RB||βre D. ro
74. The voltage gain for the BJT amplifier configuration shown below is AV = -(RC||ro)/re.
The phase angle relation between the input and output voltage is
A. 1800 out of phase C. 2700 out of phase
B. 900 out of phase D. None

75. The fixed-bias configuration of the JFET shown below has an operating point defined by
VGSQ = -2 V and IDQ = 5.625 mA, with IDSS = 10 mA and VP =- 8 V. The value of
the transferred trans-conductance gm is
A. 18.8mS B. 1.88 mS C. 2.5 mS D. 25 mS

Figure A
76. The input impedance of the JFET common source configuration shown above in fig. A is
A. 0.5MΩ B. 1MΩ C. 2KΩ D. None
77. The output impedance of the JFET common source configuration shown above in fig. A is
A. 0.5MΩ B. 1MΩ C. 2KΩ D. None
78. Consider a particular common emitter amplifier has a low frequency response f1=10 HZ
and f2 = 113 HZ due to its coupling capacitors C1 and C2 at its input and output ports.
The low cutoff frequency of this amplifier is
A. 10 HZ B. 113 HZ C. 123 HZ D. 61.5 HZ
79. Consider a particular common emitter amplifier has a high frequency response fA=100
HZ and fB = 1.5 KHZ due to its shunt capacitors CA and CB at its input and output ports.
The High cutoff frequency of this amplifier is
 A. 100 HZ B. 1.5 KHZ C. 1.6 KHZ D. 800HZ
80. Consider the signal in fig A is an input signal to a certain electronic device and the output
is in fig B. What is this electronic device?
A. Clipper C. Clamper
B. Amplifier D. Full wave rectifier

81. Consider the ideal inverting op-amp circuit shown in Figure X below. What is the
voltage gain Av = v O /v I for R2 = 200 k , R1 = 20 k

Fig X. inverting amplifier

A. 10 C. 220
B. -220 D. -10
82. Design an inverting amplifier to provide a nominal closed-loop voltage gain of Av= −30.
The maximum input voltage signal is 25 mV with a source resistance in the range of
1 k ≤RS ≤2 k . The variable source resistance should introduce no more than a 5
percent difference in the gain factor. What is the range in output voltage? (Assume the
percentage difference in the gain factor is 4%)

A. -0.72 V up to -0.735 V C. 0.72V up to 0.75V

B. -0.72V up to- 0.75V D. 0.72 V up to 0.735 V
83. The output of the following difference operational amplifier in terms all resistors and
inputs is.
 A. [(R4/(R4+R3))(1+(R2/R4)]V2+(R2/R1)V1
B. [(R4/(R4+R3))(1+(R2/R4)]V1+(R2/R1)V2
C. [(R4/(R4+R3))(1+(R2/R1)]V2 - (R2/R1)V1
D. - [(R4/(R4+R3))(1+(R2/R1)]V2 + (R2/R1)V1
84. Consider the Wien-bridge Oscillator shown below with R2 = 220 KΩ, R1 = 25KΩ,
C=0.01µF and R = 10 KΩ. What is the oscillator’s oscillation frequency and feedback
ratio β respectively? (assume biasing is +9 and -9)
A. 1592.4 KHZ and 0.333 volt C. 1.5924 KHZ and 1/3
B. 1.5924 MHz and 1/3 D. 1.5924 and 1/3

85. The number of FET transistors in the PMOS part of the static CMOS logic ckt that
implements the logic function Y= (ABC +DE) and the size of transistor A and B in the
PMOS (width to length ratio) is respectively. (Assume symmetrical switching times are
desired and the switching times should correspond to the basic CMOS inverter.)
A. 5 and 4, 4 C. 5 and 6, 4
B. 5 and 2, 2 D. 5 and 6, 6
86. The logic function for the following CMOS logic ckt is
A. AB + A’B’ C. (A + B)(A’ +B’)
B. AB’ + A’B D. B & C
87. For the differential amplifier circuit shown below the differential amplifier input common
mode signal is 1mV, the desired input signal V1=2mV, the collector resistance RC = 2MΩ
and RE =1MΩ. The differential gain (Av) and common mode gain (Ac) of the amplifier are
respectively
A. 461.894 and 1.5 C. 230.947 and 461.894
B. 461.894 and 1 D. 1 and 461.894

88. What is the role of differential amplifier in communication systems?

A. To amplify common mode signals C. To distort desired signals
B. To suppress desired signals D. To amplify desired signals
89. For the JFET common source amplifier shown below (M and K stands for kilo ohm and
Mega ohm) the Overall voltage gain is
A. 14.4 C. 15 mv
 B. 8.4 D. 9.5 A

90. Electrical Resistance of conductors and semiconductors with respect to temperature change
can be expressed as R=Ro +α∆T, R=Ro -α∆T respectively; where α is temperature
coefficient of resistivity and Ro is initial resistance at room temperature. From this you can
conclude that as temperature increases more and more the resistance of conductors and
semiconductors respectively
A. Increases C. increases and decreases
B. Decreases D. decreases and increases

91. Why silicon is used commonly in the manufacturing process of solid state electronic
devices?
A. It has high energy band gap C. Due to modern IC processing Technology
B. It is abundant on the earth D. All
92. The process of adding impurities to a single silicon crystal to increase the conductivity of
the semiconductors is called
A. Polishing C. Doping
B. Etching D. Photolightograpy
93. In the energy band diagram of semiconductors the energy level between conduction band
and valence band is known as
A. Energy gap C. Electron free band
B. Forbidden band D. All
94. For the JFET fixed bias configuration shown below the VGSQ and VG are respectively
A. - 4 V and 4V C. - 4 V and -4V
B. 4 V and -4V D. 4 V and Vi
95. A negative feedback amplifier as compared to the basic amplifier could be characterized
by
A. Large gain sensitivity C. Large bandwidth
B. Large nonlinear distortion D. High noise sensitivity
96. The feedback gain of the non-inverting op-amp shown below is (Hint β =R1/(R1+RF) )
A. A/(A + β) C. 1/(A + Aβ)
B. A/(A +A β) D. A/(1+AB)

97. One of the following is a Uni-polar semiconductor device

A. NPN transistor C. N channel JFET
B. PNP transistor D. All
98. A BJT transistor operates due to
A. Hole – electron interaction C. Diffusion of electrons in to valence band
B. Electricity D. Diffusion of holes in to electrons
99. In the BJT output characteristics curve the point in which the DC load line crosses the output
characteristics curve at the center of the active region is called
A. Quiescent point C. saturation point
B. Operating point D. A & B
100. The configuration type shown below is
A. Common Emitter C. Common Base
B. Common Collector D. None
101. The input and output resistance of the common emitter amplifier below are
respectively (consider ro is the collector –emitter resistance and re is effective emitter
resistance)
A. R1 ||R2||re and RC||ro C. R1||R2||βre and RC || RE
B. R1||R2||βre and RC||ro D. R1||R2||βre and RC||RL