Optical Navigation System

(Hardware)

by
Peter Wu

Department of Computer Science and Electrical Engineering,

University of Queensland

Submitted for the degree of

Bachelor of electrical Engineering / Bachelor of Arts
In the division of Electrical Engineering

October 2001
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32 Estoril St
Robertson QLD 4109
Tel. (07) 3344 5525
October 19, 2001

The Head
School of Information Technology and Electrical Engineering
University of Queensland
St Lucia, Qld 4072

Dear Professor Kaplan,

In accordance with the requirements of the degree of Bachelor of Engineering (Hon-ours)

in the division of Electrical Engineering, I present the following thesis entitled “optical
Navigation System”. This work was performed in partnership with Mr. Tien-Lung Lee
and under the supervision of Mr. Bryan Reeves. I declare that the work submitted in this
thesis is my own, except as acknowledged in the text and footnotes, and has not been
previously submitted for a degree at the University of Queensland or any other institution.
Yours sincerely,
Peter Wu.

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Abstract

This thesis describes the design and implementation of a self-contained navigation device
able to track the spatial position of ground surfaces in 2-dimensions. This device is
designed to accurately determine the spatial position of a mobile sensor as well as portray
an image of the ground, much like a scanner device. The Optical Navigation System
departs from the majority of existing products by implementing three image sensors that
could detect motion and rotation, as opposed to the conventional block sensor array. The
project also serves as a breakthrough in the design of navigation devices that are cheap,
self-contained and stable in short range scanning operations. Certain analysis of the
system’s design and has been completed, and a number of design improvements have
been suggested. While the Optical Navigation System’s software development is not
complete, the majority of the hardware design has been completed and tested.

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Acknowledgements

A thesis of this magnitude could not have been completed without the help of a
substantial number of people. Thanks must be extended to a broad array of benefactors:

Tien-Lung Lee for assisting with every aspect of this thesis. Without Tien-Lung, critical
aspects could not have been completed. His judgements have been invaluable in all
aspects of this thesis, including those in which he was not actively involved.

Bryan Reeves for providing a useful level of oversight, yet interfering only when
necessary. His guidance was always well received, as was his tolerance regarding
persistent interruptions and demands.

Len Payne for allowing us access to the new Axon labs and providing constructive
advice towards the project.

Katherine Ho for proof reading this thesis, and more importantly, her endless support
through the good and bad times this year.

Fred Hamilton and Brian Burford from National Semiconductor have given me
valuable information regarding the LM9830.

Keith and Barry from the electronic workshop, they’ve provided me with countless help
on soldering the project PCB.

Finally, I would like to thank my parents and other friends who have been supportive in
many ways towards me, I thank them very much.

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Contents

Letter to Head of ITEE department ii

Abstract iv

Acknowledgements vi

List of Figures xi

List of Tables xiii

1 Introduction 1
1.1 Design considerations 2
1.1.1 Performance 2
1.1.2 Cost 3
1.1.3 Usability 3
1.2 The organisation of work 3

2 Evaluation of existing navigation systems 5

2.1 GPS 5
2.2 INS 7
2.3 Laser positioning system 10
2.4 Radio Frequency navigation system 11
2.4.1 Decca system 11
2.4.2 LORAN-A 12
2.4.3 LORAN-C 13
2.5 Optical mouse 15
2.6 Summary 16

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3 Theory 18
3.1 Optical Sensors 18
3.1.1 CCD technology and characteristics 19
3.1.2 CMOS technology and characteristics 19
3.1.3 So why the CMOS image sensor? 21
3.1.4 Implementation of CMOS sensors 21
3.2 Signal processor 21
3.2.1 AD9822 22
3.3 Main processor unit 23
3.3.1 Altera MAX-7000 PLD 23
3.3.2 LM9830 24
3.4 Transmission 27
3.4.1 The parallel port 27
3.4.2 Enhanced Parallel Port 28
3.4.2.1 Hardware and addressing 28
3.4.2.1 Transfer cycles 30
3.5 Buffer 32
3.5.1 FIFO 33
3.5.2 SRAM 33
3.6 Summary 35

4 Hardware implementation 37
4.1 System design 37
4.1.1 Schematic design 37
4.1.1.1 Parallel port 38
4.1.1.2 SRAM 39
4.1.1.3 Optical sensors 40
4.1.1.4 Other connections 42
4.1.2 PCB 42
4.1.2.1 Design considerations 43
4.1.2.2 Importance of ground and power connections 43
4.2 Mechanical layout 43

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4.2.1 Lens 44
4.3 Summary 44

5 Software implementation 45
5.1 Initial considerations 45
5.2 Programming the EPP 45
5.2.1 Switching directions 46
5.2.2 Clearing timeouts 47
5.3 LM9830 control 47
5.3.1 Module 1(Initialise & Setup) 48
5.3.1.1 Initialise LM9830 48
5.3.1.2 Setup configuration registers 48
5.3.2 Module 2(Scan & Read data) 49
5.3.2.1 Scan 49
5.3.2.2 Read Data 53
5.4 Summary 54

6 Design review 55
6.1 Status of project 55
6.1.1 Hardware 55
6.1.2 Software 56
6.2 Performance evaluation 56
6.3 Future developments 57

7 Conclusion 58

References 59

Appendices 64

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Appendix A – Schematics 64
Appendix B – Design PCB 65
Appendix C – Source code 68

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List of Figures

2.1 GPS receiver……………………………………………………………………….6

2.2 DGPS block diagram………………………………………………………………7
2.3 Mathematical concept for INS systems……………………………………………8
2.4 INS system link up with computer………………………………………………...9
2.5 GPS/INS system…………………………………………………………………...9
2.6 Laser positioning sensor…………………………………………………………..10
2.7 Laser positioning beacons…………………………………………………………11
2.8 DECCA navigation system………………………………………………………..12
2.9 Propagating waves in a LORAN navigation system………………………………13
2.10 LORAN-C coverage map………………………………………………………...14
2.11 Top view of Logitech optical mouse…………………………………………….15
2.12 Bottom view of Logitech optical mouse…………………………………………15
2.13 The imaging technique employed by optical mice………………………………16

3.1 Theoretical Block diagram of operations…………………………………………18

3.2 CCD and CMOS image sensor architecture………………………………………20
3.3 Triangular array of CMOS image sensors………………………………………...21
3.4 Block diagram of a typical imaging application…………………………………..22
3.5 Block diagram of AD9822………………………………………………………...23
3.6 Features of the MAX-7000………………………………………………………..24
3.7 Max-7000 architecture…………………………………………………………….24
3.8 LM9830 scanner block diagram…………………………………………………..27
3.9 EPP Address Write………………………………………………………………..30
3.10 EPP Address read cycle………………………………………………………….31
3.11 EPP Data write cycle…………………………………………………………….32
3.12 EPP Data read cycle……………………………………………………………...32
3.13 IS61C1024 SRAM block diagram……………………………………………….35

4.1 Block diagram of system design…………………………………………………..38

4.2 Sequential read – Dynamic Pixel Reset time cycle………………………………..41

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5.1 EPP control signals for DB25 parallel ports……………………………………….47

5.2 12 bit mode pixel data format……………………………………………………...50
5.3 Pixel packing into one Byte diagram………………………………………………50
5.4 TR1-φ1 guardband equal to 0 diagram…………………………………………….51
5.5 3-channel pixel rate mode diagram………………………………………………...51
5.6 12 bit/8 slot SRAM access mode…………………………………………………..52
5.7 Memory map for IS61C1024 SRAM………………………………………………53
5.8 Reading pixel data (EPP) time diagram……………………………………………54

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List of Tables

3.1 Pin descriptions for EPP………………………………………………………...28

3.2 EPP registers and their functions………………………………………………..29
3.3 Summary of different modules of the proposed system design…………………35

4.1 Truth table of operations for the IS61C1024……………………………………40

4.2 Truth table for the LIS-1024 modes……………………………………………..41

5.1 Listing of significant registers setup before scanning…………………………...49

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Chapter 1

Introduction

Since the beginning of our existence, humans have faced the challenge of creating a
means that would enable them to confidently determine where they are, help guide them
to where they are going, and to get them back home again.

Studies of prehistoric human beings suggest that stones and twigs were employed to mark
a trail when they set out hunting for food. The earliest mariners followed the coast
closely to keep from getting lost. When navigators first sailed into the open ocean, they
discovered they could chart their course by following the stars.

As the human species have evolved and developed, so too have our navigation techniques,
and continue to do so as there seems to be no limits to the possibilities.

The origins of optical navigation can also be traced back to military target tracking, but it
offers a more advanced application. Optical navigation tracks textures or features, and
rather than continually re-centring them, measures their movement from the previous
position. Both optical navigation and target tracking capture sequential images and use
cross-correlation to determine any displacement between the images.

Optical navigation is a relatively complex science, engaging in fast image capture and a
suite of mathematical image-processing manipulations, including prediction, correlation,
and interpolation.

In the past decade, navigation devices have made vast technological advancements with
improvements in performance, accuracy and precision. Yet, most of the modern
navigation devices are often limited to usage within the high technology sectors of the
public, often implicating that the costs and availability of these navigation systems are
expensive and rare. One example of a navigation system available to public is the car

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GPS tracking system, but it is also high in costs and availability is somewhat scarce. The
intention of the project was to develop a device that could scan ground images and also
provide spatial positions using optical sensors, while not allowing the developed system
to skyrocket in price.

Despite all the new technological developments and inventions, a device that could scan
ground images and portray relative position of travel has yet to be created. The absence
of such a product in the market prompted the desire to create a device that could track the
spatial position of ground surfaces in 2-D as it moves over a surface. Furthermore, the
ideal product would have the additional features of being relatively inexpensive, self-
contained and reasonably accurate in its scanning.

The application of such a system could be used in conjunction with other navigation
systems such as the GPS system, or it could be further developed to act as a handheld
scanner. Hence, there are many future developments available for such a device.

1.1 Design considerations

It is logically expected that there would be a number of design considerations that need to
be taken into account, in the delivery of such a product before further engineering
techniques can begin. The Optical Navigation System was designed with significant
emphasis on three main criteria, namely performance, cost and usability.

1.1.1 Performance
The first area of focus is to design with performance in mind. The performance of
the Optical Navigation System can be somehow considered to be close to that of a
scanner’s; that is, clear resolution and high data transfer speeds are the two most
important items that need to be achieved. In terms of the navigation capabilities,
the margin of error would have to be as low as possible, as a high margin of error
would not make much sense since the device is only intended to scan areas in
small scale. Scanning pace is another performance criterion that needs to be
looked upon, as well as the speed of data transfer would also determine the

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 device’s performance capabilities. In general, if the scanning pace and data
transfer speed could keep up with the speed of 4m/s (walking pace), the device
would have met its requirements.

1.1.2 Cost
Cost is always a key issue in any design. Naturally, there will be a general regard
for minimising the cost of an end product, however the design aims also to
minimise the cost of development as well. As discussed above, the cost of
navigation devices is often very high, not to mention the general public, but also
for the likes of research and development. Therefore a lower price tag on the
optical Navigation system would be beneficial to many parties.

1.1.3 Usability
The intended audience for use of the optical Navigation system would mainly be
academics or people from the navigation professional, therefore it is assumed that
the audience has a certain degree of background knowledge in MatLab and
navigational/imaging devices, hence the user interface design would not be a main
priority within the project. However, the usability of the device itself is intended
to be as simple as possible, as explained that the device would be self-contained,
and it’ll only require the user to have a Personal Computer.

1.2 The organisation of work

Having explained the aims and design considerations of the project, further discussion
upon the thesis will be discussed by the author in later sections. Here is a brief summary
of the contents in this thesis.

In Chapter 2 a range of currently available products which come close to satisfying the
stated vision are examined, and a key set of product features are identified. The other
systems that will be discussed in this chapter are the Global Positioning System (GPS),
Inertial Navigation System (INS), laser/radio location system and the optical mouse.

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Chapter 3 sees the description of the specific modules of the Optical Navigation System.
This chapter talks about some of the specific components used in the Optical Navigation
System, and also talks about the hardware structure and flow of the scanning process.

Chapter 4 describes the actual components used, that is, their use in the navigation device
and the method to implement them together.

The software that is used to control the hardware is described in chapter 5. Although the
code is not fully functional, the details of the software coding are explained in this
chapter.

Chapter 6 highlights the review of the design. Based upon the level of functionality of the
device, the entire design is reviewed, and errors as well as methods that would’ve
increased the device’s functionality are highlighted. Other future enhancements are also
enlisted.

Chapter 7 is the presentation of final conclusions.

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Chapter 2

Evaluation of existing navigation systems

In order to design a system comparable or superior to existing products, it is necessary to

identify the capabilities of other navigation systems. There are already a wide range of
navigational devices and systems in the market, representing a wide range of
functionalities, so a review on their capabilities would be beneficial in understanding
navigational systems and devices.

A number of different systems were reviewed in order to identify key features of the
Optical Navigation System. Following the review of these systems and products, the
derivation of the Optical Navigation specifications are presented.

2.1 Global Positioning System (GPS)

This is probably a familiar name with many people, but its operation is quite interesting
and some how relates to the project. The GPS is a worldwide radio-navigation system
formed from a constellation of 24 satellites and their ground stations. These satellites are
used as reference points to calculate the relative positions of the navigated object. GPS in
a sense is like giving every square meter on the planet a unique address. These days GPS
is finding its way into cars, boats, planes, construction equipment, farm machinery, and
even laptop computers. GPS systems follow five fundamental steps, as follows:

1. The basis of GPS is "triangulation" from satellites.

2. To "triangulate," a GPS receiver measures distance using the travel time of radio
signals.
3. To measure travel time, GPS needs very accurate timing which it achieves with
some mathematical methods.

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 4. Along with distance, the position of the satellites needs to be known. These
satellites need to be carefully monitored.
5. Finally, errors need to be corrected for any delays the signal experiences as it
travels through the atmosphere.

Figure 2.1 GPS receiver

The block diagram for the GPS receiver is portrayed in figure 2.1. However, the GPS
system has accuracy correct to meters, and the Optical Navigation system being
developed requires an accuracy up to the scale of centimetres, therefore a brief look into
the Differential GPS system is worthwhile, although this system costs a great deal more
than the usual GPS system (thousand’s of dollars).

Differential GPS involves the cooperation of two receivers, one that's stationary and
another that's roving around making position measurements. The stationary receiver is
the important reference point. It ties all the satellite measurements into a solid local
reference. The operation behind differential GPS (DGPS) is that one receiver measures
the timing errors and then provides correction information to the other receivers that are
roving around. That way virtually all errors can be eliminated from the system, hence
increasing the accuracy range during navigation. Please refer to the block diagram figure
2.2.

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 Figure 2.2 DGPS

In summary, the GPS system has good long-term stability, meaning that it can be used to
navigate at long distances with high precision. The GPS system was not considered to
form the basis of the Optical Navigation System due to the fact that it isn’t a self-
contained device, accuracy isn’t high enough for local navigation and the costs of DGPS
systems are not feasible for this particular project.

2.2 Inertial Navigation System (INS)

Inertial navigation is based on techniques which have been invented and developed after
the Second World War. The first systems were built of mechanical gyros, which required
very complicated technical and power consuming constructions being prone to failure.

Later on 'solid state' solutions have been realized by using only discrete integrated electro-
mechanical or electro-optical sensors. These 'solid state' systems had no moving parts,
but consisted of expensive laser-gyros and integrated sensor devices. INS is used in civil
and military aviation, cruise missiles, submarines and space technology. According to
these areas of operation, the components used and the entire system has to be very precise
and reliable.

Consequently, the costs for such a system are still very high (> 100'000 US dollars) and
the size is not yet as small that it can be used for mobile roboting, automotive or
consumer electronics.

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The idea behind the INS is that a body’s actual spatial behaviour / movement can be
described with six parameters: three translatory (x-, y-, z-acceleration) and three rotatory
components (x-, y-, z-angular velocity). To be able to define the movement of the body,
three acceleration sensors and three gyros have to be put together on a platform in such a
way that they form an orthogonal system. The distance laid back and the angle the body
has rotated can be obtained by integration of the individual translatorial and rotatory
components. Performing these calculations accurately and periodically enables the ideal
system to trace its movement and to indicate its current position and heading. Please refer
to figure 2.3 about the mathematical concept behind INS.

Figure 2.3 Mathematical concept behind INS

However, nothing’s perfect, and although the INS can have accuracy ranging to
centimetres, it still has some limitations. The main limitation of the system performance
is given with the finite precision of the sensors. A continuous small error in acceleration
will be integrated once and results in a big error in actual speed, integrated a second time
in a greater error in distance. Therefore very precise sensors and error correction
mechanisms (feedback algorithms) are necessary to get an accurate inertial navigation
platform. Therefore, if the INS were used for small navigational areas, the degree of
accuracy would be quite high since the amount of compounding errors has yet to
accumulate to a substantial amount.

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 Figure 2.4 INS system linked up to a laptop

Because the Global Positioning System (GPS) and an inertial navigation system (INS)
complement each other, it is common practice to integrate the two systems in applications
calling for continuous high accuracy and reliability. Kalman filtering1 is the basis for
correcting the INS with GPS measurements of satellite range. In the combined system,
the INS provides smooth and accurate short-term measurements of acceleration and
velocity that can be used to aid GPS receiver code and carrier tracking. Together the two
systems permit improved navigation accuracy especially when GPS is degraded or
interrupted because of jamming or interference. Please refer to figure 2.5 for the block
diagram of this system.

Figure 2.5 GPS/Ins system

1
Kalman filtering is a mathematical technique used by navigational engineers to estimate the state of a
system from measurements which contain random errors

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2.3 Laser positioning Systems

The Laser positioning system consists of numerous laser-sensing beacons spread out in a
sampling field, and of another optical sensor/pointer that is being tracked.

In general, these devices work by the fact that the object that requires navigation is
located within the sampling field, carrying the pointer that will be tracked. Hence the
pointer can send and receive signals to and from the beacons, which then tells the user the
position of the object.

The HiBall 3000 device is a laser-positioning device that works in a similar fashion to the
theory explained before. Due to the improvement in technology, these devices now have
very high accuracy and are reasonably priced, but they are highly restricted due to the fact
that sampling beacons need to be placed within the field, hence it isn’t a self-contained
system. Also, the purpose of scanning ground images isn’t met too, due to the nature of
these devices leaning more towards a “tracking” sense of nature.

Figure 2.6 Laser positioning sensor (Hi-Ball 3000)

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 Figure 2.7 Laser positioning beacons (Hi-Ball 3000)

2.4 Radio Frequency navigation system

A few ground-based radio-navigation systems are still in use today. One drawback of
using radio waves generated on the ground is that a choice between a system that is very
accurate but doesn't cover a wide area, or one that covers a wide area but is not very
accurate. High-frequency radio waves (like UHF TV) can provide accurate position
location but can only be picked up in a small, localized area. Lower frequency radio
waves (like AM radio) can cover larger areas, but are prone to errors.

Radio Frequency navigation systems were the most common navigation systems up until
the 1970’s, before GPS systems really took off. There are a few navigation systems that
use radio frequency, and the more common ones are the DECCA Navigator System,
LORAN-A Navigator system and the LORAN-C navigator system.

2.4.1 DECCA Navigator System

The DECCA system is a low-frequency hyperbolic navigation system covering
much of Western Europe, parts of Canada, the Persian Gulf and the Bay of
Bengal.

Hyperbolic navigation systems use coordinated transmissions from two or more

radio stations. It relies on the fact that all the points where the difference between
radio signals from different stations are a constant form of a hyperbola. The user
uses radio equipment to listen to the radio signals, and then matches the difference

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heard to the appropriate hyperbola on the map. This puts the user somewhere
along one arc on the ground. This process is repeated by using a second pair of
stations to determine another hyperbola. Therefore the user determines position by
finding the point on the map where the two parabolas intersect.

DECCA works by comparing the phase difference of radio signals emitted by

several radio stations. The conventional DECCA chain consists of three slave
transmitting stations, namely red, purple and green being symmetrically located
around a common master station. It employs transmitting signals of very low
frequency (around 100 kHz) for phase difference measurements.

The DECCA system had an accuracy found to be less than 15 km, due to
anomalies in the propagation velocity of electromagnetic radiation. The accuracy
is considered to be quite unacceptable nowadays, which explains why this system
is hardly used anymore. Figure 2.8 is a block diagram of the DECCA system.

Red slave station

Red Baseline

Green baseline
Purple baseline
Master Station

Purple slave station Green slave station

Figure 2.8 DECCA navigation system block diagram

2.4.2 LORAN-A Navigator system

The LORAN-A (standard LORAN) system was developed during World War II at
the Massachusetts Institute of Technology. LORAN-A is another hyperbolic
navigation system. LORAN stands for LOng Range Navigation and was

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developed in response to the need for precise navigation for military ships and
aircraft. Operation was in the 1850 kHz - 1950 kHz radio band.

The system had a 1km range, which is considered to be quite reasonable in the
past. LORAN-A also uses radio stations positioned along the regions intended for
navigation, but it differs from the DECCA system due to the use of a different
frequency range. This is because that the lower frequency transmissions produced
most stable sky wave signals at night, whereas the higher frequencies gave more
stable sky wave reflections by day. Therefore it was decided that the medium
frequencies offered the best compromise solution for long-range navigation
performed at both night and day.

Due to its nature of having different performances in day or at night, the level of
accuracy also differs. In daytime, the margin of error ranges from +/- 270m to +/-
2 km. At night, the average position error ranged between +/- 2.5 to +/- 14 km,
due to the longer wavelengths in the transmission signals (low frequency).

Figure 2.9 Propagating waves in the LORAN navigation system

2.4.3 LORAN-C Navigator system

The LORAN-C system was developed after the LORAN-A system. It uses radio
navigation systems operating in the 90 kHz to 110 kHz band.

LORAN-C is a pulsed hyperbolic system that provides 20 - 90 m in repeatable

accuracy. The LORAN-C navigation network is one that is still currently used as
the previously discussed navigation systems have been discarded. It was

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developed to provide the U.S. Department of Defence with a radionavigation
capability with longer range and much greater accuracy than its predecessor,
LORAN-A. Loran-C provides coverage for the continental U.S. and its coastal
waters, as well as many other countries such as India, Norway, France, Ireland,
Germany, Spain, Italy, Russia, China, Japan, and the Philippines.

Figure 2.10 LORAN-C coverage (shaded)

The theory behind LORAN-C is that it uses the difference in the time of arrival of
radio frequency pulses broadcast by three or more transmitting stations. A
LORAN-C line of position is determined by measuring (a) the difference in time
of arrival of synchronised pulsed signals from a master and secondary transmitting
station, and (b) the difference in phase of the synchronised 100 kHz carrier within
the master and secondary pulses.

Position accuracies in the LORAN-C system are functions of two parameters;

geometrical considerations and instrumental errors in the transmitting and
receiving systems. The accuracy range is within 20 – 90 meters; hence it has
greater accuracy than the previously mentioned navigation systems.

The Radio Frequency method of implementing an optical navigation device was

not feasible; however, it did provide some helpful insight into the methods and
practices of some established navigation systems.

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2.5 Optical mouse

Figure 2.11 Top view of Logitech optical mouse

Figure 2.12 Bottom view of Logitech optical mouse

The Optical Mouse is one of the recent breakthroughs in optical navigation systems and
devices. The optical mouse performs exactly the same way as the mechanical mouse,
however, it is a device that offers superior precision and accuracy, high reliability over
traditional mechanical mouses, and needs no maintenance what so ever.

The optical mouse is by far the closest device in the market that matches the aims and
criteria of the project. The development of the optical mouse is due to recent advances in
application-specific integrated circuits (ASICs), imaging arrays, and embedded
mathematics; technologies that have come together to lower the cost and increase the
practicality of optical navigation.

For the optical mouse, optical navigation involves capturing an image and then analysing
it by tracking the motion of microscopic texture or other features on a surface. Because
optical mice depend on tracking surface detail, a key discovery was that most work
surfaces are microscopically textured. When these surface textures are illuminated by a
light-emitting diode (red light in fig. 2.12), a pattern of highlights and shadows are

15
revealed (see figure 2.13). Optical mice "watch" these surface details move by imaging
them onto navigational integrated circuits.

Figure 2.13 The imaging technique employed by optical mice

The optical mouse is a device that can achieve similar aims to the project that it is able to
provide spatial positions of the navigational path, but this path is limited to be within the
size of a computer screen, which simply cannot be used as a “navigational device.” Also,
the optical mouse cannot portray ground images, as it is purely a positional device.

2.6 Summary
The specifics of the Optical Navigation System can then be listed having completed the
analysis of various navigation systems. The analysis has also served as a good source of
knowledge of the techniques, mathematics and theories employed in developed navigation
systems. The following core specifications have been identified as:

!" The Optical Navigation System should be self-contained.

!" The navigational path should be limited to local area; vast coverage is not possible,
unless linked with another system.
!" The scanned image only needs to be in black and white, colour processing will take
up additional time in the scanning process.
!" As mentioned, accuracy and precision is very important in navigational devices,
therefore the degree of accuracy needs to be limited to within 1% ~ 3% degree
accuracy.
!" Economical

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!" The speed of data transfer, i.e. the speed that the scanned image will be portrayed
upon the PC monitor should be as fast as possible. Probably would not be able to get
real time scanning effects, but as fast as the system can go.
!" Acquire a scanning pace of approximately walking pace, or at 4 m/s.

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Chapter 3

Theory

In this chapter, the theory behind the operation of the Optical Navigation system will be
explained, along with a discussion of some of the hardware parts that were examined.
The actual hardware implementation is discussed in chapter 4. To start off the chapter,
please look at figure 3.1 for the overall hardware block diagram.

Host PC Sends
& Receives
signals

Transmission Screen
interface display

Optical
sensor Buffer
outputs

Signal Main
processor Processor
unit

Figure 3.1 Theoretical Block diagram of operations

3.1 Optical Sensors

The project course outline actually specified that the project would be using CMOS
(complementary metal oxide semiconductor) image sensors, yet there are many other
image sensors in the market that can also be considered. Right now, the most commonly
used image sensor in the optic-electronic field is the CCD (charge-coupled device) sensor,
most popularly used in the likes of digital cameras and other photo-image devices,
however, this situation might change and the reasons will be given in the following

18
passages. The choice of image sensors was vital for this thesis project; therefore a
detailed discussion of these two sensors along with comparisons will be followed.

3.1.1 CCD technology and characteristics

Both CMOS and CCD imagers are manufactured in a silicon foundry; the
equipment used is similar. But alternative manufacturing processes and device
architectures make these imaging sensors quite different in both capability and
performance.

Developed in the 1970s and 1980s specifically for imaging applications, CCD
technology and fabrication processes were optimized for the best possible optical
properties and image quality. The technology continues to improve and is still the
choice in applications where image quality is the primary requirement or market
share factor.

A CCD comprises photosites, typically arranged in an X-Y matrix of rows and

columns. Each photosite, in turn, comprises a photodiode and an adjacent charge
holding region, which is shielded from light. The photodiode converts light
(photons) into charge (electrons). The number of electrons collected is
proportional to the light intensity. Typically, light is collected over the entire
sensor simultaneously and then transferred to the adjacent charge transfer cells
within the columns.

Next, the charge is read out: each row of data is moved to a separate horizontal
charge transfer register. Charge packets for each row are read out serially and
sensed by a charge-to-voltage conversion and amplifier section. This architecture
produces a low-noise, high-performance imager. That optimization, however,
makes integrating other electronics onto the silicon impractical. In addition,
operating the CCD requires application of several clock signals, clock levels, and
bias voltages, thereby complicating system integration and increasing power
consumption, system size, and cost.

3.1.2 CMOS technology and characteristics

A CMOS image sensor, on the other hand, is made with standard silicon processes
in high-volume foundries. Peripheral electronics, such as digital logic, clock

19
drivers, or analog-to-digital converters, can be readily integrated with the same
fabrication process. CMOS image sensors can also benefit from process and
material improvements made in mainstream semiconductor technology.

To achieve these benefits, the CMOS sensor architecture is arranged more like a
memory cell or flat-panel display. Each photosite contains a photodiode that
converts light to electrons, a charge-to-voltage conversion section, a reset and
select transistor and an amplifier section. Overlaying the entire sensor is a grid of
metal interconnects to apply timing and readout signals, and an array of column
output signal interconnects. The column lines connect to a set of decode and
readout (multiplexing) electronics that are arranged by columns outside of the
pixel array. This architecture allows the signals from the entire array, from
subsections, or even from a single pixel to be readout by a simple X-Y addressing
technique, something a CCD can’t do.

The biggest opportunities for CMOS sensors lie in new product categories for
which they are uniquely suited. Feature of their success are

!" Lower power usage

!" Integration of additional circuitry on-chip
!" Lower system cost

The difference in the architecture of the image sensors is shown in figure 3.2.

Figure 3.2 CCD and CMOS image sensor architecture

20
 3.1.3 So why the CMOS image sensor?
Recalling the system’s criteria mentioned previously, the Optical Navigation
system was meant to be implemented with low cost materials, therefore the CMOS
sensor would seem to fit best. Also, due to the manufacturing process of the
CMOS sensor, other circuitry are on-board the same chip, making the
implementation process much simpler.

3.1.4 Implementation of CMOS sensors

The image sensors shall be implanted in a form of a triangle, the reason being that
when simultaneous readings are taken from each corresponding pixel upon each
sensor, calculations at that instance in time can be made by a software program,
hence calculating the overall value at that instance of time.

Another calculation will be performed once the point of calculation has reached
the following pixel, and then the program would compare the two calculated
values, then trace and display the path of travel upon a computer. Therefore, it is
reasonable to say that the more pixels on a sensor, the more detailed and accurate
the reading would be, since more calculations are performed. The CMOS sensor
LIS-1024 consists of 1024 pixel arrays, and doesn’t require additional hardware,
so it was considered to be the first choice for the image sensors. The cost for each
LIS-1024 is US$12. Details about the hardware implementation of these sensors
are in the next chapter.

Figure 3.3 Triangular array of CMOS image sensors

3.2 Signal Processor

The signal processor connected must be able to process the data sent by CMOS sensors
before they reach the main processing unit. The data from the sensor must be processed

21
in the analog domain, converted to digital, and further processed in the digital domain.
This allows the image to be analyzed, manipulated, and enhanced, prior to storage,
display, transmission, and/or further processing.

Imaging applications typically involve three chips—an image sensor, an analog front-end
(AFE), and a digital ASIC (application-specific integrated circuits). The AFE conditions
the analog signal received from the image sensor and performs the analog-to-digital (A/D)
conversion. The digital ASIC contains image processing and timing-generation circuitry.
So in general, the signal processor block will involve the use of the AFE and the digital
ASIC. Figure 3.4 represents a typical imaging application.

Figure 3.4 Block diagram of a typical imaging application

3.2.1 AD9822
One device that would fit into the proposed system is the AD9822. It is a
complete analogue signal processor for CCD image sensors. However, the CDS2
amplifiers may be disabled for use with CMOS sensors, which do not require CDS.

The 14 bit digital output from the CMOS sensor would be multiplexed into an 8-
bit output word that is accessed using two read cycles. The internal registers are
programmed through a 3-wire serial interface, and provide adjustment of the gain,
offset, and operating mode. Since the proposed idea is to use three CMOS
scanners placed in a triangular array, the multi-channel feature of the AD9822
allows three sampling channels to operate simultaneously, being the red, Green
and Blue outputs. Therefore the tracking of position and rotation can be calculated.
The price for the AD9822 is USD $4.033.

2
To filter the video signal from noise of high and low frequencies, the baseline and the CCD output are
integrated and subtracted by the correlated double sampler (CDS).
3
Price figure taken form Analog Devices website

22
 Figure 3.5 Block diagram of AD9822

3.3 Main processor unit

The main processor unit has the job of processing the digital data converted by the signal
processor for transmission purposes. It is also the main unit that will control the scanning
process. A chip with on-board transmission interfacing is also part of the requirements.

3.3.1 Altera MAX-7000 PLD

The Altera MAX-7000 was considered to be a candidate for the main processor
unit. It is a programmable logic device with multiple array matrices that are able
to handle multiple operations simultaneously. The MAX-7000 architecture
includes the following elements: Logic array blocks, Macrocells, Expander
product terms (shareable and parallel), Programmable interconnect array and I/O
control blocks. The features are listed in figure 3.6.

The I/O control blocks are of particular interest to the design of the navigation
system. The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state buffer
that is individually controlled by one of the global output enable signals or directly
connected to ground or VCC. One possibility of implementing this device was by
using these input/output pins of one Macrocell region to act as a transmission
interface, using another Macrocell region for scanner controls and another
Macrocell region to process the image data for transmission. The MAX-7000
PLD can be programmed with external hardware, but it requires 486 or Pentium

23
 based PCs with the MAX+PLUS 2 Programmer, an Altera Logic Programmer
card, a Master Programming Unit (MPU), and the appropriate device adapter. As
you can image, it will be quite costly to obtain these programming elements, and
there would be many limitations to the programming. The cost of the MAX-7000
is AUS $42.164.

Figure 3.6 Features of the MAX-7000

Figure 3.7 Max-7000 architecture

3.3.2 LM9830

4
Taken from Farnell 2000 catalogue, book 2 pp. 1912

24
Other possibilities had to be considered since using the MAX-7000 would pose
unnecessary difficulties. Scanner chips were a good bet to investigate in, so one
particular chip, the LM9830 stood out from the rest.

The LM9830 is a complete document scanner system on a single IC. The

LM9830 provides all the functions (CCD control, illumination control, analog
front end, pixel processing function, image data buffer/SRAM controller, micro
stepping motor controller, and EPP parallel port interface) necessary to create a
high performance color scanner, which is also good enough for the optical
Navigation System. The Optical Navigation System requires external SRAM for
buffering purposes.

This meant that the LM9830 was able to perform all the desired operations of the
Optical Navigation system, with the benefit of having the signal processor
(AD9822) and the PLD (MAX-7000) combined together. Since the LM9830 was
around US$8 per piece and free samples were available for development, the cost
of developing and implementing the device was not considered to be high. Here
are some of the features of the LM9830 that are useful to the Optical Navigation
System (as quoted from the datasheet):
!" Scans at up to 6Mpixels/s (2M RGB pixels/sec).
!" Digital Pixel Processing provides 300, 200, 150, 100, 75, and
50 dpi horizontal resolution from 300dpi sensor, and 600, 400,
300, 200, 150, 100, 75, and 50 dpi horizontal resolution from a 600dpi sensor.
!" Provides 50-600dpi vertical resolution in 1 dpi increments.
!" Pixel rate error correction for gain (shading) and offset errors.
!" Output formats include 12 bit linear, 10 bit linear with shading and offset, or
8 bit gamma corrected, all with 12 bit accuracy.
!" Multiple CCD clocking rates allows matching of CCD clock to scan
resolution and pixel depth for maximum scan speed.
!" Supports 64k, 128k, or 256k x8 external SRAMs.
!" Parallel Port interface supports EPP, PS2 (bidirectional), or SPP (nibble)
modes of operation.
!" Pixel depths of 1, 2, or 4 bits are packed into bytes for faster scans of line art
and low pixel depth images.

25
!" Supports 1 and 3 channel CIS and CCD devices.
!" 3 (R, G, and B) user-programmable gamma correction tables.
!" Able to transmit an arbitrary range of pixels to speed up scanning of smaller
items (business cards, etc.) by zooming in on a subset of CCD pixels.
!" Compatible with a wide range of color linear CCDs and Contact Image
Sensors (CIS)
!" Internal bandgap voltage reference
!" 100 pin TQFP package

Notice that one of the features claim that the LM9830 is compatible with a wide
range of CCD and CIS sensors and that CMOS sensors were not mentioned.
However, as mentioned previously in the discussion of CCD and CMOS sensors,
the only difference to the project is that the LIS-1024 CMOS sensors require a
common clock rate to run and they will each output a voltage value to the R, G, B
inputs of the LM9830 as illustrated in figure 3.7. The SRAM interfacing will be
discussed in section 3.5.

Even though the LM9830 is a chip that is highly regarded, there are some features
that will not be employed. These are Illumination, Stepper motor and the
connection to the printer (Please refer to figure 3.8). Illumination control supplies
light to the image being scanned, due to the complete darkness that is inside a
scanner (enclosed). The Optical Navigation System doesn’t require this feature,
since the hardware device will be placed under the influence of natural sunlight,
which would be enough for illumination purposes. The Stepper motor also isn’t
required, as the Optical Navigation device will be maneuvered by hand, unlike
normal scanners that have motors to control the movement of image sensors.
Lastly, the Optical Navigation System only needs to be connected to the PC,
leaving out the control lines to the printer.

26
 Figure 3.8 LM9830 scanner block diagram

3.4 Transmission
The method of transmitting the data to and from the PC is an important aspect of the
design criteria, even if the developed product doesn’t require real time imaging, the speed
at which the image is portrayed and updated is a deciding factor between a good and bad
navigation device.

3.4.1 The Parallel port

The parallel port is the medium used for transmitting and receiving data for the
LM9830. A PC’s parallel port has eight outputs, five inputs, and four
bidirectional lines. These are enough for communicating with many types of
peripherals, including the LM9830. On many newer PCs, the eight outputs can
also serve as inputs, for faster communications with scanners, drives, and other
devices that send data to the PC. A parallel port transfers multiple bits at once,
unlike a serial port, which only transmits one bit of data each time.

There are numerous modes of parallel ports, with the modern modes being faster
and more reliable. One such mode of the parallel port is the Enhanced Parallel
Port mode (EPP), which the LM9830 uses for high data transfer speed. A more
detailed discussion of EPP is in the following section. The choice of modes can
be found and selected in the BIOS program during the boot-up of a PC.

Unlike many modern scanners, the LM9830 uses the parallel port instead of USB
(Universal Serial Bus), which can only be explained that the LM9830 was
developed in 1998, at a time when USB connectors weren’t common in household

27
 PC’s. The USB connection is a possible future development for the data transfer
medium.

3.4.2 Enhanced Parallel Port (EPP)

The EPP (enhanced parallel port) was originally developed by chip maker Intel,
PC manufacturer Zenith, and Xircom, a maker of parallel-port networking
products. It was developed because the standard mode of the parallel port was too
slow in data transfers, and was limiting the performance of external peripherals.

EPP has a typical transfer rate in the order of 500KB/S to 2MB/S. This transfer
rate is fast enough for the LM9830 to transfer data to the host PC. It is achieved
by allowing the hardware contained in the port to generate handshaking, strobing
etc, rather that have the software do it. An EPP can read or write a byte of data in
one cycle of the ISA expansion bus5, or about 1 microsecond, including
handshaking, compared to four cycles for the standard parallel port.

The data lines are bidirectional in EPP. An EPP can switch directions quickly, so
it’s very efficient when used with disk and tape drives and other devices that
transfer data in both directions. Here are some of the details of the EPP parallel
port:

3.4.2.1 Hardware and addressing

The EPP uses the same hardware as the normal parallel port, as it only differs in
the handshaking as previously mentioned. Table 3.1 illustrates the pin
descriptions of the EPP.

SPP EPP
Pin IN/OUT Function
Signal Signal
A low on this line indicates a
1 Strobe Write Out
Write, High indicates a Read
2-9 Data 0-7 Data 0-7 In-Out Data Bus. Bi-directional
Interrupt Line. Interrupt occurs
10 Ack Interrupt In
on Positive (Rising) Edge.

5
Industry Standard Architecture (ISA). The parallel and serial ports, which used to reside on such cards, are
now integrated into most motherboards

28
 Used for handshaking. An EPP
11 Busy Wait In cycle can be started when low,
and finished when high.
Paper Out Spare - Not Used in EPP
12 Spare In
/ End Handshake
Spare - Not Used in EPP
13 Select Spare In
Handshake
Auto Data When Low, indicates Data
14 Out
Linefeed Strobe transfer
Error / Spare - Note used in EPP
15 Spare In
Fault Handshake
16 Initialize Reset Out Reset - Active Low
Select Address When low, indicates Address
17 Out
Printer Strobe transfer
18-
Ground Ground GND Ground
25
Table 3.1 Pin descriptions for EPP

The EPP uses eight registers; five more than the original parallel port. Table 3.2
shows the registers and their functions. In EPP transfers, the port uses these
additional registers. For instance, to write or read an address byte in EPP mode,
the Address register is used. To write or read a data byte in EPP mode, the Data
register is then used. Address reads and writes use the Address Strobe (pin 17),
whereas Data reads and writes use the Data Strobe (pin 14).

There are also concerns with the EPP timeout bit and direction control, with more
on this in chapter 6. The base address of an EPP is usually at 378h or 278h, and it
can be checked through BIOS or by using the debug command in DOS.

Register Name Address (offset) Read/Write Function/Use

Data port (SPP) Base address + 0 Write Read/Write to data lines
Status port (SPP) 1 Read Bit (0) indicates timeout.
Control port (SPP) 2 Write Contains configuration bits for
EPP.
EPP Address 3 Write/Read Read/Write address cycle with
handshaking
EPP Data 4 Write/Read Read/Write data cycle with

29
 handshaking
(User specify) 5 - User defined
(User specify) 6 - User defined
(User specify) 7 - User defined
Table 3.2 EPP registers and their functions

3.4.2.2 Transfer cycles

EPP mode supports four operations: address write, data write, address read, and
data read. Each has its own unique handshake.

Address write
The following is the description of an address write cycle.
1. Program writes address to EPP's Address Register.
2. Write is placed low. (Low indicates write operation).
3. Address is placed on Data Lines 0-7.
4. Address Strobe is brought Low.
5. Host waits for Acknowledgment by wait going high.
6. Address Strobe is brought high to latch the address.
7. EPP Address Write Cycle Ends.

Figure 3.9 EPP Address Write

Address Read

30
The following is the description of an address read cycle.
1. Program reads EPP Address Register. (Base + 3).
2. Address Strobe is brought low if Wait is Low.
3. Host waits for Acknowledgment by Wait going high.
4. Data is read from Data port lines 0-7.
5. Address Strobe is brought high.
6. EPP Address Read Cycle Ends.

Figure 3.10 EPP Address read cycle

Data write
1. Program writes to EPP Data Register. (Base + 4)
2. Write is placed low.
3. Data is placed on Data Lines 0-7.
4. Data Strobe is brought low if Wait is Low.
5. Host waits for Acknowledgment by Wait going high.
6. Data Strobe is brought high to latch the data.
7. EPP Data Write Cycle Ends.

31
 Figure 3.11 EPP Data write cycle

Data read
1. Program reads EPP Data Register. (Base + 4)
2. Data Strobe is brought low if Wait is Low, whereas Write is brought high.
3. Host waits for Acknowledgment by Wait going high.
4. Data is read from Data port lines 0-7.
5. Data Strobe is brought high.
6. EPP Data Read Cycle Ends.

Figure 3.12 EPP Data read cycle

3.5 Buffer
Due to the different rates of data transfer between the EPP and the LM9830, there needs
to be a buffer of some kind to even out the differences in data rates to allow smooth

32
transfer of data to the PC. In theory, the EPP will have a data rate much higher of the
LM9830’s data output rate. Two ways of solving this problem would be to use a FIFO
chip if the MAX-7000 is used, or to use a SRAM chip as prescribed by the LM9830.

3.5.1 FIFO
One method to eliminate data bottlenecks between high-speed processors, industry
standard buses, memory devices, and Analogue Front Ends involves the use of
First-In, First-Out (FIFO) memory chips.

The AD9822 Evaluation board actually specified to use two FIFO’s chips for data
buffering, using two IDT72261 chips together. However, the Optical Navigation
System is not intended to have vast data handling capabilities such as an
evaluation board, so one FIFO chip was considered to be enough.

The FIFO chip can be seen as a pipe for data. The FIFO collects new samples and
places them in one end of the pipe at a constant sample rate, while the PC retrieves
old samples from the other end as needed.

FIFO chips use the technology of memory arrays to store data that will be
transmitted, with modern devices using CMOS materials to create high speed, low
power FIFO chips. They are quite easy to implement too, with the presence of one
single system clock, ‘synchronous6’ FIFO’s can be easily programmed by setting
up two write and read registers as well as monitoring the status flags within a
FIFO. However, FIFO chips are fairly costly, ranging from AUS $ 15 to $ 507
(The IDT722xx series).

3.5.2 SRAM (Static Random Access Memory)

SRAM is a type of memory that is faster and more reliable than the more common
DRAM (dynamic RAM). The SRAM doesn’t need to be refreshed like DRAM,
therefore given the name static. While DRAM supports access times of about 60
nanoseconds, SRAM can give access times as low as 15 nanoseconds. In addition,

6
Synchronous FIFO’s use 1 common clock, whereas Asynchronous FIFO’s use different clocks.
7
Taken from Farnell electronics 2000 catalogue book 2.

33
 its cycle time is much shorter than that of DRAM because it does not need to
pause between accesses.

SRAM technology works by allowing the data to be read from or written to be

placed on the address pins (common in all SRAM), and then by altering the read
and write control line signals, the SRAM can identify whether the intended
operation is a write or a read.

The SRAM that is incorporated in the LM9830 scanner block diagram resembles
that of a data buffer as well as a storage medium for some fixed data that can be
used in processing the image data; for instance, the SRAM stores the calibration
details such as offset and gain coefficients in the external SRAM.

The SRAM is a cheaper component to use than the FIFO chip. Using the
IS61C1024 1Mega bit chip would cost AUS $23.658. The SRAM is also easier to
implement than a FIFO chip, as it requires one clock source, one power source and
just write/read control lines to be fulfilled. Therefore the SRAM and LM9830
combination was chosen to fill in as the buffer and main processing unit. The
SRAM incorporated into the LM9830 would require no programming, besides
setting up the configuration register for it in the LM9830.

There are different sizes of SRAM that can be used with the LM9830; more details
about the SRAM implementation will be given in the following chapter.

8
Farnell electronic price, 2000 catalogue book 2, under “static” RAM category

34
 Figure 3.13 IS61C1024 SRAM block diagram

3.6 Summary
The component features described in this chapter have been looked upon keeping the
design criteria in perspective. It was decided to use the LM9830 as it incorporates all the
scanner capabilities onto one chip. This way, the design saves money and space, not to
the difficulty of hardware implementation would be reduced. The devices that were
discussed in this chapter have been put into a summary table (Table 3.3). The system was
first broken down into different sets of working modules, therefore the actual design and
implementation that took place may now be discussed. The hardware implementation
follows in chapter 4, while the software implementation is described in chapter 5.

Module Criteria Listings Features

Optical sensor Device that detects
imaging
Signal processor Processor of the imaging
data
LIS-1024 1024 arrays of CMOS
imaging pixels
AD9822, On ADC, AFE, 3 channel
board in LM9830 input to process raw
data from optical
sensors

35
Main processor Controls scanning and Altera MAX7000 MAX7000 uses
transmission NSC LM9830 Macrocells for multiple
purposes, while
LM9830 already has
in-built scanner
capabilities
Buffer Evens out different FIFO FIFO is purely used for
transmission rates SRAM data buffering, while
SRAM can also store
data.
Transmission Medium used to send and Many modes, 500 KB to 2 MB data
medium receive data from the PC. EPP is most transfer speed
desired.
Table 3.3 Summary of different modules of the proposed system design

36
Chapter 4

Hardware Implementation

After deriving the basic set of modules and corresponding components of the Optical
Navigation System in chapter three, the actual design and implementation of the system
hardware is documented in this chapter. A block diagram (Figure 4.1) of the proposed
circuit is first presented, and then the actual implementation of each module is explained
section by section. The schematic and PCB diagrams are used for reference and are
included in the back of this thesis. This then concludes the hardware implementation,
with sufficient detail to proceed with the software design in chapter 5.

4.1 System design

The proposed design for the Optical Navigation System consists of the LM9830 as the
main processing unit, along with the 3 LIS-1024 optical sensors in a triangular array, the
Enhanced Parallel Port as the transmission medium and SRAM as the buffer for data
transmissions. The reasons for choosing the LM9830 and associated peripherals have
been discussed in the previous chapter. Figure 4.1 represents the system’s block diagram.

4.1.1 Schematic design

The schematic design involved using the ProtelTM 98 design software package.
Before the complete schematic was drawn, the diagrams for the SRAM, LM9830
and LIS-1024 had to be created accordingly because the normal Protel library
didn’t hold information of such components. The divided modules are in the
following sections, and their connections to the LM9830 are documented in these
sections. The schematic design is part of appendix A at the back of this thesis.
Just before the preceding sections begin, please note that the terms VCC, VAA
and ground refer to Digital voltage, Analogue voltage and 0 voltage (common
reference point).

37
 DB25

17 lines

3 output lines
SRAM
Sensors
28 bi-directional read-write lines
LM9830
6 control lines

Caps & Inductors minimize ripple

48 MHz CLK

5V Power

Figure 4.1 Block diagram of system design

4.1.1.1 Parallel port

The parallel port connections are quite straight forward, from which the pin
descriptions of the LM9830 follows the pin names of the Standard Parallel Port
(SPP), but the mode which the system would use is the Enhanced Parallel Port
(EPP). The physical pin connections are standard upon all modes, only the

38
 handshaking between the PC and the LM9830 differ from that of SPP. As
mentioned in the introduction of EPP, the hardware does all the necessary
handshaking automatically, without the user needing to put in extra hardware for
the EPP mode. The parallel port has 8 data lines, 8 ground lines and 9 control
lines. Table 3.1 lists the pin connections from the parallel port to the appropriate
signal name on the LM9830.

4.1.1.2 SRAM
The IS61C1024 SRAM consists of 1,048,576 bits of high-speed static RAM
organized as 128 Kbytes x 8. The LM9830 actually specified to use either three
SRAM sizes; 64KBytes x 8, 128KBytes x 8 or 256 Kbytes x 8.

The 128KByte option was chosen because this was enough to achieve 600 dpi
(Dot per inch) resolution, which is the same amount of resolution that can be
achieved by using a 256KByte x 8 SRAM. However, the price is the major factor
here; while the IS61C1024 SRAM costs AUS $23.659, the 256KByte choice is
AUS $5510. The IS61C1024 has access times of 15ns, which is also why the
IS61C1024 was chosen over some other manufacturers that make SRAM chips.

The IS61C1024 has 17 Address decoder pins, 8 I/O control pins and 4 control
logic pins. The Address and I/O pin connections are straightforward. The
Address pins A0 to A16 are directly connected to the A0 to A16 pins on the
LM9830, note that there is a label ‘A17’ on pin 22 of the LM9830, this is the
additional Address pin allocated for 256KByte SRAM’s, so it can be left floating.

The I/O control pins are connected accordingly to the DB0 to DB7 pins of the
LM9830. According to the truth table, the CE1 and CE2 pins always remain low
and high whether they’re reading or writing data. Therefore, it is appropriate to tie
the CE1 pin to ground and the CE2 pin to VCC (5 volts). Pin WE is the control
signal for writing data, therefore it is connected to pin WR (pin 34) of the LM9830,
and OE is connected to pin RD (pin33) of the LM9830, since it is the read data

9
Farnell electronics price, pp. 1916 in book2, catalogue 2000
10
RS-components price, Farnell electronics didn’t have this category of SRAM available

39
control signal. Their operation during read and write are automatically controlled
by the LM9830 after setting up the appropriate configuration registers.

Table 4.1 Truth table of operations for the IS61C1024

4.1.1.3 Optical Sensors

Having discussed the decision to employ CMOS imaging sensors rather than CCD
sensors, the key features of the LIS-1024 can be discussed, as well as its
connections to the LM9830.

The theory behind the imaging is that the sensors will scan sequentially, as the
calculations at each pixel will be done sequentially too. Therefore the previous
pixel value along the 1024 array is discarded, that is, each pixel is sequentially
reset after reading it. This is utilized by using the sequential read-Dynamic Pixel
Reset (DPRTM) mode available on the LIS-1024. Implementing this mode means
that each pixel has the same integration time, which is important, so the values
read are consistent and accurate for the calculations done on the PC.

Referring to the time cycle figure for this mode, it is obvious that the RMS pin is
held high throughout the cycle, and referring to mode 2 of the truth table, the PRE
pin on the LIS-1024 can be either high or low, so it was decided to tie it to ground.

40
 Table 4.2 Truth table for the LIS-1024 modes

Figure 4.2 Sequential read – Dynamic Pixel Reset time cycle

The RST pin of the LIS-1024 is the reset pin, and it is tied to the LM9830’s TR1
pin. The TR1 pin is specified as a digital output and it contains the transfer pulses
for the LIS-1024, so once a transfer pulse is detected, the LIS-1024 will be in reset.

The three LIS-1024 sensors share the same clock source, so they will be clocked
simultaneously from the φ1 output of LM9830. Note, that to prevent the sensors
from saturation11, the LM9830 always clocks the image sensor except when in
reset or standby mode. The output voltage, or the raw image data, is outputted via
two 0.1uF capacitors in parallel, and sent to the Red, Green, Blue inputs (OS-R,
OS-G, OS-B) of the LM9830. The reason to place the capacitors are to minimize
ripple voltage from the sensors, and to prevent damage done to the Red, Green and
Blue inputs of the LM9830. The Optical Navigation System was not intended to
portray scanned images in colour, so the intended use for these R, G, B inputs on
the LM9830 are for the calculation of position. The voltage required is tied to
VAA, as the sensors are not part of the digital circuitry.

11
When the charge within an pixel is full (full well), this pixel cannot accommodate anymore charge and
causes erroneous results

41
 4.1.1.4 Other connections
The clock used by the LM9830 is specified to be at 50MHz, however, it has been
changed to 48MHz because the Master Clock (MCLK) of the LM9830 is set to
divide the 48MHz clock source by four, so the internal clock cycle of the LM9830
will be at 12MHz. It is specified that the clock frequency for the LIS-1024 be
within 12MHz, otherwise the signal-to-noise ratio will degrade so that is why a
lower frequency clock source is more suitable.

To limit the use of external components in the design, a TTL12 clock module13 was
used. Therefore to use an external clock module, the ‘CLK_SEL’ pin had to be
tied high, whereas the ‘CRYSTAL IN’ pin had to be tied low. By doing so, the
output from the clock module is driven into the ‘CRYSTAL OUT’ pin on the
LM9830.

Referring to the schematic, there are many capacitors connected in parallel to

some sort of voltage source (VCC or VAA) and then to ground. These capacitors,
along with the aid of 2 inductors maintain the quality of the supply voltage and
current. The values of the inductors had to be chosen carefully, as every inductor
has its own self resonating frequency14, and a wrong value chosen will cause the
inductor to self resonate like a clock crystal. The inductors chosen were to be
2.2uH each, one to smooth ripple current for VCC and the other for VAA.

4.1.2 Printed Circuit Board (PCB) design

The PCB designed was based on the schematics in appendix A. The footprints for
the LM9830, IS61C1024, 2.2uH inductor, 33uF capacitor and 10uF capacitor had
to be individually created according to their manufacturer’s details. The other
components were of standard ProtelTM library footprints. Some design
considerations had to be taken into account, especially regarding the integrity of
the power and ground connections on the PCB. Finally, the designed PCB is
placed in appendix B, including the top and bottom view.

12
Transistor-Transistor logic
13
Every component (resistors and capacitors) on a standard clock circuit is integrated into one component
14
Maximum frequency rating that can be handled by an inductor where it will start to resonate like a clock
crystal if this frequency is exceeded.

42
 4.1.2.1 Design considerations
The design of the PCB had to be carefully considered because the effects of
voltage and current ripple may affect the functionality of the LM9830. Therefore
the placement of capacitors was an important factor. They would need to be
placed as close to the pin outs of the LM9830 as possible. The ideal case is to
have a short wire coming out of a pin, connected straight to a via15, and then
connected to a capacitor on the bottom side of the PCB. The optical sensors were
placed near the top of the PCB; this is because it is using a different voltage source
(VAA) than the digital circuitry of the LM9830 and IS61C1024 (VCC). Therefore
it was safer to create some distance between the LM9830 and the sensors so the
two different voltages would not interfere with each other.

4.1.2.2 Importance of Ground and power connections

The ground, VAA and VCC tracks were made to a thickness of 0.8mm, to reduce
the effect of power surges from the power supply. The thicker tracks can also
accommodate a smoother power transfer characteristic for tracks that are longer in
length, i.e. VAA, VCC and ground.

Ground planes were placed under the LM9830, LIS-1024 optical sensors, 48MHz
clock module, as well as the region where the parallel port takes place. This
ensures that power can be dispersed on the board with the minimal distance of
travel required.

4.2 Mechanical layout

The mechanical layout of the Optical Navigation System mainly consists of the
PCB, two wires to connect the power supply, a DB25 parallel port that requires an
external cable to connect to the PC and a 35mm camera lens setup to focus the
LIS-1024 sensors to the ground. There are plans to place the PCB into a case with

15
Shaped as a hole, it links the wiring on the top and bottom surface of a PCB.

43
peripherals attached, and to place four wheels on each corner of the case so the
Optical Navigation System can be wheeled along ground surfaces. However,
these plans have not been able to take place due to the time conceived on the
development of the hardware and software.

4.2.1 Lens
The lens that will be used is 35mm in size, and can create a larger imaging area for
the LIS-1024. The footprint of the lens can be seen on the topside of the PCB, as
there are four drill holes to secure the lens in place. The lens are placed a few
millimeters below the LIS-1024 for optimal vision onto the ground.

4.3 Summary
The hardware components, connections, peripherals, schematics and PCB have
thus been discussed and developed. Commencing with the overall system criteria
of specifications, the hardware has been designed and implemented by individual
modules. The PCB was made and basic testings such as power transfer has been
conducted, so the software design and implementation can now be discussed.

44
Chapter 5

Software implementation

Chapter 4 has outlined the proposed hardware implementation of the Optical Navigation
System, so therefore it is possible to derive the software control of the hardware.
There are a number of distinct programs running on the Optical Navigation System, but
the main responsibility of the software is to initialize hardware, setup the required
registers, scan and to transmit data to the PC. The data that is sent to the PC is then stored
into the hard-drive and processed to display images of the scanned surface.
The software coding on the PC mainly consists of digital signal processing, that is, using
the techniques of Cross Correlation16 and mathematical methods such as Fast Fourier
Transform17 to display images. This part of the software was performed by Mr.Tien-Lung
Lee as part of his thesis.

5.1 Initial considerations

The hardware programming of the Optical Navigation System would require some
kind of programming language that is easy to understand to avoid unnecessary
complexity, therefore the universal C language was chosen. The primary
responsibilities that the software would need to perform have been discussed
previously, and these control programs would be sent via the parallel port interface
to the LM9830. The PC does all the controlling of the Optical Navigation System,
so there isn’t any software required to load into the LM9830.

5.2 Programming the Enhanced Parallel Port

The time diagrams of the EPP have been shown in figures 3.9 to 3.12 and the table
of registers in table 3.2. However, the control signals of the EPP have yet to be
mentioned, so a brief discussion on the process of EPP programming will be
followed by its link to the LM9830.
16
Digital signal processing, refer to Mr. Tien-Lung Lee’s thesis more details
17
Mathematical method for digital signal processing, is the faster variation of the normal Fourier Transform

45
 5.2.1 Switching directions
In EPP mode, changing direction doesn’t require special handshaking of the
control signals. Therefore, referring to table 3.1, when the nWrite pin is low, the
Optical Navigation System hardware disables the data outputs 0-7 so the PC can
write to the hardware, and then the hardware responds by reading the data pins 0-7.
Oppositely, when nWrite is high, the PC disables its data outputs so the system
hardware can write to the PC. Although not specified in IEEE 128418, the PC’s
EPP hardware automatically controls the nAddress Strobe or nData Strobe output,
enables or disables data when appropriate and monitors nWait input to check if the
system hardware is ready for another transfer.

Another thing that is important in EPP transfers is to set the direction of the port
correctly. The fifth bit of the control register (figure 5.1) selects whether the
parallel port on the PC is a write or a read. Before initialising EPP cycles, it is
essential to place the PC parallel port to a write, so the nAddress Strobe, nData
Strobe, nWrite and nReset lines are inactive, high. Writing xxxx010019 (0x04)20
to the control registers achieves this.

* Data Register (base + 0) (Write)

*
* 76543210
* . . . . . . . …...* D0 ........... (pin 2), 1=High, 0=Low (true)
* . . . . . . …..* D1 ........... (pin 3), 1=High, 0=Low (true)
* . . . . . ….* D2 ........... (pin 4), 1=High, 0=Low (true)
* . . . . …* D3 ........... (pin 5), 1=High, 0=Low (true)
* . . . ...* D4 ........... (pin 6), 1=High, 0=Low (true)
* . . ..* D5 ........... (pin 7), 1=High, 0=Low (true)
* .* D6 ........... (pin 8), 1=High, 0=Low (true)
* * D7 ........... (pin 9), 1=High, 0=Low (true)

* Status Register (base + 1) (Read)

18
IEEE 1284 is the standard describing the EPP bidirectional parallel port.
19
Binary representation
20
Hexadecimal representation

46
 * 76543210
* . . . . . * * * Undefined
* . . . . * . . . Error ............(pin 15), high=1, low=0 (true)
* . . . * . . . . Selected ..... (pin 13), high=1, low=0 (true)
* . . * . . . . . No paper .....(pin 12), high=1, low=0 (true)
* . * . . . . . . Ack ............. (pin 10), high=1, low=0 (true)
* * . . . . . . . Busy ......... (pin 11), high=0, low=1 (inverted)

* Control Register (base + 2) (Write)

*
* 76543210
* . . . . . . . ……* Strobe ................(pin 1),1=low, 0=high
* . . . . . . …..* Auto Feed ......... (pin 14), 1=low, 0=high
* . . . . . ….* Initialize ............ (pin 16), 1=high, 0=low
* . . . . …* Select In............. (pin 17), 1=low, 0=high
* ..* Input/Output....... 1=Input, 0=Output
* **.* Unused
Figure 5.1 EPP control signals for DB25 parallel ports

5.2.2 Clearing timeouts

IEEE 1284 doesn’t specify it, but Status register bit 0 is a timeout bit that indicates
a failed EPP transfer. This happens when a falling edge on a strobe input doesn’t
cause the system hardware to bring nWait high within 10 microseconds. If a
timeout occurs, it means that the transfer cycle was erroneous, which would
indicate a high for this timeout bit. It needs to be cleared before another EPP
transfer can begin. The method to clear the timeout bit is as follows; write a 1 to
status register bit 0, followed by a 0, after the two write cycles, read the status
register twice in succession to clear the timeout bit. A common scenario of the
EPP port being affected by this timeout bit is always reading 0xFF from the
Address or Data registers.

5.3 LM9830 control

The LM9830 control software will be broken down to the following modules, with
the initialisation and setup of configuration registers in the first module, followed
by the scanning process and reading of data modules. The parallel port

47
programming considerations have to be in taken into account for of the modules,
as the LM9830 requires EPP timing cycles with all of its communications with the
PC.

5.3.1 Module 1 (Initialisation & setup)

This part of the module documents the coding required to setup and initialise the
LM9830. The C code is documented in appendix C.

5.3.1.1 initialise the LM9830

For the PC to be ready to communicate to the LM9830, the LM9830 must be
brought from transparent mode (after power up), to a “wake up” mode, where all
the processes can occur. In order to wake the LM9830, the PC sends a sequence
of data onto the data pins of the parallel port through SPP mode without changing
any of the 4 control line signals (Strobe, Autofeed, Initialise and Select In). The
sequence of data is 99, 66, CC, 33. There is a delay of 100 milliseconds placed
between each data sequence to assure the data transfer isn’t too fast in case the
LM9830 misses one of the data sequences. Once the LM9830 is woken up, it is
necessary to reset it, because the PC will not know what state it has woken up in.
To reset the LM9830, register 7 of the configuration registers needs to be written
(0x08), followed by (0x00) to return to idle.

Note that these transfers use EPP timing, unlike the initialisation process from
before. The PC write command requires the PC to send the configuration register
address through the EPP address register, and then send the data that needs to be
written into this address through the EPP data register to the LM9830. For the PC
read command, the configuration register address of the LM9830 is written first
through the EPP address register, and then the direction of the port is set to a read
by changing bit 5 of the parallel port control register. After each cycle, the EPP
timeout bit is cleared to ensure that the data transfers are correct. Therefore there
are two special functions to cater for writing registers and reading registers. These
two functions will be used for all the communication of registers to the PC.

5.3.1.2 Setup configuration registers

48
Out of the 128 configuration registers of the LM9830, some may be set up before
the scanning process proceeds, while other registers that will not be used are left
blank. These registers that need to be written beforehand will not include
information that needs to be changed throughout the scanning process. The
registers that have higher importance are listed in table 5.1. Please refer to the
related program in appendix C for the register setups, they are commented to aid
in understanding.

Register Address Value written (hex) Function

08 0x06 The master clock frequency is set to
12MHz
09 0x38 12 bit data from the ADC is sent
before processing, horizontal dpi is
set to 1
0B 0x08 Set the sensor resolution to 600dpi
0D 0x21 To set the clock and reset pulses for
the sensors active
26 0x18 To set the AFE to 3 channel pixel
rate, more on this later
42 0x06 Set the parallel port to EPP
43 0x1D Set the SRAM size to 128 Kbytes
and enable full duplex transmission
70 0x70 Parallel port noise filter
71 – 7F 0x00 Datasheet specification
Table 5.1 Listing of significant registers setup before scanning

5.3.2 Module 2 (Scan & read data)

This part of the module documents the coding required to scan and read data from
the LM9830. The C code is documented in appendix C.

5.3.2.1 Scan

49
Within the scanning process, there are some factors of the LM9830 that need to be
discussed.

To maximise scanning speed and image quality, pixel processing of the sensor’s
data can assist in the quality of the data sent to the PC. To initially test the
integrity of the LIS-1024 optical sensors and the LM9830, images are scanned in
12-bit mode, which can only be done at the optical resolution of the LIS-1024.

This mode is used to acquire 12 bit data for accurate gain and offset calibration,
and for applications requiring maximum resolution data. The horizontal dpi must
be set to one to get 12 bit data. The shading and offset functions must also be
disabled by writing 0 to registers 3E, 3F, 40 and 41. The output data is formatted
as in figure 5.2, where one 12-bit data is formatted into two separate Bytes.

Figure 5.2 12-bit mode pixel data format

Another method in maximising scanning speed is to determine the most efficient

number of bits in each Byte of data that is transmitted to the PC. Therefore, to get
as much resolution and transmission speed, 8 bits per pixel are packed, resembling
a sequence similar to figure 5.3. Note that the unit for pixel depth of figure 5.3
represents bits/pixel. “b7” is the most significant bit while b0 is the least
significant bit. “p0” is the start of an original pixel sequence.

Figure 5.3 Pixel packing into one Byte

The control of the LIS-1024 optical sensors will be performed by the TR1 pulse
from the LM9830. In register 0E, it is required to setup the TR1 pulse duration
and the TR1-φ1 Guardband duration. This is set to zero initially, to allow the

50
sensor to be set as a reference for future calibrations. This setting causes TR1 and
φ1 to go high simultaneously and low simultaneously.

Figure 5.4 TR1-φ1 guardband equal to 0

The Analogue Front End of the LM9830 allows the operation of 3-channel pixel
rate mode. In this mode, all three channels (R, B, G) are converted with the
multiplexer in front of the ADC switching at the ADC conversion rate (6 MHz),
producing interleaved RGB data that is transferred to the IS61C1024 SRAM.
With this interleaved data that is being sent, the PC can now process this data
because it represents the point coordinates of each three sensors at the same time
interval.

Figure 5.5 3-channel pixel rate mode

The SRAM access mode is selected to 12bit/8 slot to accommodate full duplex
transmission of 12 bits, as mentioned previously. The 8 slot modes have higher
bandwidth and can be used with high speed SRAM, such as the IS61C1024 which
has 15-nanosecond access time. The offset and gain coefficients stored in the
SRAM are set to 6 and 10 bits respectively. These coefficients ensure that the data
being processed has a certain degree of accuracy. Figure 5.6 illustrates the data
format for the 12-bit/8-slot SRAM access mode.

51
 Figure 5.6 12-bit/8-slot SRAM access mode

This mode allows the host to read pixel data from the SRAM while scanning,
which is a key factor in performance speed.

Previously, the SRAM function of storing data processing coefficients was

mentioned. The line buffer feature of the LM9830 allows the SRAM to behave
like a transmission buffer that was part of the block diagram in figure 3.1.

The line buffer uses the SRAM to store the pixel data at a fixed rate and sends it
back to the PC at an asynchronous, unpredictable, and non-constant rate. The
buffer was intended to be coupled to the stepper motor so in a situation where the
buffer overflows, the motor is stopped (hence scanning is stopped) until the buffer
nears empty. In the case of the Optical Navigation System, because no motor is
attached, the scanning procedure will be halted until the buffer is near empty again.

The situation where the line buffer would start to fill up is when the LM9830 is
generating pixel data faster than the PC can acquire it. As the buffer nears 100%
full, the scan is paused before it can acquire the next line to store due to the lack of
storage space in the SRAM. Therefore, there is a Pause Threshold limit (register
4E) that needs to be programmed. Since the Optical Navigation system uses three
sensors with three outputs, this register is set to pause when the line buffer is
94KBytes full. After a pause, the buffer will now transmit data to the PC until it
hits the Resume Threshold limit (register 4F). This register is set to resume
scanning when the line buffer is 50Kbytes full.

52
 Figure 5.7 Memory map for IS61C1024 SRAM (numerical figures in Bytes)

Having discussed the major factors that will affect the scanning process, the
scanning process can now be discussed in full. An image scan is started by setting
the Scanning bit in configuration register 7. The line buffer is reset automatically
when the Scanning bit is set, not when it is cleared. The PC can continue to read
stored data when scanning has been paused or stopped. If for some particular
reason the Optical Navigation System needs to be paused, the LM9830 can allow
pauses in scanning and can resume scanning later. All that needs to be done is to
put the LM9830 to idle (configuration register 7) and stop reading pixel data. The
pixel read configuration register (00) is the register where the PC reads the
processed data. More on the read data operation in the next section

5.3.2.2 Read data

The LM9830 pixel data is read from the configuration address 00. The host
latches address 00 into the LM9830’s address pointer. Subsequent reads from the
host will read the next Byte of pixel data stored in the line buffer. Figure 5.8 is the
time diagram that illustrates this. Please note that each pixel data is stored in the
SRAM and transmitted to the PC in two Bytes, a high Byte containing the 4
MSB21 of the pixel and a low Byte containing the 8 bit LSB22 (post processing),
please refer to figure 5.2 for the data format.

The program included in appendix C is for a fast read upon configuration register
00, which is just writing the address 00 and reading from it continuously, since it
is desired to achieve a transmission rate (hence scanning pace) as fast as possible.

21
Most Significant Bit
22
Least Significant Bit

53
 Figure 5.8 Reading pixel data (EPP)

5.4 Summary
This chapter has presented the design and theory behind the LM9830’s software
components of the Optical Navigation System. The various modules of software have
been considered, from initializing the LM9830, setting up configuration registers,
scanning and reading data to the PC. With the software design and coding put together
with the hardware design and implementation, the design of the Optical Navigation
System can be considered to be completed. In the following chapter, a review of the
Optical Navigation System is presented. This review will reveal which aspects of the
Optical Navigation System have been successful, the aspects that need correcting, and the
possibilities of future developments for the Optical Navigation System.

54
Chapter 6

Design Review

Having completed the design of the Optical Navigation System in Chapter 4 and Chapter
5, it is appropriate to assess the development of the project. The status and performance
of each component module will be discussed in order to provide an indication of exactly
how much progress was made. This analysis will reveal to what extent the actual design
has approached the intended design, and will give some idea of the relative success of the
project. Finally, some future enhancements for the optical Navigation System are
suggested for further development.

6.1 Status of project

Substantial progress had been made towards the final completion of the Optical
Navigation system during the period of writing this thesis, however full functionality has
not been achieved hindered by several delays. The status of the project is presented in
two separate sections, the hardware and software.

6.1.1 Hardware
The schematic and PCB design have been discussed in chapter 4, and in the course
of writing this thesis, Mr. Fred Hamilton from National Semiconductors was able
to provide the author with a software package called “Merlin Bench” to test the
designed PCB. The results from the test were positive, with communications,
initialisation, scanning and retrieving image data fast. However, the actual display
of the scanned surface didn’t come up very well, with the system only being able
to distinguish light and dark surfaces.

There are numerous factors that could have contributed to the scanning error, and
that being that the LIS-1024 sensors could not be “homed”(set to start), possibly
because the TR1 pulse should not have been used as the reset pulse for the LIS-
1024 sensors. There has not been enough time to wait for another PCB to conduct

55
 this test, but it is the only doubt of the hardware with the amount of testing done
so far.

The routing of the PCB was a long process, since the LM9830 package was very
small and allowed minimal space for routing near its pins. The routing of the PCB
was done partially in manual route with autoroute.

The soldering of components onto the PCB was often a tricky and time consuming
process, specially with the LM9830 being so small, the university workshop didn’t
have the right equipment to deal with it, so a lot of unnecessary fiddling was spent
on it.

6.1.2 Software
The software development of the Optical Navigation System has been completed
and included in appendix C, but the communications in EPP have been erroneous
and could not be resolved in time. The only part that the software can achieve is
initialising the LM9830 through SPP registers. The software coding had been
reviewed many times, even compared with the Merlin Bench source code, and the
only problems that happened were the toggling and handshaking signals between
the PC and Optical Navigation System. The basic idea of writing the address byte
to the address register of EPP and the data byte of this address to the EPP data
register were the same between the code written and that of the Merlin Bench.

The failure of the software to perform as desired can be attributed to the late
development of the PCB, as well as the complexity involved with the EPP
programming.

6.2 Performance evaluation

Due to the software not being able to provide the necessary communications, the
performance could not be evaluated in comparison to the criteria listing in chapter 2. The
PC was able to read what it wrote out, but it cannot read the results from the LM9830.
Furthermore, the registers weren’t written properly either, because during testing, if

56
configuration register 59 was written with 0x99, pins 64 and 65 should output a high that
can be detected by a CRO. This was evident while using the Merlin Bench, with other
signals such as sensor clock signal, CDS test signal all being able to be detected on the
PCB. Unfortunately due to the lack of time, the source code of the Merlin Bench couldn’t
be understood fully, however, the EPP transfer codes were the same as in the Merlin
Bench code, so the errors can be limited down to
1. The control signals are not behaving like they should, therefore there must be
some missing code involved with the EPP transfers.
2. The Merlin Bench actually drives the parallel port to EPP upon startup, so the
BIOS setup may not be correctly set. There wasn’t enough time to evaluate this
code in the Merlin Bench, however, if time permits, the code may be rectified for
the EXPO demonstration.

6.3 Future developments

The Optical Navigation System can be further developed to accommodate colour imaging
and with the use of USB transmission medium. The later revisions of National
Semiconductor’s “scanner on chip” series includes USB interfacing in-built into the chip,
and with the wide range of sample software code in the internet for USB interfacing, this
task shouldn’t be overly difficult to implement. These two improvements may serve as
possible immediate developments for the Optical Navigation System. The Optical
Navigation System can also be used in conjunction with a GPS system, with the Optical
Navigation System playing more of a scanning role rather than a navigation tool.

57
Chapter 7

Conclusion

The design and development of an Optical Navigation System that can achieve short-term
stability at a reasonable price has been presented in this thesis. The concept of using three
optical sensors in a triangular array along with the scanner chip LM9830 has not been
capable of providing a “proof-of-concept” demonstration, due to the failure of
communication between the Optical Navigation System and the PC. The majority of the
design had been properly built and tested, however, there still are some aspects of the
project development which are incomplete, therefore this project may be considered
partially successful in terms of hardware. Several areas in which the existing design may
be improved have been outlined, as have a number of directions in which the design may
be extended in the future.

58
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