#CLUS

Cisco ASR 9000

System Architecture
Yongzhong Peng
Manager, Technical Marketing
BRKARC-2003

#CLUS
Agenda

• ASR9000 Products Introduction

• ASR9000 System Hardware Architecture
• ASR9000 Distributed Control Plane
• Data Packet Processing & QoS
• IOS-XR & IOS-XR 64 Bit
• Conclusion

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ASR 9000 Products
Introduction
Cisco ASR 9000 System Comprehensive Portfolio
Compact & Powerful
Access/Aggregation
• Small footprint with full IOS-
XR for distributed
environments
nV Satellites
ASR 9000v, NCS5000
High Density Service Edge
Flexible Service Edge
and Core
• Optimized for ESE and MSE with high • Scalable, ultra high density
M-D scale for medium to large sites service routers for large, high-
growth sites
One Platform, One OS, One Family
ASR 9922
ASR 9912

ASR 9010 ASR 9910

ASR 9901
ASR 9906
ASR 9006
456Gbps
ASR 9904
ASR 9001

Fixed 2RU 2 LC/6RU 4 LC/10RU 4 LC/14RU 8 LC/21RU 8 LC/21RU 10 LC/30RU 20 LC/44RU

240 Gbps 16 Tbps 7 Tbps 32 Tbps 14 Tbps 64 Tbps 80 Tbps 160 Tbps

MSE E-MSE Peering P/PE CE Mobility Broadband

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ASR 9901 Highlights
Form Factor & BW Ports / Port Density
• 2 RU box with 2 Tomahawk NPU • Fixed ports available; no MPAs
(ASR 9001 is 2 RU with 2 • 42 ports on the faceplate : 16X1G,
Typhoons) 24X1/10G, 2X100G(QSFP28)
• Depth of ~23 inches,(9001 is 18”) • 1G ports : LAN & MACSEC
• 456G Duplex BW 10G ports: LAN & MACSEC
(9001 is 120G Duplex) 100G port : LAN & MACSEC

SW & Licensing Mechanicals & Commons

• Redundant Power & Fan-trays
• 64 bit XR only
• Front to back Airflow
• PAYG mode for 120G,240G,360G
and 456G • NEBS, EMC Compliant
• All ports/power cabling on front
• Full feature parity with Tomahawk plate; fan trays on backside
feature-set
• Typical Power Consumed : 1200W

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 Cisco ASR 9906 Overview

 Scalable for Dense 100GE

Applications for future investment 2 Fan Trays
protection
4 Line Card
Slots
 Greater Capacity, Greater Flexibility:
2 RSPs
Start with 2 RSPs, then add fabric
cards to scale beyond 460G and 5 Fabric
Cards
enable N+1 fabric redundancy
1 Power
Tray
 Mid-Plane design allows for compact
chassis footprint

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Edge Linecard Silicon Evolution
1 st Gen
Trident
Class Trident Octopus Santa Cruz PowerPC
120G 90nm 130nm 130nm Dual Core
15 Gbps 60 Gbps 90 Gbps 1.2 Ghz

2 nd Gen
Typhoon
Class Typhoon Skytrain Sacramento PowerPC
360G 55nm 65nm 65nm Quad Core
60 Gbps 60 Gbps 220 Gbps 1.5 Ghz

3 rd Gen
Tomahawk
Class Tomahawk Tigershark SM15 X86
800G 28nm 28nm 28nm 6 Core
240 Gbps 200 Gbps 1.20 Tbps 2 Ghz

4 th Gen
LightSpeed
Class LightSpeed SKB X86
3.2T 16nm
400 Gbps
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 ASR 9K Ethernet Line Card Overview

MPAs
20x1GE MPAs
2x10GE 1x100GE
4x10GE 2x100GE
1x40GE 20x10GE
2x40GE

3rd LC Tomahawk
NPU: 240Gbps,
~150Mpps

-TR, -SE
MOD400/MOD200
A9K-8x100GE
A9K-4x100GE A9K-48X10GE-1G
A99-12x100GE A9K-400G-DWDM
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Cost Optimized 4x100GE LAN Line card

• Tomahawk based, 5-fabric linecard with: 2x NPU and 5Mbit internal TCAM
HW Specs
• Supported on all ASR 90xx and 99xx systems

• Parity with Tomahawk TR linecards at FCS except for Timings features (post FCS)
Features
• Features not supported: VidMon, Cluster, LISP, NSH, BNG, Satellite, MPLS-TP

• Limited scale for TCAM dependent features; rest of the scale on-par with other Tomahawk –
Scale TR cards

• cXR: 6.2.3, 6.3.2, 6.4.1 and onwards. SMU option possible for 6.1.4, 6.3.1, subject to business
SW support case
• eXR: 6.4.1

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Dual-rate dense 10G/1G Tomahawk LC
A9K-48x10G-1G – Enables easy migration from Typhoon

Ultra-Dense dual rate

1G/10G fixed line card.
Powered by Tomahawk Price and power
Available in 24-port and
48-port versions
NPU & ASICS optimized LC
(Oversubscribed)

• Supports 1G, 10G Dual Rate
• Feature and scale parity on PAR with • Ideal low cost replacement
Typhoon LC with minimal exceptions for both fixed and modular
• No OTN/MACSec Typhoon LC
• Support for all SFP+/SFP • PAYG consumption model
• 64bit XR capable available
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ASR9000 Hardware
Architecture
 ASR 9000 System Architecture “At-a-Glance”
Control plane split
RSP/RP Network Processor
among RSP/RP
and LC CPU
CPU

RSP FIA
CPU CPU
NP Bay

Network Processor CP
BITS/DTI
U
Switch SerDes
FIA Fabric XBAR

FIC
CPU
CPAK

CPAK
PHY
NP FIA FIA NP Bay

CPAK

CPAK
PHY
NP FIA
Switch
CPAK
Fabric Line Card
CPAK
PHY
NP FIA
CPAK

CPAK
PHY
NP FIA Fully Distributed Architecture for
High Performance and High Multi-
Data forwarding is fully Switch Fabric dimensional Control Plane Scale
distributed across NPs
Active-Active Switch Fabric
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 ASR 9000 Switch Fabric Overview
Separated fabric card
Integrated + Separated 6+1 redundancy
Fabric is integrated on RSP
Fabric
6+1 redundancy
Integrated fabric/RP/LC
9904
RSP880: 1.4T/slot
9901 2RU, 456G

9906 9910
1.2Tb+200G /slot
9912 9922

9006 9010 1.2Tb+200G /slot

RSP880: 400G+400G /slot

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 ASR 9000 Switch Fabric High-Level Architecture
3-Stage Non-Blocking Fabric (Separate Unicast and Multicast Crossbars)
Fabric frame format:
Super-frame Stage 1 Stage 2 Stage 3
Fabric load balancing: Active-Active
Unicast is per-packet Fabric
Multicast is per-flow Unicast
Virtual Output Queue Crossbar
Arbitration fabric

fabric fabric
Arbiter FIA
FIA Multicast FIA
FIA RSP0
Crossbar FIA
FIA
Tomahawk
Tomahawk LC
fabric Egress Linecard
Ingress Linecard
Arbiter

RSP1
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ASR99xx Switch Fabric Card (FC2)
6+1 All Active 3-Stage Fabric Planes, Scale to 1.6Tbps/LC, Separated Ucast/Mcast Crossbars

5x 2x115G bi-directional 7x2x115G bi-directional

= 1.15Tbps = 1.6Tbps

5-Fabric LC 7-Fabric LC

FIA
FIA
FIA Fabric Fabric FIA
SM15 SM15 FIA
FIA
Tomahawk Line Tomahawk Line
Card Card

Fabric frame format:

Super-frame Fabric bandwidth:
Fabric load balancing: 10x115Gbps ~ 1.15 Tbps/slot with 5x FC2
Unicast is per-packet SFC v2
Multicast is per-flow 14x115Gbps ~ 1.6 Tbps/slot with 7x FC2

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Tomahawk LC: 8x100GE Architecture
Slice Based Architecture
VoQ buffering, Fabric credits, mcast LC CPU
FPOE, Auto-Spread,
L2/L3/L4 lookups, all VPN types, all hashing, scheduler for fabric and
CPAK: Macsec Suite B+, G.709, OTN, DWRR, RBH, replication
feature processing, mcast replication, egress port
100G, 40G, 10G Clocking
QoS/Queuing, ACL, etc …

240G 240G
Tomahawk
PHY FIA Up to
NP 14x115G

Separated Switch Fabric

240G 240G
Tomahawk
PHY FIA
NP

XBAR
240G 240G
Tomahawk
PHY FIA
NP

240G 240G
Per Slice Power Management:
PHY
Tomahawk
(100-200W Power Savings)
Tigershark
PE1(admin-config)# hw-module NP
power saving location ? sliceFIA
[0-3]

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4x100GE LAN-based linecard architecture

Interlaken
2x 16x 10.9375G 2x 8x15G = 240G raw bw
= 350G raw bw 3x Fencer ports

QSFP 0

QSFP 1
PHY NP FIA
CPU

Switch
Fabric
(SM15)
QSFP 2

QSFP 3
PHY NP FIA
Up to
10x115G

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 ASR9901 System Architecture
Similar to A9K-48X10G-1G-SE Tomahawk
Line Card

NPU: 2x NP5c | Mem: 12 GB DDR3

TCAM: External Shared 80Mbit (40Mbit / NP)

RSP & LC CPU: 4-core Broadwell 2.4Ghz each

Memory: RP - 32GB DDR4 | LC CPU - 16GB

DDR4

Storage:

RP: 2x128GB SATA SSD Hard Disk &

8GB eUSB

LC: SSD 128GB

Central Switch Fabric: SM15 – No LC Fabric

Arbiter – Lightning

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ASR 9901 Port mapping

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ASR9901 Port Configuration – Internal View

Tomahawk NPU 0 Tomahawk NPU 1

IFE 0 & IFE 1 IFE 0 & IFE 1

Group 0 Group 1 Group 2 Group 3 Group 4 Group 5

8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 33

Config Rules Per NP

Only for 24x 1/10G Ports (Marked on FP) Same Port-speed for all ports in a port group
Similar to A9K-24X10G-1G Line Card Port Grouping 1st Group (0 or 3) : If set to 1G -> All Remaining Ports in NP 1G
Ports Divided: 6 Fixed-Groups: 0–5 1st Group (0 or 3) : If set to 10G -> We get Flexibility in that NP
Remaining Groups (1,2,4,5) -> Can be either 1G or 10G
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ASR9901 Port Configuration – NP Valid Configs
NPU 0
Group 0 Group 1 Group 2
P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19
1G 1G 1G 1G 1G 1G 1G 1G 1G 1G 1G 1G
10G 10G 10G 10G 1G 1G 1G 1G 1G 1G 1G 1G
10G 10G 10G 10G 1G 1G 1G 1G 10G 10G 10G 10G
10G 10G 10G 10G 10G 10G 10G 10G 1G 1G 1G 1G
10G 10G 10G 10G 10G 10G 10G 10G 10G 10G 10G 10G

NPU 1
Group 3 Group 4 Group 5
P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33
1G 1G 1G 1G 1G 1G 1G 1G 1G 1G 1G 1G
10G 10G 10G 10G 1G 1G 1G 1G 1G 1G 1G 1G
10G 10G 10G 10G 1G 1G 1G 1G 10G 10G 10G 10G
10G 10G 10G 10G 10G 10G 10G 10G 1G 1G 1G 1G
10G 10G 10G 10G 10G 10G 10G 10G 10G 10G 10G 10G

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Port Speed Configuration Example

hw-module location <rack>/<slot>/CPU0 port-mode RxS,RxS[,RxS…]

 R = Run-length (number of consecutive ports with same

speed)
 S = Speed (1 or 10, in Gbps)

EXAMPLE:
hw-module location 0/4/CPU0 port-mode 8x10,16x1

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 Runs distributed control plane
Line Card Components protocols for increased scale
BFD, CFM, ARP
Main forwarding engine L2 and L3 lookups Receive FIB table from RP and
program hardware forwarding
Multicast replication toward Optics table
User level QoS and Security features CPU

NPU P1
PHY P1
FIA
P2
P3 Switch
TM
P2
P3
BE Fabric
BE ASIC

Dedicated queue ASIC – TM (traffic Provides data connection to switch fabric

manager) per NPU for QoS functions
User Configurable Queue on TM.
Default Port Queue Always Created.
#CLUS
Manage VoQ, Superframe and loadbalancing
data traffic across switch fabric
Mcast replication table for replication toward
NPs
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Network Processor Architecture Details
TR and SE has different
TR and SE has same
memory size
memory size NPU Complex

STATS MEMORY
FIB MAC
LOOKUP Forwarding chip (multi core) FRAME MEMORY
MEMORY TCAM
-

• TCAM: VLAN tag, QoS and ACL classification

• Stats memory: interface statistics, forwarding statistics etc

• Frame memory: buffer, Queues

• Lookup Memory: forwarding tables, FIB, MAC, ADJ

• TR/SE
• Different TCAM/frame/stats memory size for different per-LC QoS, ACL, logical interface scale
• Same lookup memory for same system wide scale mixing different variation of LCs doesn’t impact
system wide scale
-TR: transport optimized, -SE: Service edge optimized
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Pop Quiz ????

For the 24 dual 10G/1G ports on ASR9901, if the first port-group on a

NP is configured as 10G, what is the possible port speeds for the
other two port-groups of the same NP?
• 10G
• 10G or 1G
• 1G

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ASR9000 Distributed
Control Plane
ASR9000 Fully Distributed Control Plane
CPU
LPTS (local packet transport service):
control plane policing
RP
CPU Punt
FPGA FIA

Switch Fabric Switch Fabric

LC
Control
Punt Switch CPU
CPAK

packet CPAK
PHY
NP
LPTS FIA
CPAK RP CPU: Routing, MPLS, IGMP, PIM,
CPAK
PHY
NP FIA HSRP/VRRP, etc
Switch
Fabric
CPAK

CPAK
PHY
NP FIA LC CPU: ARP, ICMP, BFD, NetFlow,
CPAK
OAM/CFM, L2 Protocols etc
CPAK
PHY
NP FIA
NP Offloading: BFD
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L3 Control Plane Architecture

Static BGP OSPF

LDP RSVP-TE
ISIS EIGRP

LSD RIB RSP/RP CPU

RSP/RP

LC

ARP/NDP
SW FIB HW FIB Adjacency
LC NP
AIB
AIB: Adjacency Information Base
LC CPU RIB: Routing Information Base
FIB: Forwarding Information Base
LSD: Label Switch Database
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 MAC Learning and Sync
Hardware based MAC learning:
1 NP learn MAC address in hardware (around ~4Mpps/NP
4M pps)
RP
2 NP flood MAC notification (data plane) Punt
CPU
message to all other NPs in the system to FPGA FIA
sync up the MAC address system-wide.
MAC notification and MAC sync are all done
in hardware
Switch Fabric Switch Fabric

CPU LC1
LC2
CPU
Data 3x10GE
SFP + 1NP 2
packet 3x10GE
SFP + NP
FIA 3x10GE
SFP +
NP
FIA
3x10GE
3x10GE
NP SFP +
NP
2

Fabric ASIC
Switch
SFP +
FIA 3x10GE
3x10GE NP

Fabric ASIC
Switch
NP SFP +
SFP + FIA
3x10GE
3x10GE NP
NP SFP +
SFP +
FIA 3x10GE
3x10GE NP
NP SFP +
SFP + FIA
3x10GE
3x10GE NP
NP SFP +
SFP +
FIA 3x10GE
3x10GE NP
NP SFP +
SFP + FIA
3x10GE
NP
SFP +

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Distributed BFD Architecture

RP
OSPF ISIS BGP

BFD Events
BFD session info

BFD Session Tables on RP

BFD Session info BFD Events BFD Session info

LC1-CPU LCn-CPU
BFD Session Tables on LC …… BFD Session Tables on LC

BFD Hellos BFD Hellos

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HW-offloaded BFD hw-module bfd-hw-offload enable location 0/0/CPU0

RP
OSPF ISIS BGP

BFD Events
BFD session info

BFD Session Tables on RP

BFD Session info BFD Events BFD Session info

LC1-CPU LCn-CPU
……
BFD BFD BFD BFD BFD BFD BFD BFD
On On On On On On On On
NP NP NP NP NP NP NP NP

BFD Hellos BFD Hellos

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Pop Quiz ????

In an ASR9906 system which has 2 RSP, 4 linecards and 5 switch

fabric cards, how many total CPUs are available to host ASR9000
control-plane functionalities?
• 2
• 4
• 6
• 11

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Data Packet Processing
& QoS
 Distributed Two-Stage Packet Processing
• Ingress lookup yields packet egress port and applies ingress features

• Egress lookup performs packet-rewrite and applies egress features

CPU CPU
CPAK 0
1 CPAK 0
PHY NP FIA FIA NP PHY
CPAK 1
CPAK 1

CPAK 2
Switch CPAK 2
Fabric
PHY NP FIA FIA 2
NP PHY
CPAK 3 CPAK 3
Switch Switch

…
…
Fabric Fabric
CPAK 4 CPAK 4
FIA
(SM15) (SM15)
PHY NP FIA NP PHY
CPAK 5
CPAK 5 Up to
Up to
14x120G 14x120
CPAK 6 1 Switch G CPAK 6
PHY NP
2 FIA Fabric FIA NP PHY
CPAK 7 CPAK 7

Uniform packet flow for simplicity and predictable

performance
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ASR9000 Life of a Packet – Tomahawk LC
2 4 6 • Egress L2/L3 FIB lookup, 8
• Ingress L2/L3 FIB lookup, • Buffering packet from NP • MACSEC Emcryption
ACL/QoS lookup • Requesting fabric credit ACL/QoS lookup
• Egress PBR/ABR, ACL, uRPF • G.709/OTN/WAN-
• Ingress PBR/ABR, ACL, uRPF • Manage superframe and PHY/LAN-PHY
• Ingress QoS: classification, load-balancing packet • Egress QoS: classification,
marking, policing, shaping • Line Clocking
marking, policing across fabric
• Packet Punting • Manage system VoQ • Incomplete Adj Packet
• Ingress ECMP/LAG hashing Punting
• Egress ECMP/LAG hashing

Ingress side of LC CPU CPU 6 8

NP PHY
5 7 TM

CPAK 0
1
2
4
FIA
CPAK 1
PHY NP
3 TM
FIA Switch
Fabric
Egress side of LC
1 3 5
7
• MACSEC Decryption • Ingress Queuing • Re-assembling packets • Egress Queuing
• G.709/OTN/WAN- Processing from superframe Processing
PHY/LAN-PHY • Bypassed in case no • Send packet to
• Line Clocking ingress queuing support corresponding NP
• Release buffer and
fabric credit

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Switch Fabric Arbitration
5: credit return
Fabric
1: Fabric Request ASIC

Fabric
ASIC

Arbitration
FIA* FIA*
and VOQ SFC or RSP0 2: Arbitration and VOQ

Fabric
ASIC
3: Fabric Grant
Fabric
ASIC

4: load-balanced Arbitration

transmission across SFC or RSP1 *FIA: FABRIC

fabric links INTERCONNECT
ASIC
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Fabric Load Balancing – Unicast
Fabric
ASIC

Fabric
ASIC
Arbitration FIA
FIA
and VOQ SFC or RSP0 and VOQ 4 3 2 1

Fabric
ASIC
Fabric
ASIC
Arbitration
SFC or RSP1

• Unicast traffic sent across first available fabric link to destination (maximizes efficiency)
• Each frame (or super frame) contains sequencing information
• All destination fabric ASIC have re-sequencing logic
• Additional re-sequencing latency is measured in nanoseconds

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Fabric Load Balancing – Multicast
Fabric
ASIC

Fabric
ASIC
Arbitration FIA
FIA
C1 B2 A3 B1 A2 A1
and VOQ SFC or RSP0 and VOQ

Fabric Flows exit in-order

ASIC
Fabric
ASIC
Arbitration
SFC or RSP1

• Multicast traffic hashed based on (S,G) info to maintain flow integrity

• Very large set of multicast destinations preclude re-sequencing
• Multicast traffic is non arbitrated – sent across a different fabric plane

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 ASR9000 Priority-Based QoS Architecture
• Dedicated Traffic Manager(TM) for Traffic Queuing
• User Configurable QoS Policy on Ingress/Egress NP
• End-to-End priority propagation  Guarantee bandwidth, low latency for high priority traffic
• Unicast VOQ and back pressure
Ingress side of LC Egress side of LC

CPU CPU 4
P1
P2
NP0 PHY
P3 3 P1
P1 BE
2
P2
NP1 PHY
FIA
P2 P3
CPAK 0 TM P3 BE

FIA
BE

CPAK 1
PHY NP Switch NP2 PHY
1 Fabric P1
NP3
TM
P2
P3 PHY
BE

1 2
• Ingress (sub-)interface
QoS Queues
• User Configurable
Ingress QoS Policy
User-configuration
with Ingress MQC
3 4
• 4xVOQ per VQI 4x Egress Destination Qs per VQI,
Egress (sub-)interface
• Up to 8K VOQs per TSK FIA aggregated at egress port rate
(vs 4k per SKT FIA) QoS Queues
User-configuration
with Egress MQC
Implicit Configuration
Not User-controllable
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 L2 IF: trust outer Cos
Default Implicit Trust Model L3 IF: trust DSCP
L3 MPLS: trust outer EXP

IPP=5 DSCP=44
802.1p = 1 L2 Bridging internal
IPP=5 DSCP=44 cos = 1 802.1p = 1 *
IPP=5 DSCP=44

ASR 9000 would never modify

Carried in internal buffer header,
by default, internal cos is used for impositioned fields only, packet DSCP/IP without
For example, added vlan tag, impositioned MPLS label, a policy-map configured
It doesn’t include VLAN tag translation or MPLS label swap

IPP=5 DSCP=44

Untagged L2 Bridging
internal 802.1p = 0 *
IPP=5 DSCP=44 IPP=5 DSCP=44
cos = 0

Ingress line card Egress line card

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 Internal QoS: Back Pressure and VoQ
Ingress LC Packet
CPU process in NP
FIA
P1
P2
NP P3
BE
Switch
Fabric Egress LC
PHY NP P1
P1
P2
P3
P2
P3
BE
Back pressure triggered CPU
BE 3 by NP congestion
P1 P1
PHY
P2 P2
P3
• Per egress NP input q backpressure to egress FIA DQ
P3
BE BE PHY
P1 P1

• Per egress FIA priority DQ backpressure to switch fabric,

P2
P3
P2
P3
PHY
BE BE
then to the same priority VoQs on all ingress FIAs
4
• No Head of Line Blocking between different ports or • 100G singe flow!
- Per Tomahawk FIA VoQ (3) or DQ (4) 100G, 40G or 10G single flow
between different priority VoQs for the same SFP/VQI
line-rate
• Per Tomahawk FIA: 2k x4 VoQs, 96 x4 DQs

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3-Layer Hierarchical QoS (H-QoS)
L3 policy-map child
L0 L1 L2 L4 class Pr1
Parent Policy on L2
Port Group Port Grand-Parent (EFP) or L3 subint. Child policy (child of
scheduler scheduler Policy class-default or Parent) with user- police rate 64 kbps
not not physical port /w
user-defined defined classes & priority level 1
configurable configurable classes class-default class Pr2
police rate 10 mbps
priority level 2
class Cl3
bandwidth 3 mbps
class Cl4
bandwidth 1 mbps
!
policy-map parent
class parent1
shape average 100 mbps
service-policy child
class parent2
shape average 25 mbps
service-policy child
•N/A •N/A •Shape •Priority Level 1 •Priority Level 1 class class-default
•Priority Level 2 •Priority Level 2 !
•Bandwidth •Shape, •Shape,
remaining •bandwidth or •bandwidth or policy-map grand-parent
bandwidth remaining bandwidth remaining class class-default
•1R2C policer •(W)RED •(W)RED
•Police •Police shape average 500 mbps
•Set (marking) •Set (marking) service-policy parent

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 44
H-QoS – Supported Classification/Policy
Policy-map hierarchy level Classification support Policy Support

• Shape Average
• Bandwidth remaining
Grand-parent Only class-default • 1R2C policer with only drop/transimit
action(no set/mark, Tomahawk card
only)
• Priority/WRED Queue and Queue-limit on
User defined fields with
Leaf only
Parent restrictions based on
• Policer/Shaper/Marking/non-Priority
format/interface types.
Queue/Bandwidth/Bandwidth Remaining
• Priority/WRED Queue and Queue-limit on
User defined fields with
Leaf only
Child restrictions based on
• Policer/Shaper/Marking/non-Priority
format/interface types.
Queue/Bandwidth/Bandwidth Remaining

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 45
ASR9000 QoS Configuration Model
class-map match-any GREEN
match cos 0 2 3
class-map match-any RED
match cos 4
Classifier class-map match-any BLUE
match cos 5

023

57
match cos 7

4
policy-map ACTION
Policy class GREEN
bandwidth 10 gbps
class RED
priority level 2
Normal Priority

police rate percent 10

Priority 2

Priority 1
class BLUE
priority level 1
police rate percent 5

Interface GigabitEthernet0/0/0/0.1
service-policy output ACTION
GigabitEthernet0/0/0/0.1

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 46
ASR9000 QoS Classification Criteria
L2 Header Fields L3 Header Fields Internal Marking
L2 Inner/outer COS, Outer EXP Discard-class
Interfaces/EFPs inner/outer vlan, DSCP/TOS Qos-group
DEI TTL, TCP flags,
Source/Destination MAC Source/destination L4
Or address* ports
L3 Interfaces match all/match any Protocol
Source/Destination IPv4
address*

Notes: - Support match all or match any

- Max 8 match statements per class, max 8 match entries per match statement
- Not all header fields can be used in one MQC policy-map, see details next
- No ”Deny” statement if access-list used.

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 47
 Traffic Marking Sample configuration for the marking
class CLASS-UNTAGGED-PD
• “settable” packet fields: set cos 2
– dscp/precedence set dscp 21

– EXP imposition police rate 10240000 bps burst 320000 bytes peak-rate 20480000
– EXP topmost bps peak-burst
conform-action set cos 2
– cos inner/outer conform-action set prec 2
– qos-group exceed-action set cos 1
exceed-action set dscp 8
– discard-class violate-action set cos 0
– DEI violate-action dscp 0

• ASR9K supports maximum of 2 fields per class-map. The same 2 fields

can be placed in any combination below
– 2 sets per police-conform/exceed/violate
– 2 sets without policing

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 48
 Marking in Hierarchical Policy-Map

Policy-map parent policy-map child Cos=2

Class class-default Class c1 Dscp=af12
Qos-group=2
Parent Set cos 1 Set cos 4

Set cos 1 Set dscp AF11 Set qos-group 1

Set dscp af11 Set dscp af12
Police rate 10 Mbps peak-rate 20 Mbps Police rate 5 Mbps peak-rate 10 Mbps Set cos 2

conform-action set dscp af12 conform-action set qos-group 2

Parent
conform-action set cos 2 conform-action set cos 5

Child exceed-action set dscp af13 exceed-action set qos-group 3 Set qos-group 2
Set cos 5
Set cos 4 exceed-action set cos 3 exceed-action set cos 6
Set qos-group 1
violate-action drop violate-action drop Child

service-policy child class class-default

Non-policer set first from Top to Bottom

Then policer set from Bottom to Top
#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 49
ASR9000 Policing
• RFC 2698 supported (2r3c) and 1r2c ‒transmit
• Ingress & egress policing supported ‒drop
‒set (implicitly behaves like set
• General Rule: Policing required on and transmit)
priority queues.
‒each color can have two set
Priority level 2 classes can also actions:
accept shaping instead of
policing.
• Granularity of 8Kbps supported. Policy-map parent
Class class-default
• 2-level nested policy maps Police rate 10 Mbps peak-rate 20 mbps
conform-action set dscp af12
supported conform-action set cos 2
Note: policers at parent and child exceed-action set dscp af13
work independently exceed-action set cos 3

• Policer actions supported:

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 50
Pop Quiz ????
With the configuration below, what is the policer rate programed in
hardware?

1. 2000 kbps Policy-map test

2. 88805 kbps class class-default
3. 88800 kbps police rate 88805 kbps
Interface HundredGigE 0/0/0/0.2000
encapsulation dot1q 2000
service-policy input test

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 51
The Result
RP/0/RP0/CPU0:9912-64Bit#show qos interface hundredGigE 0/0/0/0.2000 input
Interface: HundredGigE0_0_0_0.2000 input
Bandwidth configured: 100000000 kbps Bandwidth programed: 100000000 kbps
ANCP user configured: 0 kbps ANCP programed in HW: 0 kbps
Port Shaper programed in HW: 0 kbps
Policy: test Total number of classes: 1
----------------------------------------------------------------------
Level: 0 Policy: test Class: class-default
QueueID: 524611 (Port Priority 3)
Policer Profile: 63 (Single)
Conform: 88800 kbps (88805 kbps) Burst: 1110062 bytes (0 Default)
Child Policer Conform: TX
Child Policer Exceed: DROP
Child Policer Violate: DROP
----------------------------------------------------------------------

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 52
Shaping, Policing Overhead Accounting
• L2 frame length is being used by default without preamble and IFG.
• Same for ingress/egress
• Same for all QOS actions

• QoS policy can be configured to take into account arbitrary L1 framing and L2 overhead

Length/
Inter Frame Gap Preamble SFD DA SA VLAN Type Payload FCS
12 7 1 6 6 4 2 46-1500 4

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 53
Queueing
Queueing Action Ingress Egress Comments
1 shape Yes Yes Supported on all interfaces.
Rate configuration supported in percent and absolute
terms. Burst configuration not supported.
2 bandwidth Yes Yes Supported on all interfaces.
Rate configuration supported in percent and absolute
terms.
3 bandwidth-remaining Yes Yes Supported on all interfaces.
Configuration supported in percent and ratio, although
only one type can be used in a policy.
4 priority Yes Yes Two priority levels supported on all interfaces. Priority
class should be always constrained by a policer.

5 queue-limit Yes Yes Supported on all interfaces. Can be specified in

packets, bytes and time-based units.
6 WRED Yes Yes WRED based on prec/DSCP/EXP are supported on L3
interfaces. WRED based on discard-class is supported
on L2 and L3 interfaces.

 Not all LCs support ingress queueing

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 54
Default Interface Queues
P1 P2 P3 L

Level 4 Queues

Level 3 Schedulers

Level 2 Schedulers

Level 1 Schedulers

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 55
 MQC Hierarchy in Queuing ASIC
Port default queues MQC queues
policy-map child
P1 P2 P3 L c1 c2 cd-c class c1
priority level 1
police rate 640 kbps
class c2
bandwidth 20 mbps
class class-default cd-c
bandwidth 1 mbps
!
L4
policy-map parent
class class-default cd-p
shape average 35 mbps
service-policy child
L3 cd-p !
interface GigabitEthernet0/0/0/0
service-policy output parent

L2
Inactive entity
Active entity
L1

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 56
 MQC Hierarchy in Queuing ASIC
policy-map child
Port default queues G0/0/0/0.1 G0/0/0/0.2 class c1
P1 P2 P3 L c1 c2 cd-c c1 c2 cd-c priority level 1
police rate 640 kbps
class c2
bandwidth 20 mbps
class class-default cd-c
bandwidth 1 mbps
!
policy-map parent
L4 class class-default cd-p
shape average 35 mbps
service-policy child
!
L3 cd-p cd-p interface GigabitEthernet0/0/0/0.1
service-policy output parent
!
interface GigabitEthernet0/0/0/0.2
service-policy output parent
L2
Inactive entity
L1 Active entity
#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 57
Pop Quiz ????

For an incoming untagged layer 2 frame, what is the priority value

used when the frame is processed inside ASR9000?
• 2
• COS bit
• 802.1p Value
• 0

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 58
IOS-XR & IOS-XR 64 Bit
 Cisco IOS – A Recap
Cisco IOS Cisco IOS-XE Classic IOS-XR IOS-XR 64 Bit
Control Data Mgmt
Plane Plane Plane
XR Code v1 XR Code v2

Hosted App 1

Hosted App 2
IOSd

NetFlow
SNMP
OSPF

LPTS

NetFlow
NetFlow
XML
QoS
BGP

ACL
PIM

SNMP
SNMP

OSPF
OSPF

LPTS
LPTS

XML
XML

QoS
BGP
QoS

ACL
BGP

ACL

PIM
PIM
System
IOS “Blob” Admin

Operational Infra Distributed Infra Distributed Infra Distributed Infra

Kernel Kernel Kernel Kernel Kernel

Linux-BinOS QNX, 32bit Linux, 64bit Linux, 64bit Linux, 64bit

Virtualization Layer

1990s 2000s 2003-04 Present Day

Incremental Development, with Industry leading investment protection

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 60
IOS XR Evolution: XR 64 bit Architecture
IOS-XR IOS-XR Separate Admin Plane
Routing Admin Plane
Apps Routing
Control Plane
RP

RP
System 64-bit IOS XR.
Admin Linux Linux
QNX Linux
IOS XR IOS-XR
Admin Plane
Line Card

Line Card
Linux VM

LC-CPU LC-CPUs

Linux Linux
QNX 64 bit Linux Kernel
Linux

Classic IOS XR Linux-based Virtualized

IOS XR 64 Bit
#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 61
IOS XR 64 Bit Packaging
Bootable Images

Core packages: OS, Admin, Forwarding, Modular Services

Minimum Image asr9k-mini-x64-6.1.2.iso Card, Basic Routing, SNMP, Alarm Correlation

Customized ISO image includes mini ISO + required packages + SMUs + XR

Golden ISO
config

Optional Feature Packages

asr9k-eigrp-x64-1.0.0.0-r612.x86_64.rpm
asr9k-mpls-x64-2.1.0.0-r612.x86_64.rpm
asr9k-isis-x64-1.1.0.0-r612.x86_64.rpm
asr9k-mcast-x64-2.0.0.0-r612.x86_64.rpm
asr9k-ospf-x64-1.1.0.0-r612.x86_64.rpm
asr9k-optic-x64-1.0.0.0-r612.x86_64.rpm
asr9k-m2m-x64-2.0.0.0-r612.x86_64.rpm
asr9k-li-x64-1.1.0.0-r612.x86_64.rpm
asr9k-mgbl-x64-3.0.0.0-r612.x86_64.rpm
asr9k-k9sec-x64-3.1.0.0-r612.x86_64.rpm
asr9k-mpls-te-rsvp-x64-1.2.0.0-r612.x86_64.rpm

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 62
IOS XR 64 Bit Packaging - GISO – Golden ISO
• GISO is a customized iso which is built as per individual customer needs.
• GISO contains Mini ISO + rpms + SMUs + config

How to build GISO: use tool provided on the router at /pkg/bin/gisobuild.py in XR

domain.
Usage: gisobuild.py [-h] -i BUNDLE_ISO [-r RPMREPO] [-c XRCONFIG] [-l GISOLABEL]
[–m] [-v]
Example: gisobuild.py -i asr9k-mini-x.iso -r . -c config-file -l v1

Script Parameter Expansion Explanation Required/optional

-I BUNDLE_ISO Path to mini ISO Required
-r RPMREPO Path to RPM repo Optional
-c XRCONFIG Optional
-l GISOLABEL GISO Label Optional
-m migration To build migration tar for ASR9K only. Optional
-v version Print script version and exit Optional
-h help Print help menu N/A

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 63
Migrating Classic XR to IOS XR 64 Bit
eXR Migration

eXR

FPD eXR 6.2.x

eXR 6.3.x
Upgrade
cXR 6.2.x
cXR or later

Pre-6.1.3 Target 64 Bit XR

5.x.y/4.x.y Classic XR
Corresponding
To Target 64 Bit XR Two Ways to Migrate:
1. CSM Orchestrated Migration
2. MOP: Manual Migration
Follow below link for details:
https://www.cisco.com/c/en/us/td/docs/routers/asr9000/migration/guide/b-migration-to-
ios-xr-64-bit/b-migration-to-ios-xr-64-bit_chapter_011.html

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 64
Migration Pre-requisites
HW Component Backup cfg to
Upgrade cXR Operational Status External Server
Check
(Calvados, XR)

• All hardware • Any pre-6.1.3 • All hardware • Back up admin/XR

components, release needs to components must configuration to
Chassis, RSP/RP, be upgraded to be in operational external server
LC, FC, FAN and classic XR state before
PEM, should be corresponding to migration
supported in target IOS XR 64
ASR9K 64 bit. Any Bit version
unsupported
hardware may fail
to boot after
migration

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 65
ASR 9000 System Migration Example to
Lightspeed
Classic XR 5.3.4 Classic XR 64 Bit XR 6.5.1 64 Bit XR
6.5.1 6.5.1
RP2/RSP4 RP2/RSP4 RP2/RSP4 RP3/RSP5
RP2/RSP4 RP2/RSP4 RP2/RSP4 RP3/RSP5
SFC2 SFC2 SFC2 SFC3
SFC2 SFC2 SFC2 SFC3
SFC2 SFC2 SFC2 SFC3
SFC2 SFC2 SFC2 SFC3
SFC2 SFC2 SFC2 SFC3
Tomahawk Tomahawk Tomahawk Lightspeed

Upgrade FPD
with cXR 6.5.1
FPD
#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 66
Conclusion
• ASR9000 - Truly Carrier-Class Edge Router Provides:
• Rich Features, Flexible Service Capability
• Variety of Hardware to Meet Different Capacity Requirements

• Fully Distributed Architecture for High Performance and System

Scalability
• Uniform, Open and Modularized Software Architecture

#CLUS BRKARC-2003 © 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 67
Complete your online session evaluation

Give us your feedback to be entered

into a Daily Survey Drawing.
Complete your session surveys through
the Cisco Live mobile app or on
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Don’t forget: Cisco Live sessions will be available for viewing
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Continue
your Demos in
the Cisco
Walk-in
self-paced
Meet the
engineer
Related
sessions
education campus labs 1:1
meetings

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Thank you

#CLUS
#CLUS
 R&S related Cisco education offerings
Course
CCIE R&S Advanced Workshops (CIERS-1 &
CIERS-2) plus
Self Assessments, Workbooks & Labs
• Implementing Cisco IP Routing v2.0
• Implementing Cisco IP Switched
Networks V2.0
• Troubleshooting and Maintaining
Cisco IP Networks v2.0
Interconnecting Cisco Networking Devices:
Part 2 (or combined)
Interconnecting Cisco Networking Devices:
Part 1
For more details, please visit: http://learningnetwork.cisco.com
Questions? Visit the Learning@Cisco Booth
Description Cisco Certification
Expert level trainings including: instructor led workshops, self CCIE® Routing & Switching
assessments, practice labs and CCIE Lab Builder to prepare candidates
for the CCIE R&S practical exam.
Professional level instructor led trainings to prepare candidates for the CCNP® Routing & Switching
CCNP R&S exams (ROUTE, SWITCH and TSHOOT). Also available in
self study eLearning formats with Cisco Learning Labs.
Builds on ICND1 to provide capabilities needed to configure, implement CCNA® Routing & Switching
and troubleshoot a small enterprise network. Including: understanding of
Quality of Service (QoS), how virtualized and cloud services interact and
impact enterprise networks, along with an overview of network
programmability and the related controller types and tools that are
available to support software-defined network architectures.
Also available in self study eLearning format with Cisco Learning Lab.
Understand layer 2 and layer 3 networking fundamentals needed to CCENT® Routing & Switching
install, configure, and provide basic support of small/branch networks.
Covers network device security and IPv6 basics. Also available in self
study eLearning format with Cisco Learning Lab.
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 Network Programmability Cisco education offerings
Course
Developing with Cisco Network
Programmability (NPDEV)
Designing and Implementing Cisco Network
Programmability (NPDESI)
Programming for Network Engineers (PRNE)
Cisco Digital Network Architecture
Implementation Essentials (DNAIE)
For more details, please visit: http://learningnetwork.cisco.com
Questions? Visit the Learning@Cisco Booth
Description Cisco Certification
Provides Application Developers with comprehensive curriculum to Cisco Network Programmability
develop infrastructure programming skills; Developer (NPDEV) Specialist
Addresses needs of software engineers who automate network Certification
infrastructure and/or utilize APIs and toolkits to interface with SDN
controllers and individual devices
Provides network engineers with comprehensive soup-to-nuts Cisco Network Programmability
curriculum to develop and validate automation and programming skills; Design and Implementation
Directly addresses the evolving role of network engineers towards more (NPDESI) Specialist Certification
programmability, automation and orchestration
Learn the fundamentals of Python programming – within the context of Recommended pre-requisite for
performing functions relevant to network engineers. Use Network NPDESI and NPDEV Specialist
Programming to simplify or automate tasks Certifications
This training provides students with the guiding principles and core
elements of Cisco’s Digital Network Architecture (DNA) architecture and
its solution components including; APIC-EM, NFV, Analytics, Security
and Fabric.
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 Service Provider Cisco education offerings
Course
Deploying Cisco Service Provider Network Routing
(SPROUTE) & Advanced (SPADVROUTE)
Implementing Cisco Service Provider Next-
Generation Core Network Services (SPCORE)
Edge Network Services (SPEDGE)
Building Cisco Service Provider Next-Generation
Networks, Part 1&2 (SPNGN1), (SPNGN2)
Implementing Cisco Service Provider Mobility UMTS
Networks (SPUMTS);
Implementing Cisco Service Provider Mobility CDMA
Networks (SPCDMA);
Implementing Cisco Service Provider Mobility LTE
Networks (SPLTE)
Implementing and Maintaining Cisco Technologies
Using IOS XR (IMTXR)
For more details, please visit: http://learningnetwork.cisco.com
Questions? Visit the Learning@Cisco Booth
Description Cisco Certification
SPROUTE covers the implementation of routing protocols (OSPF, IS-IS, BGP), CCNP Service Provider ®
route manipulations, and HA routing features; SPADVROUTE covers advanced
routing topics in BGP, multicast services including PIM-SM, and IPv6;
SPCORE covers network services, including MPLS-LDP, MPLS traffic
engineering, QoS mechanisms, and transport technologies;
SPEDGE covers network services, including MPLS Layer 3 VPNs, Layer 2 VPNs,
and Carrier Ethernet services; all within SP IP NGN environments.
The two courses introduce networking technologies and solutions, including OSI CCNA Service Provider ®
and TCP/IP models, IPv4/v6, switching, routing, transport types, security, network
management, and Cisco OS (IOS and IOS XR).
The three courses (SPUMTS, SPCDMA, SPLTE) cover knowledge and skills Cisco Service Provider Mobility
required to understand products, technologies, and architectures that are found CDMA to LTE Specialist;
in Universal Mobile Telecommunications Systems (UMTS) and Code Division Cisco Service Provider Mobility
Multiple Access (CDMA) packet core networks, plus their migration to Long- UMTS to LTE Specialist
Term Evolution (LTE) Evolved Packet Systems (EPS), including Evolved Packet
Core (EPC) and Radio Access Networks (RANs).
Service Provider/Enterprise engineers to implement, verification-test, and Cisco IOS XR Specialist
optimize core/edge technologies in a Cisco IOS XR environment.
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 Data and Analytics Cisco education offerings
Course Description
ANDMB – Data Management, Architecture and Applications Provides hands on training with a technical mix of application, compute, storage and
networking topics concerning the deployment of Big Data clusters.

ANDMA – Advanced Data Management, Architecture and
Applications
Covers major architecture design to cater to different needs of the application, data center
or deployment requirements. It provides architectural designs and advanced hands-on
training on topics covering Scaling of cluster to thousands of nodes and management, Data
Life Cycle management with HDFS tiered storage, and different approaches for Multi-tenant
Hadoop cluster deployments with Openstack

Data and Analytics training page: http://www.cisco.com/c/en/us/training-events/resources/learning-services/technology/data-analytics.html

For more details, please visit: http://learningnetwork.cisco.com
Questions? Visit the Learning@Cisco Booth

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