ASR 1000

Overview

Presentation_ID © 2006 Cisco Systems, Inc. All rights reserved. Cisco Confidential 1
 ASR 1000 Overview

Next-generation of Midrange router family
2RU/4RU/6RU chassis
5 / 10 / 20 / 40 Gbps forwarding
Supporting same feature set at different price
performance points

ASR 1000 Differentiators
Highly available carrier-class design
Integrated services (SBC, FPM, Security..)
State of the art QoS
Unmatched midrange scalability & performance
Feature velocity

Feature richness provides deployment
flexibility
Support for Service Provider & Enterprise
features
BNG (BRAS, LAC, LNS)
IPSec Termination
Distributed PE / MSE
High-speed CPE
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 2
…
Cisco ASR 1000 Series Introduction
SPA Interface Processor SPA Slots
Can take Up to 4 HH SPAs Re-Uses existing SPAs

Embedded Services Processor Route Processor

40 Cores with Traffic Manager 1.5 GHz, Up to 4GB DRAM
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 3
 ASR 1000 Product Family

ASR 1002 ASR 1004 ASR 1006

2RU 4RU 6RU
SPA Slots 3-Slot 8-Slot 12-Slot
Aggregated Services and Scale
Number of ESP Slots 1 1 2
Integrated
Number of RP Slots 1 2
(RP1)
Integrated
Number of SIP Slots 2 3
(SIP10)
Cisco® IOS®
Software Software Hardware
Redundancy
Built-in GigE 4 N/A N/A
Height 3.5” (2RU) 7” (4RU) 10.5” (6RU)
Bandwidth 5–10 Gbps 10–40+ Gbps 10–40+ Gbps
Performance 4–8 Mpps 8–16+ Mpps 8–16+ Mpps
Air Flow Front to Back Front to Back Front to Back
Power Supply (Watts) 470 765 1275
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 4
 ASR 1000 – Product Positioning

>300G

7600,
20G GSR,CRS
18G

ASR 1000 10K

10G with
PRE-3
ESP20
ASR 1000
ASR 1000 with
2RU w/ ESP10
ESP5

5G

7304-NSE

< 3G 7200
3845

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential List Price Price includes Chassis, engine 5
 ASR 1000 Hardware
& System
Architecture

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 6
 ASR 1000 Building Blocks

ESP RP RP ESP
(active) (active) (standby) (standby)

RP (Route Processor)
FECP
Handles control plane traffic
FECP RP RP
Manages system

Interconn. Interconn.

ESP
QFP QFP
Crypto
subsys- Crypto
subsys- Handles forwarding plane
assist tem assist tem
traffic

Interconn. Interconn.

SPA Interface Processor
Houses the SPAs

Midplane
SPAs
Provide interface
connectivity
Interconn. Interconn. Interconn.

Centralized Forwarding
SPA IOCP SPA IOCP SPA IOCP Architecture
Agg. Agg. Agg. All traffic flows through the
ESP
SPA … SPA SPA … SPA SPA … SPA

ESI, (Enhanced Serdes Interface) 11.5Gbps

SPA-SPI, 11.2Gbps
Hypertransport, 10Gbps
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 7
 Route Processor – RP1

General Purpose CPU based on 1.5GHz Freescale 8548

Memory:
1. DRAM: Default: 2 GB; Max: 4 GB
2. NVRAM: 1G of Internal Flash for code storage, boot,
config, logs, etc.

Management Interfaces:
– Management ethernet management port, auxiliary port,
console port

Storage:
– For core dumps, failure capture, etc; 40 GB Hard Disk
Drive (rotary) initially; Solid-state drive (SSD) option at
FCS (TBD)
– External USB flash for IOS configs or File copying

Communications paths to other cards (for control and for
network control packets)

Stratum-3 network clock circuitry and BITS reference input
(for synchronizing SONET links, etc.)

Miscellaneous control functions for card presence detection,
card ID, power/reset control, alarms, redundancy, etc.

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 8
 2RU

Integrated RP1. Exact same hardware features as RP1 with the

following exception
– DRAM – 4G default
– No Hard Drive for Mass storage
– eUSB of 8GB
• 7GB used for mass storage
• 1 GB used as NVRAM for code storage, boot, config, logs,
etc

Modular ESP; supports ESP5, ESP10, ESP10-N

Built-in 4XGE ports – feature/performance parity to GE SPA

Software redundancy feature supported with IOS processes

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 9
 Embedded Services Processors
ESP5 , ESP10, ESP10-N, ESP20

Centralized, programmable forwarding
engine (i.e. QFP subsystem (PPE) and
crypto engine) providing full-packet
processing
ESP10-N does not support crypto engine

Packet buffering and queuing/scheduling
(BQS)
For output traffic to SPA Interface
Processors/SPA’s
For special features such as input
shaping, reassembly, replication, punt to
RP, etc.

Interconnect providing data path links
(ESI) to/from other cards over midplane
Transports traffic into and out of QFP10
Input scheduler for allocating QFP10 BW
among ESI’s

FECP CPU managing QFP, crypto device,
midplane links, etc
ESP10-N does not support crypto device

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 10
Quantum Flow Processor Architecture, 1st generation

Quantum

+ + Flow
Processor
Software
Multi-Core (40) Packet Processor Traffic Manager (BQS)

1. Scale  100s of resources & massive feature scale

2. Performance  Designed to deliver 5-100s of Gbps
3. Feature Velocity  Software designed to deliver a
common forwarding plane for multiple systems.
4. Multi-Generational  This is only the 1st Generation!
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 11
QFP Summary

• Packet Processing Engine (QFP-PPE)

– 40 Packet Processors – 4 Contexts (threads) each
– Up to 1.2GHz (Tensilica ISA) processors + DRAM packet memory
– Single TCAM4 I/F (can cascade 1-4 devices)
– C-language for feature development (extensive development support
tools)
– HW assist for flow-locks, look-ups, stats, WRED, policers, range lookup,
crypto, CRC
• Buffer/queue subsystem (QFP-BQS)
– HW hierarchical 3-parameter (min, max & excess) scheduler
– Fully configurable # of layers based on HQF
– Priority propagation through the multiple layers

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 12
 ASR 1000 ESP Generations
Roadmap

ESP5 ESP10 ESP10-N ESP20

Bandwidth 5Gbps 10Gbps 10Gbps 20Gbps

Based on QFP10 QFP10 QFP10 QFP10

# of Processors 20 40 40 40

Clock Rate 900 Mhz 900 Mhz 900 Mhz 1.2 Ghz

Crypto Engine BW 1.8Gbps 4Gbps NA 8Gbps

QFP Memory 256MB 512MB 512MB 1GB

Packet Buffer 64MB 128MB 128MB 256MB

TCAM 10Mb 10Mb 10Mb 40Mb

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 13
 SPA Interface Processor – SIP10

Physical termination of SPA

Supports up to 4 SPA’s
4 half-height, 2 full-height, 2 HH+1FH
full OIR support

Does not participate in forwarding

Limited QoS
– Ingress packet classification – high/low
– Ingress over-subscription buffering (low
priority) until ESP can service them. Up
to 128MB of ingress oversubscription
buffering

Capture stats on dropped packets

Network clock distribution to SPA’s,
reference selection from SPA’s

IOCP manages Midplane links, SPA OIR,
SPA drivers

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 14
 System Architecture - Dataplane

ESP RP RP ESP

All data forwarding is (active) (active) (standby) (standby)

through ESP
FECP RP RP FECP

Exception: Punt path
for Legacy protocols –
handled by the RP QFP
Interconn. Interconn.
QFP

SPI4.2
SPI4.2
subsys- Crypto subsys-
Crypto

Interconnect ASIC in assist tem assist tem

each of the functional

elements provides the Interconn. Interconn.

backplane connection
through ESI links
Midplane

ESI (Enhanced Serdes
Interconnect) links are
used for Data Interconn. Interconn. Interconn.

forwarding SPA IOCP SPA IOCP SPA IOCP

SPA-SPI links connect Agg. Agg. Agg.

to the backplane
through the SPA-Agg SPA … SPA SPA … SPA SPA … SPA
ASIC
ESI, 11.5Gbps
SPA-SPI, 11.2Gbps
Hypertransport, 10Gbps

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 15
 System Architecture Control Plane

ESP RP RP ESP

Two different control plane (active) (active) (Standby) (Standby)
links separate from the
dataplane links FECP FECP
RP RP
–Ethernet out-of-band
Channel (EOBC).
QFP QFP
–I2C - Monitor health of Crypto subsys-
tem
Crypto subsys-
tem
assist
hardware components assist

SPA control links Interconn. Interconn.

Run between IOCP and

SPAs Midplane

Interconn. Interconn. Interconn.

SPA IOCP SPA IOCP SPA IOCP

Agg. Agg. Agg.

SPA … SPA SPA … SPA SPA … SPA

EOBC - 1Gbps
I2C – Inter Integrated Circuit
SPA Control
SPA Bus
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 16
 What does the ESP Bandwidth mean?

ESP bandwidth denotes the total ‘output’ bandwidth of the system, regardless of
the direction

High priority traffic (as long as it is not over-subscribed - Example: <=10G for
ESP10) will not be affected by this bandwidth limit

ESP10 Examples:

5G 5G 1G 8G
5G ASR 1000
5G 2G ASR 1000
2G

5G Unicast in each direction 1G Multicast with 8X replication in one direction

Total Output bandwidth 5+5=10 2G unicast in the other direction
Total Output bandwidth 8+2=10G

5G 5G 1G 10G
6G 6G 1G 1G
ASR 1000 ASR 1000

5G Unicast in one direction & 6G Unicast 1G Multicast with 10X replication in one direction
in the other direction 1G Unicast in the other direction
Total output bandwidth (5+6=11) exceeds Total bandwidth (10+1=11) exceeds 10G; only 10G
10G; Only 10G will go through will go through
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 17
 ASR 1000 System Bandwidth

Total bandwidth of the system is determined by the following factors

– The type of forwarding engine : ESP5 or ESP10 or ESP20
– The type of SPA Interface Processor

SPA Interface Processors in the system share the ESP bandwidth,
regardless of the type of the SIP – 2XSIP in 4RU chassis and 3XSIP
in 6RU chassis
– ESP5 : 5G bandwidth shared among all SPAs (&built-in
interfaces on ASR 1002)
– ESP10 & ESP10-N : 10G bandwidth shared among all SPA
Interface Processors
– ESP20 : 20G bandwidth shared among all SPA Interface
Processors

The SIP bandwidth is the bandwidth of the link between one SPA
Interface Processor and the ESP
– SIP10 :10G link between SIP and ESP

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 18
 ESP & SIP Configurations

ESP10 ESP20
10G 20G

SIP10 SIP10
SIP10 SIP10

SIP10
SIP10

10G shared by
3 XSIP10 20G shared by
3XSIP10

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 19
I/O – Shared Port Adapters
• SPAs currently
ATM: • T3/E3 supported in other Ethernet: • FE
• OC3 Cisco Platforms will • GE
• OC12 also be supported on • 10GE
ASR 1000
POS: • OC3 • Please refer to Clear Chan.: • T3/E3
• OC12 Roadmap for roll-out
POS/DPT/RPR: • T1/E1
• OC48 plan Channelized:
• T3
• OC192
CEOP: • OC3 • STM1
RPR • GE • T3/E3 • OC12
• 10GE • T1/E1 • OC48

Single-Height Double- Height Double- Wide

X
SPA SPA SPA

© 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential Not supported on ASR 1000 20
 High Availability

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 21
 ASR 1000 HA Highlights

ASR 1000 leverages Cisco IOS HA infrastructure – NSF/SSO,

ISSU

1+1 redundancy option for RP and ESP
– Active and standby
– No load balancing

RP’s are separate from ESP’s
– Switchover of ESP does not result in switchover of RP
– Switchover of RP/IOS does not result in switchover of ESP

Single RP may be configured with dual IOS for SW redundancy
(single RP only)

No redundancy for SIP or other I/O cards
– SPA plugs into a single SIP

Protection against SPA or SIP failure is via APS or Y-cable
redundancy feature (Future: requires SPA support)

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 22
 System Architecture – Distributed Control Plane

Zero
Active Standby Packet
RP
Route
fails Becomes
Route Loss
HW
Processor
or SW Processor
Active

Active Standby
ESP ESP

SPA SPA SPA SPA SPA SPA

SPA Interface Processor SPA Interface Processor SPA Interface Processor

SPA SPA SPA SPA SPA SPA

Separate and independent internal communication link for control plane (GE)
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 23
 System Architecture – Centralized Data Plane

Minimal
Active Standby Data
Route Route Interruption
Processor Processor

Active
Active ESP fails Standby
Standby
(SWESP
or HW) ESPActive
Becomes

SPA SPA
SPA SPA SPA SPA
SPA Interface Processor SPA Interface Processor SPA Interface Processor

SPA SPA SPA SPA SPA SPA

• All packets processed by QFP for forwarding

• Separate and Independent links for Data Plane communication (ESI 11.5G)
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 24
 Software Architecture – IOS-XE

IOS-XE = IOS + IOS-XE Middleware
+ Platform Software Route Processor

Operational Consistency - same IOS
look and feel as IOS Router 12.2SR
(Active)

IOS runs as its own Linux process

for control plane (Routing, SNMP, IOS-XE “Middleware”
Chassis Forwarding Interface
CLI etc). 32bit and 64bit options. Manager Manager Manager

Linux kernel with multiple Kernel

processes running in protected
memory for
Control Messaging
– Fault containment
– Re-startability SPASPASPASPA QFP
Driver
Driver
Driver
Driver Client/Driver
– ISSU of individual SW
packages Interface Chassis Forwarding Chassis
Manager Manager Manager Manager

ASR 1000 HA Innovations

Kernel Kernel
– Zero-packet-loss RP Failover
– <50ms ESP Failover SPA Interface Processor Embedded Services
Processor
– “Software
ASR 1000 Overview Jul 07 Redundancy”
© 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 25
 Software Redundancy on 4RU/2RU Single RP/ESP
Stand-by IOS Active IOS
Process
Process Route Processor

Stand-by IOS process in
RP in the single-engine
4RU/2RU system IOS IOS
Backup Active

Two IOS process in a
single RP function
similar to different IOS-XE “Middleware”
processes on separate Chassis
Manager
Forwarding
Manager
Interface
Manager
RP
Linux Kernel

Support all NSF/SSO
features supported by
dual-RP systems

Requires additional RP
memory – 4G

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 26
 ASR 1000 Innovations: IOS XE
ASR 1006 Control & Forwarding Plane Redundancy Validated

IOS XE Upgrade IOS XE Upgrade IOS XE Upgrade

RP RP RP RP RP RP
Standby Active ISSU Active Standby ISSU Standby Active

IOS XE IOS XE IOS XE IOS XE IOS XE IOS XE

Zero Packet Loss Zero Packet Loss

Step Step
1 2

ESP ESP ESP ESP ESP ESP

Standby Active ISSU Active Standby ISSU Standby Active
QFP QFP QFP QFP QFP QFP
Zero Packet Loss 50ms Traffic Interruption
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 27
 ASR 1000 Innovations
Software Virtualization on Cisco ASR 1002 and 1004 Validated

IOS Upgrade IOS Upgrade IOS Upgrade

IOS IOS
IOS
Active Standby
IOS IOS IOS IOS IOS
Standby Active Active Standby Standby Active
ISSU
ISSU ISSU
ISSU
IOS XE IOS XE IOS XE
IOS XE
Step Step
1 2
Zero Packet Loss Zero Packet Loss

… Industry first,
delivering hitless upgrades without hardware redundancy

ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 28
ASR 1000 Overview Jul 07 © 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 29