INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. Theor. Appl. 2017; 45:843–850

Published online 4 August 2016 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.2248

LETTER
A 63-dB gain OTA operating in subthreshold with 20-nW power
consumption

Meysam Akbari*,† and Omid Hashemipour

Faculty of Electrical Engineering, Shahid Beheshti University, G.C., Tehran, Iran

SUMMARY
This paper presents a two-stage bulk-driven operational transconductance amplifier operating in weak-
inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, pos-
itive feedback source degeneration and indirect frequency compensation feedback to enhance
transconductance under a reasonable stability. Combining these approaches leads to an ultra-low-power high
performance amplifier without increasing power dissipation compared to the conventional one. Simulation
results in 0.13-μm complementary metal–oxide–semiconductor technology show the proposed structure
achieves a 63-dB DC gain at 0.25-V supply voltage with just 20-nW power dissipation. Copyright ©
2016 John Wiley & Sons, Ltd.

Received 2 April 2016; Revised 2 July 2016; Accepted 7 July 2016

KEY WORDS: operational amplifier; source degeneration; bulk-driven; weak inversion

1. INTRODUCTION

Biomedical and sensor applications need operating at low power supply like 0.25-V because of their
environment limitations. The weak-inversion region can be the best choice to design complementary
metal–oxide–semiconductor (CMOS) circuits because it provides the highest Gm/Id ratio for
transistors resulting in a high performance circuit [1]. In these applications, the operational
transconductance amplifiers (OTAs) are one of the important blocks in data converters.
Another important application of the OTAs is integrated filters which need high linearity and low
input referred noise [2, 3]. Decreasing power supply leads to the input voltage range degeneration
and consequently worse linearity that can be solved using bulk-driven technique. However, the
bulk-driven input differential pair suffers from lower (gmb/gm) ratio in CMOS technologies leading
to a lower performance [1,4]. To enhance (gmb/gm) ratio the recycling folded cascode structure in
[5, 6] has been reconfigured as a bulk-driven topology using composite transistors in [4]. Moreover,
positive feedback source degeneration technique has been employed in [1] to enhance efficiency of
a weak-inversion two-stage folded cascode (FC) amplifier. Nonetheless, the enhanced
transconductance of a positive feedback source degeneration topology has been increased again in
[7] using the quasi-floating gate method. All of the above mentioned techniques also improve the
slew-rate and gain bandwidth (GBW) of the weak-inversion OTAs in a single-stage structure. In
fact, for two-stage OTAs, the GBW is limited by the output pole while low (gmb/gm) ratio of the
input stage can be compensated by lower compensation capacitor [8]. Thus, the gain boosting
techniques for such structures are used to improve DC gain rather than transconductance [9, 10].

*Correspondence to: Meysam Akbari, Faculty of Electrical Engineering, Shahid Beheshti University, G.C., Tehran, Iran.
†
E-mail: Me_akbari@sbu.ac.ir

Copyright © 2016 John Wiley & Sons, Ltd.

844 M. AKBARI AND O. HASHEMIPOUR

This paper presents a novel bulk-driven topology in which utilized positive feedback source
degeneration and current recycling techniques. The presented input stage topology significantly
increases the performance of a conventional topology. The paper is organized as follows: Section 2
describes the structure of the proposed amplifier and the theoretical analyses are given for the small
signal transconductance and slew rate (SR). Section 3 provides the circuit level simulation results,
and finally, the conclusions are given in Section 4.

2. PROPOSED STRUCTURE

Figure 1 shows the conventional OTA with bulk-driven input stage. To enhance its transconductance,
the transistors M1b/M2b are used in Figure 2 to create a positive feedback source degeneration
topology. The generation of negative impedance in source terminal of the input differential pair can
increase the effective transconductance [1]. Moreover, the transistors M3/M4 pass the maximum DC
current in which generate the largest transconductance. Therefore, input signal can be applied to the
gate of these transistors to enhance transconductance again [4, 5]. The proposed bulk-driven
structure is shown in Figure 3. This figure shows that transistors M1a/M2a, M1b/M2b and
M1c/M2c are utilized as a novel input bulk-driven differential pair. The transistors M1b/M2b are
added to create a two-path structure and apply the input signal to transistors M3a/M4a by composite
transistors M4b/M6b and M3b/M5b. In fact, composite transistors help to have a constant drain
voltage of M3b/M4b causing an improvement in mismatch of the input differential pair [4].
To generate negative impedance in source terminal of the input differential pair the transistors
M1c/M2c are added to the proposed structure. These transistors introduce a positive feedback and
increase the effective transconductance. The cross coupled connection leads to instability, by which
a latchup can be occurred when a large signal is applied to the input. To prevent any latchup the
bulk terminal of source degenerated transistors can be controlled by input bulk-driven topology
causing a negative feedback at the source. In addition, the drain current of controller transistors
M1/M2 go through M3b/M4b that leads to a reduction of transferred transconductance by
M3b/M4b. Thus, to prevent flowing the drain current of M1/M2 through M3b/M4b two new
transistors M3c/M4c are used as current shunt technique. Therefore, according to mathematical
analysis in [1], Io1 = ID1b
ID2b and Io2 = ID1a
ID2a of the proposed structure can be given by

Figure 1. The conventional bulk-driven OTA.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2017; 45:843–850
DOI: 10.1002/cta
 AN ULTRA-LOW-POWER TRANSCONDUCTANCE AMPLIFIER 845

Figure 2. The enhanced bulk-driven OTA.

Figure 3. The proposed bulk-driven OTA. [Colour figure can be viewed at wileyonlinelibrary.com]

 
Vinþ
Vin

I o1 ¼ I o2 ¼ ðI Þtanh ðη þ 2Þ (1)
2ðη þ 1ÞU t

where η is the ratio of gmb/gm, and ID1b, ID2b, ID1a and ID2a are the drain current of M1b, M2b, M1a
and M2a, respectively. Thus, the output current of the first stage can be calculated by
 
Vinþ
Vin

I o ¼ kI o1 þ I o2 ¼ I ðk þ 1Þtanh ðη þ 2Þ (2)
2ðη þ 1ÞU t

where k is the current gain factor of M3a/M4a. Consequently, the first stage transconductance (internal

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2017; 45:843–850
DOI: 10.1002/cta
846 M. AKBARI AND O. HASHEMIPOUR

transconductance) can be given by

∂I o ηþ2
Gmin ¼ ¼ ðk þ 1Þgmb1a : (3)
∂Vinþ η
The optimum value for the parameter of k is presented in [5]. Nonetheless, in order to keep the
power dissipation unchanged for all structures, 3 is selected for it (k) in the current mirrors. The DC
current of transistors M1a/M2a in Figure 3 is halved of M1/M2 in Figure 1 (gmb1 = 2gmb1a).
Therefore, a significant improvement in the small signal transconductance and consequently an
enhancement of 20–23 dB in DC gain of the proposed amplifier can be achieved over the
conventional one.
Owing to the existence of extra paths in the novel topology, an improvement in the SR can be
observed. During slewing phase, the tail current (2I) never flows in only one of the input bulk-
driven transistors, because neither of them is driven into cut-off region. By assuming input
differential pair remain in saturation of weak-inversion region, equations (1) and (2) can be used to
calculate the positive and negative SRs. Therefore, internal and external SRs of the proposed
structure can be given by

Io
SRin ¼ (4)
Cc1 þ Cc2

 
SRþ þ SR
2I o þ pðI D1b þ
I D1b
Þ
SRex ¼ ¼ (5)
2 2C L
where p, Cc1 and Cc2 are the current gain factor of M9 and compensation capacitors, respectively.
From Figure 3 it can be observed that Io1 = (I+D1b
I

D1b); thus, the average SR can be simplified by

 
Io 2I o þ pI o1
SR ¼ min ; : (6)
Cc1 þ Cc2 2C L
Finally, for stability considerations, the proposed structure utilizes a feed-forward frequency
compensation path with two compensation capacitors [4,8]. Based on the concept of indirect
frequency compensation technique in [11], besides the Miller capacitor, another compensation
capacitor is located between a low impedance node of the first stage (source degenerated node of the
input differential pair) and the second stage output node. The existence of the Miller capacitor helps
to have an smooth edge of phase curve at GBW point while it does not happen just by using
indirect compensation capacitor. It means that combination of these techniques leads to a higher
GBW because it requires smaller compensation capacitors compared to the conventional structures.
Thus, in comparison with the enhanced structure shown in Figure 2, equation (6) can show a
significant enhancement in the average SR of the presented configuration.

3. SIMULATION RESULTS

The biasing currents (Iref) of the three designed OTAs (conventional, enhanced and proposed
amplifiers), in which have been designed in 0.13-μm CMOS technology, are set to 8 nA. For
operating in weak inversion region, the value of 250 mV has been selected for the minimum power
supply. Table I reports the transistor sizes and other component values that are used in simulation of
designed amplifiers.
Figure 4 shows the frequency response of designed amplifiers with the same phase margin for all
structures. This figure shows that because of the existence of feed-forward compensation path and
combination of Miller and indirect compensations in the proposed structure its phase and amplitude
curves are improved over the other structures. Therefore, the proposed topology has 62% and 100%
improvement in GBW compared to the conventional and enhanced amplifiers, respectively. In

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2017; 45:843–850
DOI: 10.1002/cta
 AN ULTRA-LOW-POWER TRANSCONDUCTANCE AMPLIFIER 847

Table I. Transistor sizes and other elements of designed amplifiers.

Parameter Conventional Enhanced Proposed
(W/L)b 8 × 11.9/0.25 8 × 11.9/0.25 8 × 11.9/0.25
(W/L)0 8 × 11.5/0.25 8 × 12.3/0.25 8 × 12.3/0.25
(W/L)1,2 4 × 11.9/0.25 — 1 × 11.9/0.25
(W/L)1a,2a — 4 × 17.6/0.25 2 × 17.6/0.25
(W/L)1b,2b — 4 × 14.6/0.25 2 × 17.6/0.25
(W/L)1c,2c — — 4 × 14.6/0.25
(W/L)3,4 8 × 4.9/0.25 8 × 4.9/0.25 —
(W/L)3a,4a — — 6 × 4.9/0.25
(W/L)3b,4b — — 2 × 4.9/0.25
(W/L)3c,4c — — 1 × 4.9/0.25
(W/L)3d — — 2 × 4.9/0.25
(W/L)5,6 4 × 37.2/0.25 4 × 37.2/0.25 4 × 37.2/0.25
(W/L)5b,6b — — 1 × 37.2/0.25
(W/L)5c — — 2 × 37.2/0.25
(W/L)7,8 4 × 11.9/0.25 4 × 11.9/0.25 4 × 11.9/0.25
(W/L)7b — — 2 × 11.9/0.25
(W/L)9 10 × 25.6/0.25 10 × 25.6/0.25 10 × 25.6/0.25
(W/L)10 10 × 58.1/0.25 10 × 58.1/0.25 10 × 58.1/0.25
Cc1 1 pF 6.7 pF 1.5 pF
Cc2 — — 1.5 pF
CL 15 pF 15 pF 15 pF
Iref 8 nA 8 nA 8 nA

Figure 4. Open-loop frequency response of designed OTAs. [Colour figure can be viewed at
wileyonlinelibrary.com]

addition, employing transconductance boosting techniques in the proposed structure resulted in an

improvement of 21.9 and 6.9 dB in DC gain compared to the conventional and enhanced structures,
respectively.
To calculate the SR and assess the overall stability, three OTAs are configured in voltage follower,
and a large step of 0.25 Vpp at 1 kHz is applied that is shown in Figure 5. The average SR of the
proposed OTA is 2.15 V/ms, which shows an enhancement of 250% compared to the enhanced
amplifier. Moreover, Figure 6 shows the simulated output and input waveforms of the proposed
amplifier as a voltage follower configuration, 10 Hz and 125-mV amplitude of the input sine wave.
This figure indicates that a rail-to-rail input/output swing is obtainable.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2017; 45:843–850
DOI: 10.1002/cta
848 M. AKBARI AND O. HASHEMIPOUR

Figure 5. Step response of designed OTAs with differential 1-kHz, 250-mVp-p input step. [Colour figure can
be viewed at wileyonlinelibrary.com]

Figure 6. The input and output waveforms of the proposed amplifier with rail-to-rail input signal at a 250-
mV power supply. [Colour figure can be viewed at wileyonlinelibrary.com]

To demonstrate the global process variations on main specifications of the proposed OTA, corner
analysis, temperature and power supply variations simulation are reported in Table II. To assist
comparing this work with the other works, two figures of merit (FoM) can be defined by

GBWC L SRC L
FoM 1 ¼ ; FoM 2 ¼ : (7)
Total current Total current

Table III summarizes the specifications of the proposed amplifier in comparison with conventional,
enhanced and other recent amplifiers. It can be seen that the proposed amplifier has better FOMs.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2017; 45:843–850
DOI: 10.1002/cta
 AN ULTRA-LOW-POWER TRANSCONDUCTANCE AMPLIFIER 849

Table II. Important specifications of the proposed amplifier in process corners, temperature variations, power
supply and load variations.
Corner analysis Supply variations Load variations

SS @ FF @ VDD
VDD + CL = CL =
Parameter SF FF SS FS 0 °C 70 °C 20% 20% 10 pF 20 pF
Unity gain 5.66 5.49 5.93 5.5 3.22 3.43 4.52 6.71 5.98 6.55
bandwidth [kHz]
Phase margin [°] 66.4 68.2 58.6 61.5 63.7 60.2 63.7 62.6 67.2 56.4
DC gain [dB] 54.4 52.2 68.2 63.9 60.55 50.2 56.4 65.3 63 63
Average slew rate 2.14 2.1 1.93 1.86 1.57 1.99 1.66 2.49 2.2 2.1
[V/ms]

Table III. Specifications of the proposed amplifier in comparison with conventional and enhanced amplifiers
and other works.

Parameter Conventional Enhanced Proposed [1] [9]

Power supply [mV] 250 250 250 250 500
Technology [μm] 0.13 0.13 0.13 0.13 0.18
Power dissipation [nW] 19 19 20 18 45 000
Capacitive load [pF] 15 15 15 15 1
GBW [kHz] 3.85 3.1 6.23 1.88 3200
Phase margin [degree] 62.6 62.6 62.5 52.5 58
PSRR @ 10 Hz 62.6 62.9 66.5 — —
CMRR @ 10 Hz 70.1 69.4 69.8 — 73
DC gain [dB] 41.1 56.1 63 60 56
Average slew rate [V/ms] 2.13 0.61 2.15 0.7 1050
THD @ 10 Hz (150mVpp) [%] 0.5 0.3 0.3 0.2 —
Maximum input/output signal 250/230 250/230 250/230 250/230 500/460
swing [mV]
Input referred noise @ 0.1 Hz 58.6 17.5 17.6 — —
[μV/√Hz]
FOM1 [Hz × pF/nA] 760 612 1117 391 35.5
FOM2 [(V/s) × pF/nA] 420 120 403 146 11.66

4. CONCLUSION

In this paper, transconductance enhancing techniques such as positive feedback source degeneration
and self-bias current mirrors are employed in the conventional two-stage FC amplifier. Moreover,
indirect frequency compensation feedback is employed to improve SR and GBW. Simulation results
show that the proposed OTA has high SR, high GBW (for fast settling) and high DC gain (for an
accurate final value).

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Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2017; 45:843–850
DOI: 10.1002/cta