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Analog paper

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Analog paper

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- PG Notes on Semiconductors (Part-2)
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- Bee Lecture Semiconductor

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in

Analog Electronics Circuits

in

• Objective

• To understand the diode operation and its equivalent circuits

• To understand various parameters of diodes

n.

• Load line analysis

• Diode applications in rectifiers; HWR,FWR

• Diode testing

• Zener diode

• Diode data sheets and specifications

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• Diode applications in clipper circuits

• Numerical

Semiconductor diode

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Basic operation

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n-type versus p-type

• n-type materials make the Silicon (or Germanium) atoms more negative.

• p-type materials make the Silicon (or Germanium) atoms more positive.

n.

• Join n-type and p-type doped Silicon (or Germanium) to form a p-n junction.

p-n junction

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• When the materials are joined, the negatively charged atoms of the n-type doped side

are attracted to the positively charged atoms of the p-type doped side.

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• The electrons in the n-type material migrate across the junction to the p-type material

(electron flow).

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• the ‘holes’ in the p-type material migrate across the junction to the n-type material

(conventional current flow).

• The result is the formation of a depletion layer around the junction.

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Depletion region

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Operating conditions

• No Bias

• Forward Bias

• Reverse Bias

No bias condition

• No external voltage is applied: VD = 0V and no current is flowing ID = 0A.

in

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Only a modest depletion layer exists

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Reverse bias condition

External voltage is applied across the p-n junction in the opposite polarity of the p- and n-

type materials.

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• The electrons in the n-type material are attracted towards the positive terminal and the

‘holes’ in the p-type material are attracted towards the negative terminal.

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Avalanche breakdown

Avalanche breakdown occurs when a high reverse voltage is applied to a diode and large

electric field is created across the depletion region. The effect is dependant on the doping

levels in the region of the depletion layer. Minority carriers in the depletion region

associated with small leakage currents are accelerated by the field to high enough energies

so that they ionise silicon atoms when they collide with them. A new hole-electron pair are

in

created which accelerate in opposite directions causing further collisions and ionisation and

avalanche breakdown

n.

Zener breakdown

Breakdown occurs with heavily doped junction regions (ie. highly doped regions are better

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conductors). If a reverse voltage is applied and the depletion region is too narrow for

avalanche breakdown (minority carriers cannot reach high enough energies over the distance

traveled ) the electric field will grow. However, electrons are pulled directly from the

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valence band on the P side to the conduction band on the N side. This type of breakdown is

not destructive if the reverse current is limited.

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• External voltage is applied across the p-n junction in the same polarity of the p- and n-

type materials.

• The depletion layer is narrow.

• The electrons from the n-type material and ‘holes’ from the p-type material have

vt

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in

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Diode current expression:

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ID = Is( eVD / VT-1)

• Is : Reverse saturation current

• q : Charge of an electron

• k : Boltzman constant 11600/η

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• T : Environment temperature in °K

[ °K = °C + 273 ]

• η =2 for silicon , η=1 for Germanium

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A diode, as any semiconductor device is not perfect!

There are two sets of currents:

vt

• Majority Carriers

The electrons in the n-type and ‘holes’ in the p-type material are the source of the

majority of the current flow in a diode.

• Minority Carriers

Electrons in the p-type and ‘holes’ in the n-type material are rebel currents. They produce

a small amount of opposing current.

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Zener Region

in

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Zener region

Zener diode operation:

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• At some point the reverse bias voltage is so large the diode breaks down.

• The reverse current increases dramatically.

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• This maximum voltage is called avalanche breakdown voltage and the current is

called avalanche current.

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Forward Bias Voltage

• No Bias condition to Forward Bias condition happens when the electron and ‘holes’

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• This energy comes from the external voltage applied across the diode.

The Forward bias voltage required for a

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Temperature Effects on performance of diode

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• As temperature increases it adds energy to the diode.

• It reduces the required Forward bias voltage in Forward Bias condition

It increases the amount of Reverse current in Reverse Bias condition

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• It increases maximum Reverse Bias Avalanche Voltage

• Germanium diodes are more sensitive to temperature variations than Silicon Diodes.

Resistance Levels

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There are 3 types of resistances.

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• DC or Static Resistance

• AC or Dynamic Resistance

• Average AC Resistance

vt

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DC or Static Resistance

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RD=VD / ID

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DC or static resistance

• For a specific applied DC voltage VD, the diode will have a specific current ID,

and a specific resistance RD.

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• The amount of resistance RD, depends on the applied DC voltage.

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AC or Dynamic Resistance

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Forward Bias region:

Rd=∆vd/ ∆Id

• The voltage across the diode is fairly constant (VT = 26mV for 25°C).

in

• Reverse Bias region:

Rd=∞

The resistance is essentially infinite. The diode acts like an open.

n.

Average AC Resistance

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Diode equivalent circuits

the actual terminal characteristics of a device, system or such a particular operating

region.

• Then device symbol can be replaced with the equivalent circuit which makes the

analysis of the circuit easy and straight forward.

in

Piece wise linear equivalent circuit

n.

io

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One technique for obtaining equivalent circuit is to approximate the characteristics of the

device by straight line segments

• Rd defines the resistance level of the device when it is in the ON state.

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• Ideal diode is included to establish that there is only one direction of conduction

through the device.

• Since silicon semiconductor diode does not conduct until VD of 0.7V is reached, a

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vt

• In most of the applications, resistance rav is very small in comparison to the other

elements of the network.

• Removal of this rav from the network makes a simplified equivalent circuit.

• And an ideal diode will start conduction for zero applied voltage.

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Transition and diffusion capacitance

in

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• The figure shows the capacitance v/s applied voltage across the diode.

• Shunt capacitive effects that can be ignored at very lower frequencies since Xc=1/2πfc

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is very large (open circuit)

• However this can not be neglected in very high frequencies since it introduces a low

reactance (shorting) path.

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• Two types of capacitive effects to be considered in FB and RB condition.

• In RB region transition or depletion region capacitance CT in FB diffusion

capacitance CD or storage capacitance.

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• W.k.t C=εA/d.

• ε is the permittivity of dielectric between tow plates of area A separated by distance d.

• In RB, depletion region which is free of carriers that behaves essentially like an

vt

insulator between the layers of opposite charges. This depletion region width increase

with increase in RB potential.

• Since d is increasing, capacitance effect is more in FB.

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Diode characteristics

in

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Diode characteristics

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• Denoted by trr.

vt

and large number of holes in p-type is a requirement for conduction. The electrons in

p-type and holes progressing through n-type establish a large number of minority

carriers in each material.

• Now if the diode is changed from FB to RB

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• The diode will not instantaneously react to this sudden change. Because of the large

number of minority carriers in each material, the current sustains in diode for a time ts

storage time which is required for minority carriers to return to their majority carrier

state in the opposite material.

• Eventually current will reduce to non conduction levels.

• This time is tt transition interval

• Hence trr= ts + tt

in

• This is very important consideration in high frequency operation.

• Commercially available diodes have reverse recovery time of few nano seconds to

n.

1micro second.

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• The applied load will normally have an important impact on region of operation of

device.

• If analysis is done in graphical approach, a line can be drawn on the characteristics of

vt

• The intersection of load line with the characteristics will determine the point of

operation.

• Such an analysis is called as load-line analysis.

• The intersection point is called ‘Q’ point or operating point.

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• Its very simple as compared to the non-linear analysis of diode which involves heavy

maths……

iR

iD

in

n.

By KVL : VSS Ri D v D

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By KCL : i R i D

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i-v curves plotted for diode (energised by Vss)

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VSS

When v D 0; i R

R

VSS vD

iD

R

in

When v D VSS ; i R 0

n.

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We can combine these curves on one plot to do a load line analysis

ut

ol

By KVL : VSS Ri D v D

By KCL : i R i D

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Example on load line analysis

iR Assume : VSS 3V

and R 150.

iD

When v D 0 :

in

VSS

i R iD 20mA

R

When v D VSS :

n.

i R iD 0

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iD = VSS/R = 20mA

iD = 12.5mA

vD = 1.25V

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Operating Point:

KVL and KCL

satisfied

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iD = 0

vt

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Diode approximations

In the approximate model of diode, the rav is not used since the value of this rav is

much less than other series elements of the network.

This model results in less expenditure of time and effort to obtain results.

Unless otherwise mentioned this approximate model is used hereforth…

in

Series diode configuration with DC inputs

• When connected to voltage sources in series, the diode is on if the applied voltage is

n.

in the direction of forward-bias and it is greater than the VT of the diode

• When a diode is on, we can use the approximate model for the on state

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Here, VD = VT, VR = E - VT

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ID = IR = VR / R

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in

Here, VD = E, VR = 0, ID = 0

Keep in mind that KVL has to be satisfied under all

conditions

n.

Parallel diode configuration

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Determine I1 , VD1 , VD2 and V0 for the parallel diode circuit in below figure

ut

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Solution

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Examples

1. Find diode current and output voltage

in

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Solution:

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2. Solve for I , v1,v2 and vo

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3.Determine unknown parameters

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4.Determine unknown parameters

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Rectifiers :

in

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For the half-wave rectified signal:

Vdc = 0.318 Vm

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considered, the output of the

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Vdc = 0.318 (Vm- VT)

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Effect of VT on half-wave rectified signal

in

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PIV rating of Half-wave Rectifiers

PIV rating is very important consideration for rectifier circuits

PIV ≥ Vm

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For the half-wave rectifier must be equal or must not exceed the peak value of the applied voltage

ut

This is the voltage rating that must not be exceeded in the reverse bias region

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Non Ideal Waveform

in

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Half-wave Rectifier

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vt

1

2 0

VAV VM sin d 0

VM

cos cos 0 VM

2

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in

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Working :

• For the positive half of the AC cycle:

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• Diode D1 and D2 gets forward biased and conducts.

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Working :

• For the negative half of the AC cycle

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• Diode D3 and D4 gets forward biased and conducts during this half cycle.

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Details of working of FWR

n.

• The four-diode bridge can be bought as a package During positive half cycles vi is

positive.

• Current is conducted through diodes D1, resistor R and diode D2

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• Meanwhile diodes D3 and D4 are reverse biased

• During negative half cycles vi is negative.

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• Current is conducted through diodes D3, resistor R and diode D4

• Meanwhile diodes D1 and D2 are reverse biased.

• Current always flows the same way through the load R.

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• the average d.c. value of this full-wave-rectified sine wave is VAV = 2VM/ (i.e. twice

the half-wave value)

• Two diodes are in the conduction path.

• Thus in the case of non-ideal diodes vo will be lower than vi by 2VC.

• As for the half-wave rectifier a reservoir capacitor can be used. In the full wave case

the discharge time is T/2 and

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VMT

ΔV

2RC

in

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• Two diodes and a center-tapped transformer are required.

• VDC = 0.636(Vm)

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• Note that Vm here is the transformer secondary voltage to the tap.

Operation

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For the positive half of the AC cycle:

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For the negative half of the AC cycle:

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Summary

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Note: Vm = peak of the AC voltage.

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• Clippers have ability to “clip/remove” off a portion of the input signal without

distorting the remaining part of the alternating waveform.

• HWR is simplest form of clippers. The orientation of diode is going to decide the part

of sinusoidal waveform to be clipped off.

in

Clipper configuration

Depending on the way in which the diodes are connected with the input, the clipper are

classified in to two major categories, viz.,

n.

• Series configuration

• Parallel configuration

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3. Series clipper ex – 3 & 4

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4. Series clipper Ex - 5 & 6

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Various clipepr examples along with transfer characteristics

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Biased parallel clippers

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Diode testing :

in

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One problem with using an ohmmeter to check a diode is that the readings obtained

only have qualitative value, not quantitative. In other words, an ohmmeter only tells you

which way the diode conducts; the low-value resistance indication obtained while

ut

conducting is useless. If an ohmmeter shows a value of “1.73 ohms” while forward-biasing a

diode, that figure of 1.73 Ω doesn't represent any real-world quantity useful to us as

ol

technicians or circuit designers.

It neither represents the forward voltage drop nor any “bulk” resistance in the

semiconductor material of the diode itself, but rather is a figure dependent upon both

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quantities and will vary substantially with the particular ohmmeter used to take the reading.

For this reason, some digital multimeter manufacturers equip their meters with a special

“diode check” function which displays the actual forward voltage drop of the diode in volts,

rather than a “resistance” figure in ohms. These meters work by forcing a small current

vt

through the diode and measuring the voltage dropped between the two test leads. (Figure

below)

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in

n.

Meter with a “Diode check” function displays the forward voltage drop of 0.548 volts instead of a low resistance.

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The forward voltage reading obtained with such a meter will typically be less than the

“normal” drop of 0.7 volts for silicon and 0.3 volts for germanium, because the current

ut

provided by the meter is of trivial proportions. If a multimeter with diode-check function

isn't available, or you would like to measure a diode's forward voltage drop at some non-

trivial current, the circuit of Figure below may be constructed using a battery, resistor, and

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voltmeter

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vt

(a) Schematic diagram. (b) Pictorial diagram

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2. Curve tracers

Device could be diode or transistor or other semiconductor device.

Curve tracer by tektronix and other companies available

Easy to use and testing with less effort and time.

in

Diode specifications

n.

• Manufacturers provide these information

• Usually given in easy readable formats like graphs, artwork, tables and so on.,

• These specifications are required for proper utilization of devices for specific

applications

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Important data to be considered are

Maximum forward current IF

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Maximum reverse saturation current IR

The reverse voltage rating (PIV)

Maximum power dissipation

Capacitance levels

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Operating temperature range

Depending on type of diode being used, additional data such as

Frequency

Noise level

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Switching time

Thermal resistance

Peak repetitive values are also provided

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For IN4001 and 4007

in

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Maximum ratings are those values beyond which device damage can occur.

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Zener diodes

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• By proper doping of the silicon, the “Zener Breakdown” can be made to have a very

“sharp breakdown”.

ut

• The breakdown voltage is commonly labeled as VZ.

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vt

resistor rZ.

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• The approximate model is obtained just by neglecting the effect of rZ in the equivalent

model. Only a constant voltage source is used in this model.

• The temperature coefficients reflects the percentage change in VZ with temperature

and it is defined by the relation

• Tc={∆V Z/ VZ( T1-T0) } x 100%

• ∆VZ change in zener potential due to temperature variation

• (T1-T0) change in temperature

in

Examples

n.

1. Det. Nominal voltage for 1N961 fairchild zener diode at temp of 1000c.

Solution:

∆VZ=Tc VZ(T1-T0)/100

={0.072x10V/100}(1000-250)

= 0.54V

io

Therefore change in Zener voltage is 10.54V when temperature is raised from 250c to 1000c.

ut

2. Find Is and vL using zener characteristics for given data.

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vt

3. Compute the Thevenin equivalent of the previous circuit with the zener diode as the

load

Thevenin voltage

Thevenin resistance

We can then write VT +RTiD+vD = 0 and find out vD,, iD using the zener diode

characteristics

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vL = vD and IS = vL /RL + iD

Solution

in

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Answers

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• vL = 10V

• IS = vL /RL + iD = 10/6 +10 mA = 11.67mA

• vL = 9.5 V

• IS = vL /RL + iD = 9.5/1.2 +5 mA = 12.92mA

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in

General Approach:

• Assume the state of each of the diodes: i.e., “on” or “off”.

n.

• Analyze the circuit and check to see if your assumptions were correct.

• If not correct try another set of assumptions.

• Assume D1 is “off”: Replace with open

• Assume D2 is “on”: Replace with short

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vD1 = 10V – 3V = 7V

But this is not possible since the D1 would be forward biased or “on” with vD1 = 0V.

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Example 2

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Objectives

To Understand :

• Concept of Operating point and stability

• Analyzing Various biasing circuits and their comparison with respect to stability

in

BJT – A Review

• Contains three adjoining, alternately doped semiconductor regions: Emitter (E),

Base (B), and Collector (C)

n.

• The middle region, base, is very thin

• Emitter is heavily doped compared to collector. So, emitter and collector are not

interchangeable.

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– Base – emitter junction forward biased

– Base – collector junction reverse biased

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• Cutoff – region operation:

– Base – emitter junction reverse biased

– Base – collector junction reverse biased

• Saturation – region operation:

– Base – emitter junction forward biased

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– Base – collector junction forward biased

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• The values of the parameters IB, IC and VCE together are termed as ‘operating

point’ or Q ( Quiescent) point of the transistor.

Q-Point

• The intersection of the dc bias value of IB with the dc load line determines the Q-

point.

• It is desirable to have the Q-point centered on the load line. Why?

• When a circuit is designed to have a centered Q-point, the amplifier is said to be

in

midpoint biased.

• Midpoint biasing allows optimum ac operation of the amplifier.

Introduction - Biasing

n.

The analysis or design of a transistor amplifier requires knowledge of both the dc and

ac response of the system.In fact, the amplifier increases the strength of a weak signal

by transferring the energy from the applied DC source to the weak input ac signal

• The analysis or design of any electronic amplifier therefore has two components:

• The dc portion and

• The ac portion

io

During the design stage, the choice of parameters for the required dc levels will

affect the ac response.

ut

What is biasing circuit?

• Once the desired dc current and voltage levels have been identified, a network

must be constructed that will establish the desired values of IB, IC and VCE, Such a

network is known as biasing circuit. A biasing network has to preferably make

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use of one power supply to bias both the junctions of the transistor.

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• To place it in operation in the region of its characteristic where the device

operates most linearly, i.e. to set up the initial dc values of IB, IC, and VCE

vt

• VBE = 0.7V

• IE = ( + 1) IB IC

• IC = IB

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Biasing circuits:

• Emitter bias

• Voltage divider bias

• DC bias with voltage feedback

• Miscellaneous bias

Fixed bias

in

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• The simplest transistor dc bias configuration.

• For dc analysis, open all the capacitance.

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DC Analysis

vt

• From the above equation, deriving for IB, we get,

IB = [VCC – VBE] / RB

• The selection of RB sets the level of base current for the operating point.

• Applying KVL for the output loop:

VCC = ICRC + VCE

• Thus,

VCE = VCC – ICRC

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VCE = VE

VBE = VB

• Design: Given – IB, IC , VCE and VCC, or IC , VCE and , design the values of RB,

RC using the equations obtained by applying KVL to input and output loops.

in

• Analysis: Given the circuit values (VCC, RB and RC), determine the values of IB,

IC , VCE using the equations obtained by applying KVL to input and output loops.

n.

Problem – Analysis

Given the fixed bias circuit with VCC = 12V, RB = 240 k, RC = 2.2 k and = 75.

Determine the values of operating point.

io

IB = [VCC – VBE] / RB where VBE = 0.7V,

thus substituting the other given values in the equation, we get

IB = 47.08uA

ut

IC = IB = 3.53mA

VCE = VCC – ICRC = 4.23V

• When the transistor is biased such that IB is very high so as to make IC very high

such that ICRC drop is almost VCC and VCE is almost 0, the transistor is said to be

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in saturation.

IC sat = VCC / RC in a fixed bias circuit.

Verification

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• Whenever a fixed bias circuit is analyzed, the value of ICQ obtained could be

verified with the value of ICSat ( = VCC / RC) to understand whether the transistor is

in active region.

• In active region,

ICQ = ( ICSat /2)

vt

A fixed bias circuit with given values of VCC, RC and RB can be analyzed ( means,

determining the values of IBQ, ICQ and VCEQ) using the concept of load line also.

Here the input loop KVL equation is not used for the purpose of analysis, instead, the

output characteristics of the transistor used in the given circuit and output loop KVL

equation are made use of.

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1. Consider the equation VCE = VCC – ICRC This relates VCE and IC for the given IB

and RC

2. Also, we know that, VCE and IC are related through output characteristics

We know that the equation,

VCE = VCC – ICRC

represents a straight line which can be plotted on the output characteristics of the

transistor.

in

Such line drawn as per the above equation is known as load line, the slope of which is

decided by the value of RC ( the load).

Load line

n.

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• The two extreme points on the load line can be calculated and by joining which

the load line can be drawn.

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• To find extreme points, first, Ic is made 0 in the equation: VCE = VCC – ICRC .

This gives the coordinates (VCC,0) on the x axis of the output characteristics.

• The other extreme point is on the y-axis and can be calculated by making VCE = 0

in the equation VCE = VCC – ICRC which gives IC( max) = VCC / RC thus giving the

coordinates of the point as (0, VCC / RC).

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• The two extreme points so obtained are joined to form the load line.

• The load line intersects the output characteristics at various points corresponding

to different IBs. The actual operating point is established for the given IB.

Q point variation

vt

As IB is varied, the Q point shifts accordingly on the load line either up or down

depending on IB increased or decreased respectively.

As RC is varied, the Q point shifts to left or right along the same IB line since the

slope of the line varies. As RC increases, slope reduces ( slope is -1/RC) which

results in shift of Q point to the left meaning no variation in IC and reduction in VCE .

Thus if the output characteristics is known, the analysis of the given fixed bias circuit

or designing a fixed bias circuit is possible using load line analysis as mentioned

above.

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Emitter Bias

• It can be shown that, including an emitter resistor in the fixed bias circuit

improves the stability of Q point.

• Thus emitter bias is a biasing circuit very similar to fixed bias circuit with an

emitter resistor added to it.

in

n.

Input loop

io

ut

ol

us

VCC = IBRB + VBE + IERE (1)

We know that,

IE = (+1)IB (2)

Substituting this in (1), we get,

vt

VCC – VBE = IB(RB + (+1) RE)

IB = (VCC – VBE ) /[(RB + (+1) RE)]

6

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IB = (VCC – VBE ) /RB

Equivalent input loop:

in

n.

•

• io

REI in the above circuit is (+1)RE which means that, the emitter resistance that is

common to both the loops appears as such a high resistance in the input loop.

ut

Output loop

ol

us

vt

Applying KVL,

VCC = ICRC + VCE + IERE

IC is almost same as IE

7

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Vtusolution.in

Thus,

= IC (RC + RE) +VCE

VCE = VCC - IC (RC + RE)

Since emitter is not connected directly to ground, it is at a potential VE, given by,

in

VE = IERE

VC = VCE + VE OR VC = VCC – ICRC

Also, VB = VCC – IBRB OR VB = VBE + VE

n.

Problem:

= 75, VCC = 16V, RB = 430k, RC = 2k and RE = 1k

io

ut

ol

Solution:

us

IC = ( 75) (30.24A) = 2.27mA

VCE = VCC - IC (RC + RE) = 9.19V

VC = VCC – ICRC = 11.46V

vt

VE = VC – VCE = 2.27V

VB = VBE + VE = 2.97V

VBC = VB – VC = 2.97 – 11.46 = - 8.49V

8

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• Addition of emitter resistance makes the dc bias currents and voltages remain

closer to their set value even with variation in

– transistor beta

– temperature

in

Stability

In a fixed bias circuit, IB does not vary with and therefore whenever there is an

increase in , IC increases proportionately, and thus VCE reduces making the Q point

n.

to drift towards saturation.In an emitter bias circuit, As increases, IB reduces,

maintaining almost same IC and VCE thus stabilizing the Q point against variations.

Saturation current

io

VCC = IC ( RC + RE )

ut

IC,sat = VCC / ( RC + RE )

The two extreme points on the load line of an emitter bias circuit are,

ol

us

+V CC

RC

vt

R1

v out

C2

C1

v in

R2

RE C3

9

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Vtusolution.in

This is the biasing circuit wherein, ICQ and VCEQ are almost independent of .

The level of IBQ will change with so as to maintain the values of ICQ and VCEQ almost

same, thus maintaining the stability of Q point.

Exact method – can be applied to any voltage divider circuit

Approximate method – direct method, saves time and energy, can be applied in most of

the circuits.

in

Exact method

In this method, the Thevenin equivalent network for the network to the left of the base

terminal to be found.

n.

io

ut

To find Rth:

ol

us

Rth = R1 R2

vt

= R1 R2 / (R1 + R2)

10

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Vtusolution.in

To find Eth

in

From the above circuit,

n.

Eth = VR2 = R2VCC / (R1 + R2)

io

ut

In the above network, applying KVL

ol

IB = ( Eth – VBE) / [ Rth +( + 1) RE ]

us

IE IC

vt

11

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Problem

Given the values of R1, R2, RC, RE and = 140 and VCC = 18V.

For the purpose of DC analysis, all the capacitors in the amplifier circuit are opened.

in

n.

io

ut

Solution

ol

us

= 1.64V

3. Then find IB

IB = ( Eth – VBE) / [ Rth +( + 1) RE ]

= 4.37A

vt

= 12.63V

12

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Vtusolution.in

Approximate analysis:

The input section of the voltage divider configuration can be represented by the network

shown in the next slide.

Input Network

in

n.

io

The emitter resistance RE is seen as (+1)RE at the input loop.

If this resistance is much higher compared to R2, then the current IB is much smaller than

ut

I2 through R2.

This means, Ri >> R2

OR

(+1)RE 10R2

ol

OR

RE 10R2

us

Thus I1 through R1 is almost same as the current I2 through R2.

Thus R1 and R2 can be considered as in series.

Voltage divider can be applied to find the voltage across R2 ( VB)

VB = VCCR2 / ( R1 + R2)

vt

VE = VB – VBE

After finding VE, IE is calculated as,

IE = VE / RE

IE IC

VCE = VCC – IC ( RC + RE)

13

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Problem

Given: VCC = 18V, R1 = 39k , R2 = 3.9k , RC = 4k , RE = 1.5k and = 140.

Analyse the circuit using approximate technique.

In order to check whether approximate technique can be used, we need to verify the

condition,

RE 10R2

in

Here,

RE = 210 k and 10R2 = 39 k

n.

Thus the condition

RE 10R2 satisfied

Solution

io

Thus approximate technique can be applied.

2. Find VE = VB – 0.7 = 0.94V

ut

3. Find IE = VE / RE = 0.63mA = IC

4. Find VCE = VCC – IC(RC + RE) = 12.55V

ol

Comparison

us

IC = 0.612mA IC = 0.63mA

vt

Both the methods result in the same values for IC and VCE since the condition RE

10R2 is satisfied.

It can be shown that the results due to exact analysis and approximate analysis have

more deviation if the above mentioned condition is not satisfied.

For load line analysis of voltage divider network, Ic,max = VCC/ ( RC+RE) when VCE

= 0V and VCE max = VCC when IC = 0.

14

Vtusolution.in

Vtusolution.in

in

n.

Input loop

io

ut

ol

us

IB = ( VCC – VBE) / [ RB + ( RC + RE)]

Output loop

vt

15

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Vtusolution.in

Neglecting the base current, KVL to the output loop results in,

in

n.

Input loop

io

ut

ol

us

IC IC and IC IE

Substituting for IE as ( +1)IB [ or as IB] and solving for IB,

vt

Output loop

16

Vtusolution.in

Vtusolution.in

in

Neglecting the base current, and applying KVL to the output loop results in,

n.

In this circuit, improved stability is obtained by introducing a feedback path from

collector to base.

Sensitivity of Q point to changes in beta or temperature variations is normally less than

Problem:

Given: io

that encountered for the fixed bias or emitter biased configurations.

ut

VCC = 10V, RC = 4.7k, RB = 250 and RE = 1.2k. = 90.

Analyze the circuit.

ol

= 11.91A

IC = ( IB ) = 1.07mA

VCE = VCC – IC ( RC + RE) = 3.69V

us

With the same procedure as followed in the previous problem, we get

IB = 8.89A

IC = 1.2mA

vt

VCE = 2.92V

50% increase in resulted in 12.1% increase in IC and 20.9% decrease in VCEQ

Problem 2:

17

Vtusolution.in

Vtusolution.in

in

n.

Solution:

Open all the capacitors for DC analysis.

io

RB = 91 k + 110 k = 201k

IB = ( VCC – VBE) / [ RB + ( RC + RE)]

ut

= (18 – 0.7) / [ 201k + 75( 3.3+0.51)]

= 35.5A

IC = IB = 2.66mA

VCE = VCC – (ICRC)

ol

= 18 – ( 2.66mA)(3.3k)

= 9.22V

Load line analysis

us

The two extreme points of the load line IC,max and VCE, max are found in the same as a

voltage divider circuit.

vt

18

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Vtusolution.in

There are a number of BJT bias configurations that do not match the basic types of

biasing that are discussed till now.

in

n.

Solution

io

This circuit is same as DC bias with voltage feedback but with no emitter resistor.

ut

Thus the expression for IB is same except for RE term.

= ( 20 – 0.7) / [680k + (120)(4.7k)]

ol

= 15.51A

IC = IB = 1.86mA

VCE = VCC – ICRC = 11.26V = VCE

us

VB = VBE = 0.7V

VBC = VB – VC = 0.7V – 11.26V = - 10.56V

vt

19

Vtusolution.in

Vtusolution.in

in

Equivalent circuit

n.

io

ut

Input loop

ol

us

vt

Output loop

20

Vtusolution.in

Vtusolution.in

in

Solution

n.

The above circuit is fixed bias circuit.

Applying KVL to input loop:

VEE = VBE + IBRB

io

IB = ( VEE – VBE) / RB = 83A

IC = IB = 3.735mA

VC = -ICRC = - 4.48V

ut

VB = - IBRB = - 8.3V

Miscellaneous bias (3)

Determine VCE,Q and IE for the network.

Given = 90

ol

( Note that the circuit given is common collector mode which can be identified by

No resistance connected to the collector output taken at the emitter)

us

vt

21

Vtusolution.in

Vtusolution.in

in

n.

Input loop

io

ut

ol

us

IB = (VEE – VBE ) / [RB + (+1) RE]

= ( 20 – 0.7) / [ 240K + (91)(2K)]

= 45.73A

vt

IC = IB = 4.12mA

22

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Vtusolution.in

Output loop

in

n.

Applying KVL to the output loop:

VEE = VCE + IERE

IE = (+1) IB = 4.16mA, VEE = 20V

VCE = VEE – IERE = 11.68V

ut

Find VCB and IB for the Common base configuration given:

Given: = 60

ol

us

Input loop

vt

23

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Vtusolution.in

IE = ( VEE – VBE ) / RE

= 2.75mA

IE = IC = 2.75mA

IB = IC / = 45.8A

Output loop

in

n.

Applying KVL to output loop:

io

VCC = ICRC + VCB

ut

VCB = VCC – ICRC = 3.4V

Miscellaneous bias (5)

Determine VC and VB for the network given below.

ol

Given = 120

Note that this is voltage divider circuit with split supply.

( +VCC at the collector and – VEE at the emitter)

us

vt

24

Vtusolution.in

Vtusolution.in

in

n.

io

ut

Rth= (8.2k)(2.2k) / [ 8.2k+2.2k] = 1.73k

I = (VCC + VEE) / [R1 + R2]

ol

= ( 20 + 20) / ( 8.2K + 2.2K)

= 3.85mA

Eth = IR2 – VEE

us

= - 11.53V

Equivalent circuit

vt

25

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Vtusolution.in

Applying KVL:

VEE – Eth – VBE – ( +1)IBRE – IBRth = 0

IB = ( VEE – Eth – VBE ) / [( +1) RE + Rth ]

= 35.39A

IC = IB = 4.25mA

VC = VCC – ICRC = 8.53V

in

VB = - Eth – IBRth = - 11.59V

Design Operations:

Designing a circuit requires

n.

Understanding of the characteristics of the device

The basic equations for the network

Understanding of Ohms law, KCL, KVL

io

If the transistor and supplies are specified, the design process will simply

determine the required resistors for a particular design.

Once the theoretical values of the resistors are determined, the nearest

ut

standard commercial values are normally chosen.

Operating point needs to be recalculated with the standard values of resistors

chosen and generally the deviation expected would be less than or equal to 5%.

ol

Problem:

• Given ICQ = 2mA and VCEQ = 10V. Determine R1 and RC for the network shown:

us

vt

Solution

To find R1:

26

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2. Thus, VE = IERE and IE IC = 2mA

= (2mA)(1.2k) = 2.4V

3. VB =2.4 + 0.7 = 3.1V

4. Also, VB = VCCR2 /(R1 + R2)

3.1 = (18)(18k) / R1+18k

Thus, R1 = 86.52k

in

To find RC :

Voltage across RC = VCC – ( VCE + IERE)

= 18 – [ 10 + (2mA)1.2k]

= 5.6V

n.

RC = 5.6/2mA

= 2.8K

Nearest standard values are,

R1 = 82k + 4.7 k = 86.7 k where as calculated value is 86.52 k .

RC = 2.7k in series with 1k = 2.8k

io

both would result in a very close value to the design level.

Problem 2

ut

The emitter bias circuit has the following specifications: ICQ = 1/2Isat, Isat = 8mA, VC =

18V, VCC = 18V and = 110. Determine RC , RE and RB.

Solution:

ol

ICQ = 4mA

VRC = (VCC – VC) = 10V

RC = VRC / ICQ,

us

= 10/4mA = 2.5k

To find RE: ICsat = VCC / (RC + RE)

To find RB: Find IB where, IB = IC / = 36.36A

Also, for an emitter bias circuit,

vt

Thus, RB = 639.8 k

Standard values: RC = 2.4 k, RE = 1 k, RB = 620 k

27

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Thus, RE = 1k

Through proper design transistors can be used as switches for computer and control

applications.

When the input voltage VB is high ( logic 1), the transistor is in saturation ( ON). And

the output at its collector = VCE is almost 0V( Logic 0)

in

Transistor as a switch

When the base voltage VB is low( logic 0), i.e, 0V, the transistor is cutoff( Off) and IC

is 0, drop across RC is 0 and therefore voltage at the collector is VCC.( logic 1)

n.

Thus transistor switch operates as an inverter.

This circuit does not require any DC bias at the base of the transistor.

Design

io

When Vi ( VB) is 5V, transistor is in saturation and ICsat

Just before saturation, IB,max = IC,sat / DC

Thus the base current must be greater than IB,max to make the transistor to work in

saturation.

ut

Analysis

ol

us

vt

IB = (Vi – 0.7) / RB

28

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= ( 5 – 0.7) / 68k

= 63A

ICsat = VCC / RC = 5/0.82k

= 6.1mA

Verification

( IC,sat / ) = 48.8A

in

Thus IB > ( IC,sat / ) which is required for a transistor to be in saturation.

A transistor can be replaced by a low resistance Rsat when in saturation ( switch on)

n.

Rsat = VCE sat/ ICsat (VCE sat is very small and ICsat is IC,max is maximum current)

A transistor can be replaced by a high resistance Rcutoff when in cutoff ( switch on)

Problem

Determine RB and RC for the inverter of figure:

io

ut

ol

us

IC sat = VCC / RC

10mA = 10V/ RC

RC = 1k

IB just at saturation = IC sat /

vt

= 10mA / 250

= 40A

Choose IB> IC sat / , 60 A

IB = (Vi – 0.7) / RB

60 A = ( 10 – 0.7) / RB

29

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RB = 155k

Choose RB = 150k, standard value,

re calculate IB, we get IB = 62 A which is also > IC sat /

Thus, RC = 1k and RB = 155k

Switching Transistors

in

Transistor ‘ON’ time = delay time + Rise time

Delay time is the time between the changing state of the input and the beginning of a

response at the output.

Rise time is the time from 10% to 90% of the final value.

n.

Transistor ‘OFF’ time = Storage time + Fall time

For an ‘ON’ transistor, VBE should be around 0.7V

For the transistor to be in active region, VCE is usually about 25% to 75% of VCC.

If VCE = almost VCC, probable faults:

– the device is damaged

io

– connection in the collector – emitter or base – emitter circuit loop is open.

One of the most common mistake in the lab is usage of wrong resistor value.

Check various voltages with respect to ground.

Calculate the current values using voltage readings rather than measuring current by

ut

breaking the circuit.

Problem – 1

ol

us

vt

Problem - 2

30

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Vtusolution.in

in

n.

PNP transistors

The analysis of PNP transistors follows the same pattern established for NPN transistors.

The only difference between the resulting equations for a network in which an npn

quantities.

transistor has been replaced by a pnp transistor is the sign associated with particular

ut

ol

us

vt

31

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Bias stabilization

in

The stability of a system is a measure of the sensitivity of a network to variations in

its parameters.

In any amplifier employing a transistor the collector current IC is sensitive to each of

n.

the following parameters.

increases with increase in temperature.

Magnitude of VBE decreases about 2.5mV per degree Celsius increase in temperature.

ICO doubles in value for every 10 degree Celsius increase in temperature.

T (degree

Celsius)

Ico (nA)

io VBE (V)

ut

- 65 0.2 x 10-3 20 0.85

25 0.1 50 0.65

ol

100 20 80 0.48

us

Stability factors

vt

S () = IC /

Networks that are quite stable and relatively insensitive to temperature variations

have low stability factors.

The higher the stability factor, the more sensitive is the network to variations in that

parameter.

32

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S( ICO)

– emitter bias configuration

– fixed bias configuration

– Voltage divider configuration

in

S( ICO) = ( + 1) [ 1 + RB / RE] / [( + 1) + RB / RE]

If RB / RE >> ( + 1) , then

n.

S( ICO) = ( + 1)

For RB / RE <<1, S( ICO) 1

Thus, emitter bias configuration is quite stable when the ratio RB / RE is as small as

possible.

io

Emitter bias configuration is least stable when RB / RE approaches ( + 1) .

ut

= ( + 1) [RE + RB] / [( + 1) RE + RB]

By plugging RE = 0, we get

S( ICO) = + 1

ol

us

Here, replace RB with Rth

S( ICO) = ( + 1) [ 1 + Rth / RE] / [( + 1) + Rth / RE]

vt

Thus, voltage divider bias configuration is quite stable when the ratio R th / RE is as small

as possible.

33

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Physical impact

In a fixed bias circuit, IC increases due to increase in IC0. [IC = IB + (+1) IC0]

IB is fixed by VCC and RB. Thus level of IC would continue to rise with temperature –

a very unstable situation.

reduces IB. IB = [VCC – VBE – VE] / RB. A drop in IB reduces IC.Thus, this

configuration is such that there is a reaction to an increase in IC that will tend to

in

oppose the change in bias conditions.

thus reducing IB and causing IC to reduce.

n.

The most stable configuration is the voltage – divider network. If the condition RE

>>10R2, the voltage VB will remain fairly constant for changing levels of IC. VBE =

VB – VE, as IC increases, VE increases, since VB is constant, VBE drops making IB to

fall, which will try to offset the increases level of IC.

S(VBE)

ut

For an emitter bias circuit, S(VBE) = - / [ RB + ( + 1)RE]

If RE =0 in the above equation, we get S(VBE) for a fixed bias circuit as,

S(VBE) = - / RB.

ol

For an emitter bias,

us

If ( + 1)>> RB/RE, then

S(VBE) = - (/RE )/ ( + 1)

= - 1/ RE

The larger the RE, lower the S(VBE) and more stable is the system.

vt

General conclusion:

design.

34

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Vtusolution.in

in

n.

io

ut

ol

us

vt

35

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Vtusolution.in

in

n.

io

ut

ol

us

vt

36

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General Amplifiers

in

Cascade connection - FET & BJT

Numerical

n.

Cascode connection

Darlington connection

ut

AC equivalent

AC voltage gain

ol

Feedback concept

us

Numerical

vt

Vtusolution.in

Vtusolution.in

in

n.

io

• Cascade connection is a series connection with the output of one stage then

ut

applied as input to the second stage.

larger overall gain.

ol

• Gain of overall cascade amplifier is the product of stage gains AV1 and AV2

us

Zi = RG1

vt

Z0=RD2

• The main function of cascading the stages is the larger overall gain achieved.

Vtusolution.in

Vtusolution.in

Numerical

in

n.

io

Calculate dc bias, voltage gain, input impedance, output impedance,Also

ut

calculate the load voltage if a 10K Ω load is connected across the output

ol

Data for numerical

• C1=C2=C3=0.05uF

us

• RG1=RG2=3.3 MΩ

• RS1=RS2=680 Ω

• RD1=RD2=2.4 KΩ

vt

Solution

Step 1: from the dc bias details we can find out VGSQ= -1.9V, IDQ=2.8mA

Vtusolution.in

Vtusolution.in

gm =5m(1-(-1.9)/(-4) = 2.6mS

in

Step 3: the voltage gain of each stage

n.

• Step 4: Overall gain of cascaded stage is

io

ut

• Step 5: output voltage is Vo=Av Vi =384 mV

ol

Zi=RG= 3.3 MΩ

us

Zo=RD= 2.4 KΩ

VL= [RL/(RL+Zo)] Vo

vt

=[10K/(10K+2.4)] 384mV=310mV

Vtusolution.in

Vtusolution.in

in

n.

io

ut

• RC coupled cascade amplifier is taken here for example

ol

us

vt

Zo=Rc װro

Vtusolution.in

Vtusolution.in

Numerical

in

n.

io

ut

Calculate voltage gain, output impedance, input impedance for cascaded BJT

amplifier of fig above. Calculate output voltage resulting if 10K ohms load is

connected to load.

ol

Given,

R1=15KΩ; R2=4.7KΩ;Rc=2.2KΩ;RE=1KΩ

us

• C1=C2=C3=10uF

vt

Solution:

• Dc analysis yields

Vtusolution.in

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• VB=4.7V;VE=4.0V;VC=11V; IE=4.0mA

in

= -665.2/6.5=-102.3

n.

• Overall gain of AV=AV1AV2

=-102.3 x -338.46

=34,624

io

ut

• Output voltage is : Vo=AV Vi=34624 x 25u

=0.866V

ol

• Amplifier input impedance is

us

=953.6 ohms.

• VL= {RL/Zo+RL} Vo

={10K/2.2K+10K}0.866 = 0.71 V

vt

Vtusolution.in

Vtusolution.in

Cascode connection

in

voltage gain to ensure that the input Miller capacitance is at a minimum with

the CB stage providing good high frequency operation.

n.

io

ut

ol

us

vt

Vtusolution.in

Vtusolution.in

in

n.

io

ut

ol

us

Numerical

Calculate the voltage gain for the cascode amplifier of fig above..

Solution:

vt

IC1=Ic2=3.8mA

Vtusolution.in

Vtusolution.in

=-265

in

• CE stage with a gain of -1 provides the higher input impedance of CE stage.

n.

• A large gain is then provided by the CB stage, resulting in large overall gain

of -265.

Darlington connection

io

Popular connection operates as “super beta” transistor is Darlington connection.

ut

ol

us

single unit with a current gains of individual transistors.

vt

typically a few thousands.

Vtusolution.in

Vtusolution.in

in

n.

DC bias of Darlington circuits

IB

Vcc VBE

RB D RE

io

ut

I E ( D 1) I B D I B

Voltages

ol

VE I E RE

VB VE VBE

us

vt

Vtusolution.in

Vtusolution.in

in

n.

io

ut

Numerical

Calculate dc bias voltages and currents for the Darlington connection. Given

ol

RB=3.3MΩ;RE=390 Ω;βd=8000;VCC=18V;VBE=1.6V

IB 2.56uA

us

RB D RE 3.3M 8000(390)

I E ( D 1) I B D I B 8000(2.56u ) 20.48mA

Voltages

vt

VE I E RE 20.48m(390) 8V

VB VE VBE 8 1.6 9.6V

VC 18V

Vtusolution.in

Vtusolution.in

AC equivalent circuit

in

n.

io

ut

Equivalent model

ol

us

vt

Vtusolution.in

Vtusolution.in

Input impedance

Ib=Vi-Vo/ri

• Since Vo=(Ib+βDIb)RE

in

• Substituting Ib in Vo expression,

Ibri=Vi-Vo=Vi-Ib(1+ βD)RE

n.

Vi=Ib[ri+(1+ βD)RE]=Ib(ri+ βDRE)

ut

ac output impedance of Darlington connection

ol

us

vt

Vtusolution.in

Vtusolution.in

Output impedance

measuring the current Io with Vs setting to zero.

in

Vo Vo V V V

Io DIB o o D o

RE ri RE ri ri

n.

1 1 D

I o Vo

E i

R r ri

Zo

Vo

1

io

I o 1 / RE 1 / ri D / ri

ut

Zo= RE װri װri/βD

ol

us

vt

Vtusolution.in

Vtusolution.in

ac voltage gain

in

n.

Gain expression

io

Vo ( I b D I b ) RE I b ( RE D RE )

Vi Ibri ( Ib D I b ) RE

ut

On simplification

Vi I b (ri RE D RE )

ol

Vi

Vo ( RE D RE )

ri ( RE D RE )

us

Vo RE DRE

Av 1

Vi ri ( RE DRE )

vt

Numerical

For the Darlington pair, given RE=390 ohms and β=8000. Calculate gain if

ri=5KΩ

390 8000 x390

Av 0.998

5 K [390 8000 x390]

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Feedback concepts

• Depending on the relative polarity of fed back signal in to the circuit, there

are two types of feedback

in

Negative feedback results in Reduced gain

n.

Feedback amplifier

io

ut

ol

us

vt

• Reduced noise

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in

• Current series feedback

Here voltage refers to small part of voltage as input to the feedback network

n.

Current refers to tapping some part of output current through feedback

network.

voltage.

io

Series refers to connecting feedback signal in series with the input signal

Shunt refers to connecting feedback signal in shunt with the input signal

ut

voltage

ol

us

vt

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in

n.

Voltage shunt feedback Af=Vo/Is io

ut

ol

us

vt

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in

n.

io

ut

Current shunt feedback Af=Io/Is

ol

us

vt

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• Feedback factor β

in

Voltage Voltage Current Current

Parameter

series shunt series shunt

n.

Gain with

A Vo/Vi Vo/Ii Io/Vi Io/Ii

feedback

Gain with

feedback

Af Vo/Vs io Vo/Is Io/Vs Io/Is

ut

Voltage series feedback

ol

• With zero feedback then Vf=0 the voltage gain of amplifier stage is

A=Vo/Vs=Vo/Vi

us

Vi=Vs-Vf

Vo=AVi=A(Vs-Vf)=AVs-AVf=A(Vs-A(βVo)

vt

Af=Vo/Vi=A/(1+A β)

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• Af=A/(1+ βA)

in

• Ref to fig(1)

n.

Vs=Ii Zi+ β A Vi = Ii Zi+ β A Ii Zi

ut

When Aβ» 1, then Af=A/(1+A β)≈1/ β

because of varying gain with frequency is considerably reduced.

ol

• Bandwidth variation

us

• Therefore, here we can see that, practical circuits, open loop gain drops at

high frequencies.

vt

Product of gain and Bandwidth remains same it’s a tradeoff between gain and BW

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Af 1 A

dA f 1 dA

dA A A

• This shows that magnitude of relative change in dAf/A is reduced by the

factor Aβ compared to that without feedback dA/A

Numerical

in

If a amplifier with gain of -1000 and feedback of β=-0.1 has a gain change of 20%

due to temperature, calculate the change in gain of the feedback amplifier.

n.

Solution:

dAf 1 dA 1

20%

Af A A

........ 0.2%

0.1(1000)

io

ut

Practical feedback circuits

ol

us

vt

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resistors R1 and R2.

• The feedback voltage Vf is connected in series with the source signal Vs.

their difference being the input signal Vi.

in

Where RL=parallel combination of RD,Ro,(R1+R2)

n.

• Using values of A and β in above equation, Af is

A g m RL

Af

1 A 1 R2 RL /( R1 R2 )g m

if .. A 1, then

1 R R2

io

ut

Af 1

R2

ol

Numerical:

Calculate the gain without and with feedback for the FET amplifier shown in fig.

circuit values are given to be R1=80KΩ,R2=20KΩ,RD=10KΩ and gm=4000uS

us

Solution :

RL=5K Ω

A=-20

vt

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in

n.

Numerical

io

ut

If open loop gain of op-amp is 100,000 and feedback resistors are R1=1.8K Ω and

R2=200 Ω then calculate the gain with feedback .

Solution

ol

• β=0.1

• Af=9.9999

us

vt

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in

n.

io

ut

• The output voltage Vo is also the feedback voltage in series with the input

ol

voltage.

us

Vo h fe I b RE h fe RE (Vs / hie ) h fe RE

A

Vi Vs Vs Vs

Vf

1

vt

Vo

• The operation with feedback then provides that,

Vo A h fe RE / hie

Af

Vs 1 A 1 (1)(h fe RE / hie )

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h fe RE

hie h fe RE

hfeRE 1,

Af 1

in

Current series feedback

n.

proportional voltage in series with the input.

increases the input resistance.

io

• In this circuit, emitter of this stage has an un bypassed emitter, it effectively

has current-series feedback.

ut

• The current through RE results in feedback voltage that opposes the source

signal applied so that the output voltage Vo is reduced.

ol

us

vt

removed or bypassed by a capacitor (as is done in most of the amplifiers)

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The fig below shows the equivalent circuit for current series feedback

in

n.

Gain, input and output impedance for this condition is,

Io A h fe / hie

Af

Vs 1 A

io

1 ( RE )

h fe

hie RE

ut

h fe RE

Z if Z i (1 A ) hie 1

h ie

ol

h fe RE

Z of Z o (1 A ) Rc 1

hie

with feedback .. A;

us

Vo I o Rc I o h fe RC

Avf

Rc A f RC

Vs Vs Vs hie h fe RE

vt

Numerical

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in

n.

Solution:

A

Io

hfe

120

Vi hie RE 900 510

io

0.085

ut

Vf

RE 510

Io

ol

1+(-0.085)(-510) =44.35

us

Af=Vo/vi=A/(1+A β)

=-.085/44.35 = -1.92x10e-3

vt

Avf=Vo/Vs=AfRC=(-1.92x10e-3)(2.2x10e3)=4.2

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Av=-RC/re=-2.2x10e3/7.5= -293.3

infinite. Hence Ii=0,vi=0 and voltage gain is infinity.

in

• Ie., A=Vo/Ii=infinity

n.

• This is transfer resistance gain.

io

ut

ol

us

2.Equivalent circuit

vt

Vo Is 1 R0

Avf ( Ro)

Is V 1 R1 R1

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in

n.

Equivalent circuit io

ut

ol

us

vt

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Vo A g m RD RS

Af

I s 1 A 1 (1 / RF )( g m RD RS )

in

voltage gain withfeedback ..is,

Vo I s g m RD RS RF 1

Avf

I s Vs RF g m RD RS

n.

RS

g m RD RF RF

( g m RD )

RF g m RD RS RF g m RD RS

Numerical io

ut

Calculate voltage gain with and without feedback for the circuit of FET f/b. With

the values, gm=5mS, RD=5.1KΩ, Rs=1KΩ, RF=20KΩ

Solution :

ol

• Av=-gmRD=-25.5

us

vt

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• Introduction

• Amplification in the AC domain

• BJT transistor modeling

in

• The re Transistor Model

• The Hybrid equivalent Model

Introduction

n.

• There are three models commonly used in the small – signal ac analysis of

transistor networks:

• The re model

• The hybrid model

• The hybrid equivalent model

io

ut

The transistor can be employed as an amplifying device, that is, the output ac power

is greater than the input ac power. The factor that permits an ac power output greater

than the input ac power is the applied DC power. The amplifier is initially biased for

the required DC voltages and currents. Then the ac to be amplified is given as input to

the amplifier. If the applied ac exceeds the limit set by dc level, clipping of the peak

ol

region will result in the output. Thus, proper (faithful) amplification design requires

that the dc and ac components be sensitive to each other’s requirements and

limitations. The superposition theorem is applicable for the analysis and design of the

dc and ac components of a BJT network, permitting the separation of the analysis of

the dc and ac responses of the system.

us

• The key to transistor small-signal analysis is the use of the equivalent circuits

(models). A MODEL IS A COMBINATION OF CIRCUIT ELEMENTS

LIKE VOLTAGE OR CURRENT SOURCES, RESISTORS, CAPACITORS

vt

etc, that best approximates the behavior of a device under specific operating

conditions. Once the model (ac equivalent circuit) is determined, the schematic

symbol for the device can be replaced by the equivalent circuit and the basic

methods of circuit analysis applied to determine the desired quantities of the

network.

• Hybrid equivalent network – employed initially. Drawback – It is defined for a set

of operating conditions that might not match the actual operating conditions.

• re model: desirable, but does not include feedback term

1

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AC equivalent of a network

• Setting all dc sources to zero and replacing them by a short – circuit equivalent

• Replacing all capacitors by short – circuit equivalent

in

• Removing all elements bypassed by the short – circuit equivalents

• Redrawing the network in a more convenient and logical form.

n.

io

ut

ol

us

re model

vt

• In re model, the transistor action has been replaced by a single diode between

emitter and base terminals and a controlled current source between base and

collector terminals.

• This is rather a simple equivalent circuit for a device

2

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For the hybrid equivalent model, the parameters are defined at an operating point.

The quantities hie, hre,hfe, and hoe are called hybrid parameters and are the

components of a small – signal equivalent circuit.

• The description of the hybrid equivalent model will begin with the general two

in

port system.

n.

io

ut

• The set of equations in which the four variables can be related are:

• Vi = h11Ii + h12Vo

• Io = h21Ii + h22Vo

• The four variables h11, h12, h21 and h22 are called hybrid parameters ( the mixture

ol

of variables in each equation results in a “ hybrid” set of units of measurement for

the h – parameters.

• Set Vo = 0, solving for h11, h11 = Vi / Ii Ohms

• This is the ratio of input voltage to the input current with the output terminals

shorted. It is called Short circuit input impedance parameter.

us

• If Ii is set equal to zero by opening the input leads, we get expression for h12:

h12 = Vi / Vo , This is called open circuit reverse voltage ratio.

• Again by setting Vo to zero by shorting the output terminals, we get

h21 = Io / Ii known as short circuit forward transfer current ratio.

• Again by setting I1 = 0 by opening the input leads, h22 = Io / Vo . This is known as

open – circuit output admittance. This is represented as resistor ( 1/h22)

vt

• h12 = hr = reverse transfer voltage ratio

• h21 = hf = forward transfer current ratio

• h22 = ho = Output conductance

3

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in

n.

•

io

ut

ol

Complete hybrid equivalent circuit

us

vt

4

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in

n.

• Essentially, the transistor model is a three terminal two – port system.

• The h – parameters, however, will change with each configuration.

•

•

io

To distinguish which parameter has been used or which is available, a second

subscript has been added to the h – parameter notation.

For the common – base configuration, the lowercase letter b is added, and for

common emitter and common collector configurations, the letters e and c are used

ut

respectively.

ol

us

vt

Configuration Ii Io Vi Vo

Common emitter Ib Ic Vbe Vce

Common base Ie Ic Veb Vcb

Common Collector Ib Ie Vbe Vec

5

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and hrVo = 0, resulting in a short – circuit equivalent.

• The resistance determined by 1/ho is often large enough to be ignored in

comparison to a parallel load, permitting its replacement by an open – circuit

equivalent.

in

n.

io

ut

ol

us

vt

hie = re

6

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hfe = ac

in

n.

Common-Base configurations - h-Parameters

io

hib= re

hfb= - = -1

ut

Problem

• Given IE = 3.2mA, hfe = 150, hoe = 25S and hob = 0.5 S . Determine

– The common – emitter hybrid equivalent

– The common – base re model

ol

us

vt

Solution:

• We know that, hie = re and re = 26mV/IE = 26mV/3.2mA = 8.125

• re = (150)(8.125) = 1218.75k

• ro = 1 /hoe = 1/25S = 40k

7

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in

• re = 8.125

• ro = 1/ hob = 1/0.5S = 2M

• 1

n.

• Small signal ac analysis includes determining the expressions for the following

parameters in terms of Zi, Zo and AV in terms of

–

– re

•

•

– ro and

– RB, RC

io

Also, finding the phase relation between input and output

The values of , ro are found in datasheet

ut

• The value of re must be determined in dc condition as re = 26mV / IE

ol

us

•

Removing DC effects of VCC and Capacitors

vt

8

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re model

in

Small signal analysis – fixed bias

n.

• From the above re model,

Zi = [RB re] ohms

Then, Zi re

io

[RB re] re

Zo is the output impedance when Vi =0. When Vi =0, ib =0, resulting in open circuit

ut

equivalence for the current source.

ol

us

• Zo = [RC ro ] ohms

vt

• AV

– Vo = - Ib( RC ro)

• thus,

– Vo = - (Vi / re) ( RC ro)

– AV = Vo / Vi = - ( RC ro) / re

9

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• If ro >10RC,

– AV = - ( RC / re)

• The negative sign in the gain expression indicates that there exists 180o phase

shift between the input and output.

in

n.

io

ut

ol

us

• The re model is very similar to the fixed bias circuit except for RB is R1 R2 in the

case of voltage divider bias.

• Expression for AV remains the same.

vt

Zi = R1 R2 re

Zo = RC

• From the re model, Ib = Vi / re

• thus,

Vo = - (Vi / re) ( RC ro)

• AV = Vo / Vi = - ( RC ro) / re

10

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o If ro >10RC,

AV = - ( RC / re)

in

n.

•

io

ut

ol

us

Vi = Ib re + IeRE

Vi = Ib re +( +1) IbRE

vt

Zb = Vi / Ib = re+ ( +1)RE

11

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Thus,

Zb = Vi / Ib = (re+RE)

Zb = RE,

•

Zi = RB||Zb

in

• Zo is determined by setting Vi to zero, Ib = 0 and Ib can be replaced by open

circuit equivalent. The result is,

• Zo = RC

n.

• AV : We know that, Vo = - IoRC

= - IbRC

= - (Vi/Zb)RC

AV = Vo / Vi = - (RC/Zb)

Substituting,

RE >>re,

Zb = (re + RE)

io

AV = Vo / Vi = - [RC /(re + RE)]

AV = Vo / Vi = - [RC /RE]

ut

• Phase relation: The negative sign in the gain equation reveals a 180 o phase shift

between input and output.

ol

us

vt

12

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Emitter – follower

in

n.

re model

io

ut

ol

us

• Zi = RB || Zb

• Zb = re+ ( +1)RE

• Zb = (re+ RE)

• Since RE is often much greater than re, Zb = RE

vt

• To find Zo, it is required to find output equivalent circuit of the emitter follower

at its input terminal.

• This can be done by writing the equation for the current Ib.

Ib = Vi / Zb

Ie = ( +1)Ib

= ( +1) (Vi / Zb)

• We know that, Zb = re+ ( +1)RE substituting this in the equation for Ie we get,

13

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= ( +1) (Vi / re+ ( +1)RE )

Ie = Vi / [re/ ( +1)] + RE

• Since ( +1) = ,

Ie = Vi / [re+ RE]

• Using the equation Ie = Vi / [re+ RE] , we can write the output equivalent circuit as,

in

n.

•

•

io

ut

Zo = RE||re

• Since RE is typically much greater than re, Zo re

• AV – Voltage gain:

ol

• Using voltage divider rule for the equivalent circuit,

Vo = Vi RE / (RE+ re)

AV = Vo / Vi = [RE / (RE+ re)]

us

AV [RE / (RE] 1

•

• Phase relationship

vt

14

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in

n.

re model

io

ut

Small signal analysis

ol

• Input Impedance: Zi = RE||re

• Output Impedance: Zo = RC

• To find, Output voltage,

us

Vo = - IoRC

Vo = - (-IC)RC = IeRC

o Ie = Vi / re, substituting this in the above equation,

Vo = (Vi / re) RC

vt

Vo = (Vi / re) RC

15

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AV = Vo / Vi = (RC/ re)

1; AV = (RC/ re)

Current gain

Ai = Io / Ii

Io = - Ie = - Ii

in

Io / Ii = - -1

Phase relation: Output and input are in phase.

n.

h-Parameter Model vs. re Model

io

ut

ol

us

vt

Common-Base h-Parameters

h ib re

h fb 1

16

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• Small signal ac analysis includes determining the expressions for the following

parameters in terms of Zi, Zo and AV in terms of

–

– re

– ro and

– RB, RC

in

• Also, finding the phase relation between input and output

• The values of , ro are found in datasheet

• The value of re must be determined in dc condition as re = 26mV / IE

n.

Common Emitter Fixed bias configuration

io

ut

ol

•

us

vt

17

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re model

in

n.

Small signal analysis – fixed bias

io

Zi = [RB re] ohms

ut

[RB re] re

Then, Zi re

ol

Ouput impedance Zoi:

equivalence for the current source.

us

vt

Zo = [RC ro ] ohms

18

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Vo = - Ib( RC ro)

From the re model, Ib = Vi / re

thus, Vo = - (Vi / re) ( RC ro)

AV = Vo / Vi = - ( RC ro) / re

in

If ro >10RC, AV = - ( RC / re)

n.

Phase Shift:

The negative sign in the gain expression indicates that there exists 180o phase shift

between the input and output.

io

ut

ol

Problem:

Common Emitter - Voltage-Divider Configuration

us

vt

19

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Equivalent Circuit:

in

The re model is very similar to the fixed bias circuit except for RB is R1 R 2 in the case

of voltage divider bias.

n.

Expression for AV remains the same.

Zi = R1 R2 re

:

Zo = RC

io

ut

From the re model,

Ib = Vi / re

Vo = - Io ( RC ro),

Io = Ib

ol

AV = Vo / Vi = - ( RC ro) / re

us

If ro >10RC, AV = - ( RC / re)

vt

20

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Problem:

Given: = 210, ro = 50k.

Determine: re, Zi, Zo, AV. For the network given:

in

n.

io

To perform DC analysis, we need to find out whether to choose exact analysis or

approximate analysis.

ut

This is done by checking whether RE > 10R2, if so, approximate analysis can be chosen.

Here, RE = (210)(0.68k) = 142.8k.

10R2 = (10)(10k) = 100k.

RE > 10R2.

ol

Thus,

Therefore using approximate analysis,

VB = VccR2 / (R1+R2)

us

VE = VB – 0.7 = 1.6 – 0.7 = 0.9V

IE = VE / RE = 1.324mA

re = 26mV / 1.324mA = 19.64

Effect of ro can be neglected if ro 10( RC). In the given circuit, 10RC is 22k, ro is 50K.

vt

Zi = ( R1||R2||RE)

= [90k||10k||(210)(0.68k)] = 8.47k

Zo = RC = 2.2 k

21

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AV = - RC / RE = - 3.24

If the same circuit is with emitter resistor bypassed,

Then value of re remains same.

Zi = ( R1||R2||re) = 2.83 k

Zo = RC = 2.2 k

AV = - RC / re = - 112.02

in

Common Emitter Un bypassed Emitter - Fixed Bias Configuration

n.

io

ut

Equivalent Circuit:

ol

us

vt

Vi = Ibre + IeRE

Vi = Ibre +( +1) IbRE

22

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Zb = Vi / Ib = re+ ( +1)RE

Since >>1, ( +1) =

Thus, Zb = Vi / Ib = (re+RE)

Since RE is often much greater than re,

Zb = RE,

in

Zi = RB||Zb

Zo is determined by setting Vi to zero, Ib = 0 and Ib can be replaced by open circuit

equivalent.

n.

The result is, Zo = RC

We know that, Vo = - IoRC

= - IbRC

Substituting

AV = Vo / Vi = - (RC/Zb)

Zb = (re + RE)

io

= - (Vi/Zb)RC

ut

AV = Vo / Vi = - [RC /(re + RE)]

RE >>re, AV = Vo / Vi = - [RC /RE]

Phase relation: The negative sign in the gain equation reveals a 180 o phase shift between

ol

input and output.

us

vt

23

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Problem:

in

n.

Given: = 120, ro = 40k.

Determine: re, Zi, Zo, AV.

To find re, it is required to perform DC analysis and find IE as re = 26mV / IE

To find IE, it is required to find IB.

We know that,

io

IB = (VCC – VBE) / [RB + (+1)RE]

IB = (20 – 0.7) / [470k + (120+1)0.56k] = 35.89A

ut

IE = (+1)IB = 4.34mA

re = 26mV / IE = 5.99

Effect of ro can be neglected, if ro 10( RC + RE)

ol

10( RC + RE) = 10( 2.2 k + 0.56k)

= 27.6 k

and given that ro is 40 k, thus effect of ro can be ignored.

us

Z i = RB|| [ ( re + RE)]

= 470k || [120 ( 5.99 + 560 )] = 59.34

Zo = RC = 2.2 k

AV = - RC / [ ( re + RE)]

vt

= - 3.89

Analyzing the above circuit with Emitter resistor bypassed i.e., Common Emitter

IB = (VCC – VBE) / [RB + (+1)RE]

IB = (20 – 0.7) / [470k + (120+1)0.56k]

= 35.89A

24

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IE = (+1)IB = 4.34mA

re = 26mV / IE = 5.99

Zi = RB|| [re] = 717.70

Zo = RC = 2.2 k

AV = - RC / re = - 367.28 ( a significant increase)

in

Emitter – follower

n.

io

ut

re model

ol

us

vt

Zi = RB || Zb

Zb = re+ ( +1)RE

Zb = (re+ RE)

Since RE is often much greater than re, Zb = RE

25

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To find Zo, it is required to find output equivalent circuit of the emitter follower at its

input terminal.

This can be done by writing the equation for the current Ib.

Ib = Vi / Zb

Ie = ( +1)Ib

= ( +1) (Vi / Zb)

in

We know that,

Zb = re+ ( +1)RE

substituting this in the equation for Ie we get,

n.

Ie = ( +1) (Vi / Zb)

= ( +1) (Vi / re+ ( +1)RE )

dividing by ( +1), we get,

Since ( +1) = ,

io

Ie = Vi / [re/ ( +1)] + RE

Ie = Vi / [re+ RE]

ut

Using the equation Ie = Vi / [re+ RE], we can write the output equivalent circuit as,

ol

us

Zo = RE||re

vt

Zo re

26

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AV – Voltage gain:

Using voltage divider rule for the equivalent circuit,

Vo = Vi RE / (RE+ re)

AV = Vo / Vi = [RE / (RE+ re)]

Since (RE+ re) RE,

AV [RE / (RE] 1

in

Phase relationship

As seen in the gain equation, output and input are in phase.

n.

Vo

io

ut

Common base configuration

ol

us

vt

27

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re model

in

Small signal analysis

n.

Zi = RE||re

Zo = RC

To find

Vo = - IoRC

Vo = - (-IC)RC = IeRC

io

Substituting this in the above equation, Ie = Vi / re,

ut

Vo = (Vi / re) RC

Vo = (Vi / re) RC

AV = Vo / Vi = (RC/ re)

ol

1; AV = (RC/ re)

Current gain Ai :

Ai = Io / Ii

us

Io = - Ie = - Ii

Io / Ii = - -1

Phase relation: Output and input are in phase.

vt

28

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in

n.

re Model

io

ut

ol

Input Impedance: Zi

Zi = Vi / Ii,

Ii = Ib – I,

us

I = (Vo – Vi)/ RF (1)

Vo = - IoRC

Io = Ib + I

vt

thus, Io = Ib ,

Vo = - IoRC

Vo = - Ib RC,

29

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Replacing Ib by Vi / re

Thus,

Vo = - (Vi RC) / re

= - (Vi RC) / re (2)

Substituting (2) in (1):

I = (Vo – Vi)/ RF

in

= (Vo / RF) - (Vi/ RF)

= - [(Vi RC) / RF re] - (Vi/ RF)

I = - Vi/RF[ (RC / re )+1]

n.

We know that, Vi = Ibre,

Ib = Ii + I

and, I = - Vi/RF[ (RC / re ) +1]

Thus,

io

Vi = ( Ii + I ) re = Ii re + I re

= Ii re - (Vi re)( 1/RF)[ (RC / re )+1]

ut

Vi + (Vi re)( 1/RF)[ (RC / re )+1] = Ii re

Vi[1 + (re)( 1/RF)[ (RC / re ) +1] = Ii re

Vi / Ii = re / [1 + (re)( 1/RF)[ (RC / re ) +1]

ol

But, [ (RC / re )+1] RC / re

(because RC >> re)

Thus, Zi = Vi / Ii

us

= re / [1 + ()(RC/RF)]

Thus, Zi = re / [(1/) + (RC/RF)]

vt

30

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Vtusolution.in

in

Zo = RC || RF ( Note that ib = 0, thus no effect of re on Zo)

n.

Voltage Gain AV:

Vo = - IoRC

= - (Vi/ re)RC

AV = Vo / Vi = - (RC/re) io

= - IbRC ( neglecting the value of I )

ut

Phase relation: - sign in AV indicates phase shift of 180 between input and output.

ol

us

vt

31

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re model

in

Zi = RF1 ||re

Zo = RC||RF2||ro,

for ro10RC, Zo = RC||RF2

n.

To find Voltage Gain AV :

Vo = - Ib(RF2||RC||ro), Ib = Vi / re

Vo = - (Vi / re)(RF2||RC||ro)

for ro10RC,

io

Vo / Vi = - (RF2||RC||ro) / re,

AV = Vo / Vi = - (RF2||RC) / re

ut

Determining the current gain

For each transistor configuration, the current gain can be determined directly from the

ol

voltage gain, the defined load, and the input impedance.

Io = (Vo / RL) and Ii = Vi / Zi

us

= - (Vo Zi / Vi RL)

Ai = - AV Zi / RL

Example:

vt

AV = - RC / re and RL = RC

Thus, Ai = - AV Zi / RL

= - (- RC / re )(re) / RC

Ai =

32

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Ai = - AV Zi / RL

= - (RC / re )(re) / RC

=-1

Effect of RL and RS:

Voltage gain of an amplifier without considering load resistance (RL) and source

in

resistance (RS) is AVNL.

Voltage gain considering load resistance ( RL) is AV < AVNL

Voltage gain considering RL and RS is AVS, where AVS<AVNL< AV

For a particular design, the larger the level of RL, the greater is the level of ac gain.

Also, for a particular amplifier, the smaller the internal resistance of the signal source, the

n.

greater is the overall gain.

io

ut

ol

us

AV = - (RC||RL) / re

Z i = RB|| re

Zo = RC||ro

To find the gain AVS, ( Zi and RS are in series and applying voltage divider rule)

vt

Vi = VSZi / ( Zi+RS)

Vi / VS = Zi / ( Zi+RS)

AVS = Vo / VS = (Vo/Vi) (Vi/VS)

AVS = AV [Zi / ( Zi+RS)]

33

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in

Voltage gain: AV = - [RC||RL] / re

n.

Input Impedance: Zi = R1||R2|| re

Output Impedance: Zo = RC||RL||ro

io

ut

ol

us

re model:

vt

34

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Input Impedance: Zi = RB || Zb

Input Impedance seen at Base: Zb = (RE||RL)

Output Impedance Zo = re

in

This is an alternative approach to the analysis of an amplifier.

This is important where the designer works with packaged with packaged products

rather than individual elements.

An amplifier may be housed in a package along with the values of gain, input and

n.

output impedances.

But those values are no load values and by using these values, it is required to find

out the gain and various impedances under loaded conditions.

This analysis assumes the output port of the amplifier to be seen as a voltage source.

The value of this output voltage is obtained by Thevinising the output port of the

amplifier.

Eth = AVNLVi

io

ut

ol

us

vt

Vo = AVNLViRL / [ RL+Ro]

35

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in

Applying voltage divider at the input side, we get:

n.

Vi = VSRi /[RS+Ri]

Vo = AVNLVi

Vi = VSRi /[RS+Ri]

io

Vo = AVNL VSRi /[RS+Ri]

Vo/ VS = AVS = AVNLRi /[RS+Ri]

ut

Two port system with RS and RL

ol

us

Vi = VSRi /[RS+Ri]

Vi / VS = Ri /[RS+Ri]

At the output side,

vt

Vo = AVNLViRL / [ RL+Ro]

Vo / Vi = AVNLRL / [ RL+Ro]

Thus, considering both RS and RL:

AV = Vo / Vs

= [Vo / Vi] [Vi / Vs]

36

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Example:

Given an amplifier with the following details:

RS = 0.2 k, AVNL = - 480, Zi = 4 k, Zo = 2 k

Determine:

in

AV with RL =1.2k

AV and Ai with RL= 5.6 k, AVS with RL = 1.2

Solution:

n.

AV = AVNLRL / (RL + Ro)

= (- 480)1.2k / (1.2k+2k)

= - 180

With RL = 5.6k, AV = - 353.76

io

This shows that, larger the value of load resistor, the better is the gain.

AVS = [Ri /(Ri+RS)] [ RL / (RL+Ro)] AVNL

ut

= - 171.36

Ai = - AVZi/RL, here AV is the voltage gain when RL = 5.6k.

Ai = - AVZi/RL

ol

= - (-353.76)(4k/5.6k) = 252.6

Hybrid model

us

vt

This is more accurate model for high frequency effects. The capacitors that appear are

stray parasitic capacitors between the various junctions of the device. These capacitances

come into picture only at high frequencies.

• rbb includes the base contact, base bulk and base spreading resistances.

37

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• rbe ( r), rbc, rce are the resistances between the indicated terminals.

• rbe ( r) is simply re introduced for the CE re model.

• rbc is a large resistance that provides feedback between the output and the input.

• r = re

• gm = 1/re

• ro = 1/hoe

in

• hre = r / (r + rbc)

n.

io

ut

ol

us

vt

38

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in

n.

io

ut

ol

us

vt

39

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in

FET small signal Analysis

n.

• FET introduction and working principles

• FET small signal analysis

• FET self bias technique.

• Examples

io

ut

• JFET self bias configuration

• Numerical

ol

• JFET common drain configuration

us

• Source follower.

• Numerical

vt

• Depletion mode

• Enhancement mode

• E MOSFET drain feedback configuration.

• E MOSFET voltage divider Configuration.

• numerical

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FET Introduction

• The Field-Effect Transistor (FET) is a type of transistor that

works by modulating a microscopic electric field inside a

semiconductor material.

• There are two general type of FET's, the MOSFET and JFET.

in

Symbol and representation

n.

io

ut

ol

us

vt

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• The JFET operation is compared with the water spigot.

The source of water pressure

• accumulated electrons at the negative pole of the applied voltage

in

from Drain to Source

The drain of water

n.

• electron deficiency (or holes) at the positive pole of the applied

voltage from Drain to Source.

The control of flow of water

•

io

Gate voltage that controls the width of the n-channel, which in

turn controls the flow of electrons in the n-channel from source to

drain.

ut

ol

us

vt

B. VGS < 0, VDS at some positive value

C. Voltage-Controlled Resistor

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in

n.

to a more positive voltage:

io

Three things happen when VGS = 0 and VDS is increased from 0

ut

electrons from n-channel combine with holes from p-gate.

• Increasing the depletion region, decreases the size of the n-channel

ol

which increases the resistance of the n-channel.

• But even though the n-channel resistance is increasing, the current

(ID) from Source to Drain

us

increasing.

vt

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Pinch off

in

n.

io

ut

Saturation

ol

us

vt

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• any further increase in VGS does not produce any increase in ID.

VGS at

pinch-off is denoted as Vp.

in

• ID is at saturation or maximum. It is referred to as IDSS.

• The ohmic value of the channel is at maximum.

n.

B. VGS < 0, VDS at some positive value

io

ut

ol

us

vt

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in

n.

As VGS becomes more negative:

io

• the JFET will pinch-off at a lower voltage (Vp).

• ID decreases (ID < IDSS) even though VDS is increased.

ut

• Eventually ID will reach 0A. VGS at this point is called Vp or

VGS(off).

ol

Also note that at high levels of VDS the JFET reaches a breakdown

situation. ID will increases uncontrollably if VDS > VDSmax

us

C. Voltage-Controlled Resistor

The region to the left of the pinch-off point is called the ohmic

region.

vt

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in

n.

Transfer Characteristics

io

• The transfer characteristic of input-to-output is not as straight

forward in a JFET

ut

as it was in a BJT.

• In a BJT, β indicated the relationship between IB (input) and IC

(output).

ol

little more complicated:

us

Current relation

vt

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BJT FET

1.BJT controls large output(Ic) by 1.FET controls drain current

means of a relatively small base by means of small gate

current. It is a current controlled voltage. It is a voltage

device. controlled device

in

2.Has amplification factor β 2.Has trans-conductance gm.

3.Has high voltage gain 3.Does not have as high as

n.

BJT

4.Less input impedance 4.Very high input impedance

io

ut

• FET Small-Signal Model

• Trans-conductance

The relationship of VGS (input) to ID(output)is called trans-

ol

conductance.

• The trans-conductance is denoted gm.

us

vt

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in

n.

Example:

io

Determine the magnitude of gm for a JFET with IDSS = 8mA and VP = -

4V at the following dc bias points.

ut

a. At VGS = -0.5V

b. At VGS = -1.5V

c. At VGS = -2.5V

ol

us

vt

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Mathematical Definition of gm

in

n.

io

ut

ol

us

FET Impedance

• Input Impedance Zi : ∞ ohms

• Output Impedance Zo: rd= 1/yos

vt

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in

n.

FET AC Equivalent Circuit

io

ut

ol

us

Phase Relationship

• The phase relationship between input and output depends on the

vt

• Common – Source ~ 180 degrees

• Common - Gate ~ 0 degrees

• Common – Drain ~ 0 degrees

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in

n.

• The input is on the gate and the output is on the drain.

io

• Fixed bias configuration includes the coupling capacitors c1 and c2

that isolate the dc biasing arrangements from the applied signal and

ut

load.

• They act as short circuit equivalents for the ac analysis.

ol

AC Equivalent Circuit

us

vt

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Voltage gain

in

n.

io

ut

Phase difference

ol

Negative sign in the gain expression indicates that the output voltage is

1800 phase shifted to that of input.

us

Example

For fixed bias circuit, the following bias data are given. VGS=-2V,

IDO=5.625mA and Vp=-8V. The input voltage vi. The value of yOs=40μS.

vt

1. Determine Gm

2. Find rd

3. Determine Zi

4. Calculate ZO, AV with and without effects of rd.

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• Main disadvantage of fixed bias configuration requires two dc

voltage sources.

• Self bias circuit requires only one DC supply to establish the

desired operating point.

in

Self bias configuration

n.

io

ut

ol

us

vt

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AC Equivalent Circuit

in

n.

io

ut

ol

• The capacitor across the source resistance assumes its short circuit

equivalent for dc allowing RS to define the operating point.

• Under ac conditions the capacitors assumes short circuit state and

us

• If RS is left un-shorted, then ac gain will be reduced.

vt

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in

n.

Circuit parameters:

io

• Since the resulting circuit is same as that of fixed bias

configuration, all the parameter expression remains same as

evaluated for fixed bias configuration.

ut

• Input impedance Zi=RG

• Output Impedance:ZO= rd parallel RD

ol

us

device by providing degenerative current feedback. However, this

method for minimizing gain variations is only effective when a

vt

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in

n.

io

ut

ol

• Here Rs is part of the equivalent circuit .

• There is no way to reduce the network with lowest complexity.

us

all polarities properly

Input Impedance

vt

the input impedance remains as follows:

Zi=RG

Output impedance

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ZO= Vo/Io at vi=0

Setting Vi=0 results in following circuit.

RD

in

Zo

RD Rs

1 gmRs

rd

n.

rd 10( RD Rs )

RD

Zo

io 1 gmRs

ut

ol

Voltage gain:

Vo

Av gmRD

Vi 1 gmRs RDrd Rs

us

gmRD

rd 10( RD Rs ), Av

1 gmRs

vt

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VGSo=-2.6V, IDq=2.6mA with IDSS=8mA and Vp=-6V.

Yos=20uS

Determine

a. Gm

in

b. Rd

c. Zi

n.

d. Zo with and without rd effect.

e. Av with and without rd effect

io

ut

ol

us

vt

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in

n.

AC equivalent circuit

io

ut

ol

us

vt

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Voltage gain:

in

n.

io

ut

Note

• Equations for ZO and Av are same as in fixed bias.

ol

• Only Zi is now dependent on parallel combination of R1 and R2.

JFET source follower

us

vt

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the output is from the source.

AC equivalent circuit

in

n.

io

ut

ol

us

• Input impedance : Zi=RG

vt

• Output impedance :

setting Vi=0V will result in the gate terminal being connected

directly to ground as shown in figure below.

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Equivalent circuit

in

n.

• Applying KCL at output node

io

ut

Vo Vo

rd Rs

ol

1 1

result : Io Vo rd gmVgs

Rs

us

1 1

Vo gmVgs

rd Rs

vt

1 1

Vo gm[Vo]

rd Rs

1 1

Vo gm

rd Rs

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Vo Vo 1

Zo

Io 1 1 V0

rd Rs g m

1

in

1 1

rd Rs g m

n.

rd, Rs and gm are all in parallel.

io

ut

Voltage gain

ol

us

vt

be equal to or greater than one. (as in the case of emitter follower of

BJT)

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Example:

A dc analysis of the source follower has resulted in VGS=-2.86V and

Io=4.56mA.

Determine

in

a. gm

b. Zi

n.

c. rd

d. Calculate Zo with and without effect of rd.

e. Calculate Av with and without effect of rd.

Compare the results.

io

Given IDSS=16mA, Vp=-4V, yos=25μS.

ut

The coupling capacitors used are 0.05μF.

JFET common gate configuration

ol

us

vt

Same as the common base in BJT

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AC equivalent circuit

in

n.

io

ut

ol

Impedances:

us

vt

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Voltage gain

in

n.

io

ut

ol

us

vt

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Determine gm,rd, Zi with and without the effect of rd, Av with and

without the effect of rd.

Also find Vo with and without rd. compare the results.

in

C1 and c2 are given by 10uf.

n.

io

ut

ol

us

vt

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MOSFETs:

MOSFETs are of two types;

Depletion type

Enhancement type

in

1. Depletion type MOSFETs

n.

io

ut

ol

us

MOSFETs.

vt

• The ac equivalent model for this MOS device is same as JFET.

• Only difference is VGSo is positive for n-channel device and

negative for p-channel device.

• As a result of this, gm can be greater than gmo.

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D-MOSFET ac equivalent model

in

n.

io

ut

Example:A network shown below has the dc analysis results as

IDSS=6mA, VP=3V,VGSo=1.5V and IDQ=7.6mA.yos=10uS

a.Determine gm and compare with gmo

ol

b.Find rd

c.Sketch ac equivalent circuit

us

vt

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in

n.

Solution:

• gmo=4mS

io

ut

• gm=6mS

• gm is 50% more than gmo

ol

• rd= 100K Ω

• Zi=10M Ω parallel with 110M Ω =9.17MΩ

us

• Av=-gmrd= 10.8

Ac equivalent circuits

vt

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in

n.

Enhancement type MOSFET

io

• There are two types of E-MOSFETs:

nMOS or n-channel MOSFETs

ut

pMOS or p-channel MOSFETs

E-MOSFET ac small signal model

ol

us

vt

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• ID=k(VGS-VGS(Th))2

• gm is defined by

• Taking the derivative and solving for gm,

in

gm=2k(VGS-VGS(th))

n.

EMOSFET drain feedback configuration

io

ut

ol

us

vt

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Ac equivalent model

in

n.

io

ut

ol

us

vt

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in

n.

Voltage gain

io

ut

ol

us

vt

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Numerical

For the above said configuration, the following results were got.

K=0.24X10-3A/V2, VgsQ=6.4V, IDQ=2.75mA. Determine gm, rd, Zi with

and without the effect of rd, Zo with and without the effect of rd. Av

with and without effect of rd. And compare the results. Id(sat)=6mA,

in

VGS(th)=3V, VGS(on)=6V,yos=20uS.

n.

io

ut

ol

• RD=2K ohms

us

• RF=10M ohms

• C1,c2=1uF

Solution.

vt

• gm=2k(VGS-VGS(th))

=1.63mS.

• rd=1/yos=50KΩ

• Zi with rd: Rf (rd // RD )

Zi

1 gm(rd // RD )

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= 2.42MΩ

• Zi without effect of rd: Zi

RF

1 gmRD

= 2.53MΩ

in

• Zo with rd: (RF parallel rd parallel RD)

= 1.92KΩ

n.

• Zo without rd: Zo=RD = 2KΩ

• Gain AV with rd:

io

ut

• = -3.21

• Without effect of rd:

ol

us

• = -3.26

vt

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in

n.

io

ut

Important Parameters

ol

us

vt

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Ac equivalent circuit

in

n.

io

ut

ol

us

vt

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• To understand

– Decibels, log scale, general frequency considerations of an amplifier.

– low frequency analysis - Bode plot

– low frequency response – BJT amplifier

– Miller effect capacitance

– high frequency response – BJT amplifier

in

Introduction

elements of the network at low frequencies and the smaller capacitive elements of the

n.

active device at high frequencies. Since the analysis will extend through a wide frequency

range, the logarithmic scale will be used.

Logarithms

To say that

io

logaM = x means exactly the same thing as saying ax = M .

ut

Since 8 is 23 the answer is "3."

So log28 = 3

Basic Rules

ol

Logarithmic Rule 1:

us

Logarithmic Rule 2:

vt

Logarithmic Rule 3:

1

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• There is another logarithm that is also useful (and in fact more common in natural

processes). Many natural phenomenon are seen to exhibit changes that are either

exponentially decaying (radioactive decay for instance) or exponentially

increasing (population growth for example).

• These exponentially changing functions are written as ea, where ‘a’ represents the

in

rate of the exponential change.

• In such cases where exponential changes are involved, we usually use another

kind of logarithm called natural logarithm. The natural log can be thought of as

Logarithm Base-e.

n.

• This logarithm is labeled with ln (for "natural log"), where, e = 2.178.

io

ut

ol

us

Decibels

• The term decibel has its origin in the fact that the power and audio levels are related

on a logarithmic basis. The term bel is derived from the surname of Alexander

vt

Graham Bell.

• Bel is defined by the following equation relating two power levels, P1 and P2:

G = [log10 P2 / P1] bel

• It was found that, the Bel was too large a unit of measurement for the practical

purposes, so the decibel (dB) is defined such that 10 decibels = 1 bel.

• Therefore,

GdB = [10 log10 P2 / P1 ] dB

2

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The decimal rating is a measure of the difference in magnitude between two power

levels.

For a specified output power P2, there must be a reference power level P1. The

reference level is generally accepted to be 1mW.

in

= [10 log10 (V22 / Ri ) / (V12 / Ri )] dB

= 10 log10 (V2 / V1)2

GdB = [20 log10 V2 / V1 ] dB

n.

One of the advantages of the logarithmic relationship is the manner in which it can be

applied to cascaded stages wherein the overall voltage gain of a cascaded system is the

sum of individual gains in dB.

AV = (Av1)(Av2)(Av3)…….

Problem1:

io

AVdB = (Av1dB)+(Av2dB)+(Av3dB)…….

ut

GdB = [20 log10 V2 / V1 ] dB = 100dB

= 20 log10 V2 / V1 ;

V2 / V1 = 105 = 100,000

ol

Problem 2:

The input power to a device is 10,000W at a voltage of 1000V. The output power is

500W and the output impedance is 20.

Find the power gain in decibels.

us

= 10 log10 (500/10k)

= -13.01dB

vt

GV = 20 log10 (Vo/Vi)

= 20 log10 (PR/1000)

= 20 log10 [(500)(20)/1000]

= - 20dB

3

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Problem 3 :

An amplifier rated at 40 W output is connected to a 10 speaker.

a. Calculate the input power required for full power output if the power gain is 25dB.

b. Calculate the input voltage for rated output if the amplifier voltage gain is 40dB.

a. 25 = 10 log10 40/Pi

Pi = 40 / antilog(2.5) = 126.5mW

in

b. GV = 20log10Vo/Vi ;

40 = 20log10Vo/Vi

n.

Vo /Vi = antilog 2 = 100

Also, Vo = PR = (40)(10) = 20V

Thus, Vi = Vo / 100 = 20/100 = 200mV

•

io

At low frequencies the coupling and bypass capacitors can no longer be replaced

by the short – circuit approximation because of the increase in reactance of these

ut

elements.

• The frequency – dependent parameters of the small signal equivalent circuits and

the stray capacitive elements associated with the active device and the network

will limit the high frequency response of the system.

• An increase in the number of stages of a cascaded system will also limit both the

ol

high and low frequency response.

• The horizontal scale of frequency response curve is a logarithmic scale to permit a

plot extending from the low to the high frequency

us

vt

• For the RC coupled amplifier, the drop at low frequencies is due to the increasing

reactance of CC and CE, whereas its upper frequency limit is determined by either

the parasitic capacitive elements of the network or the frequency dependence of

the gain of the active device.

• In the frequency response, there is a band of frequencies in which the magnitude

of the gain is either equal or relatively close to the midband value.

• To fix the frequency boundaries of relatively high gain, 0.707AVmid is chosen to

be the gain at the cutoff levels.

4

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• The corresponding frequencies f1 and f2 are generally called corner, cutoff, band,

break, or half – power frequencies.

• The multiplier 0.707 is chosen because at this level the output power is half the

midband power output, that is, at mid frequencies,

•

PO mid = | Vo2| / Ro = | AVmidVi|2 / RO

in

POHPF = | 0.707 AVmidVi|2 / Ro

= 0.5| AVmid Vi|2 / Ro

• And, POHPF = 0.5 POmid

n.

• The bandwidth of each system is determined by f2 – f1

• A decibel plot can be obtained by applying the equation,

io

= 20 log10 (AV / AVmid)

ut

ol

Most amplifiers introduce a 180 phase shift between input and output signals. At low

frequencies, there is a phase shift such that Vo lags Vi by an increased angle. At high

frequencies, the phase shift drops below 180.

us

In the low frequency region of the single – stage BJT amplifier, it is the RC combinations

formed by the network capacitors CC and CE, the network resistive parameters that

determine the cutoff frequencies.

vt

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in

XC = 1/2fC 0

At f = 0 Hz, XC = , Vo = 0V.

n.

•

As frequency increases, the capacitive reactance decreases and more of the input

voltage appears across the output terminals.

io

The output and input voltages are related by the voltage – divider rule:

Vo = RVi / ( R – jXC)

ut

the magnitude of Vo = RVi / R2 + XC2

• For the special case where XC = R,

Vo =RVi / R2 = (1/2) Vi

ol

AV = Vo / Vi = (1/2) = 0.707

• The frequency at which this occurs is determined from,

XC = 1/2f1C = R

us

where, f1 = 1/ 2RC

• Gain equation is written as,

AV = Vo / Vi

= R / (R – jXC) = 1/ ( 1 – j(1/CR)

vt

= 1 / [ 1 – j(f1 / f)]

• In the magnitude and phase form,

AV = Vo / Vi

= [1 / 1 + (f1/f)2 ] tan-1 (f1 / f)

• In the logarithmic form, the gain in dB is

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AV = Vo / Vi = [1 / 1 + (f1/f)2 ]

= 20 log 10 [1 / 1 + (f1/f)2 ]

= - 20 log 10 [ 1 + (f1/f)2]

= - 10 log10 [1 + (f1/f)2]

• For frequencies where f << f1 or (f1/ f)2 the equation can be approximated by

in

AV (dB) = - 10 log10 [ (f1 / f)2]

= - 20 log10 [ (f1 / f)] at f << f1

• At f = f1 ;

n.

f1 / f = 1 and

– 20 log101 = 0 dB

• At f = ½ f1;

• At f = ¼ f1;

f1 / f = 2

– 20 log102 = - 6 dB

io

ut

f1 / f = 4

– 20 log102 = - 12 dB

• At f = 1/10 f1;

ol

f1 / f = 10

– 20 log1010 = - 20dB

• The above points can be plotted which forms the Bode – plot.

us

• Note that, these results in a straight line when plotted in a logarithmic scale.

Although the above calculation shows at f = f1, gain is 3dB, we know that f1 is

that frequency at which the gain falls by 3dB. Taking this point, the plot differs

from the straight line and gradually approaches to 0dB by f = 10f1.

vt

corresponding change in gain by 6dB.

• When there is an decade change in frequency from f1 / 10 to f1, there exists

corresponding change in gain by 20 dB.

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• A voltage divider BJT bias configuration with load is considered for this analysis.

• For such a network of voltage divider bias, the capacitors CS, CC and CE will

determine the low frequency response.

in

n.

io

Let us consider the effect of each capacitor independently.

CS:

ut

ol

1

fLs

us

2 (Rs Ri)Cs

Ri R1 || R2 || βre

vt

small to permit a short – circuit approximations for the element.

• The voltage Vi will then be related to Vs by

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• The voltage Vi applied to the input of the active device can be calculated using the

voltage divider rule:

Effect of CC:

• Since the coupling capacitor is normally connected between the output of the

active device and applied load, the RC configuration that determines the low

cutoff frequency due to CC appears as in the figure given below.

in

n.

•

1

io

ut

fLC

2 π(Ro RL)Cc

• Ro = Rc|| ro

ol

Effect of CE:

us

vt

1 R s R s Rs || R1 || R2

fLE Re RE || ( re)

2 πReCE β

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that the gain for the amplifier without bypassing the emitter resistor is given by:

AV = - RC / ( re + RE)

• Maximum gain is obviously available where RE is 0.

• At low frequencies, with the bypass capacitor CE in its “open circuit” equivalent

state, all of RE appears in the gain equation above, resulting in minimum gain.

• As the frequency increases, the reactance of the capacitor CE will decrease,

reducing the parallel impedance of RE and CE until the resistor RE is effectively

shorted out by CE.

in

• The result is a maximum or midband gain determined by AV = - RC / re.

• The input and output coupling capacitors, emitter bypass capacitor will affect only

the low frequency response.

• At the mid band frequency level, the short circuit equivalents for these capacitors

n.

can be inserted.

• Although each will affect the gain in a similar frequency range, the highest low

frequency cutoff determined by each of the three capacitors will have the greatest

impact.

Problem:

parameters:

Cs = 10μF, CE = 20μF, Cc = 1μF io

Determine the lower cutoff freq. for the network shown using the following

ut

Rs = 1kΩ, R1= 40kΩ, R2 = 10kΩ,

RE = 2kΩ, RC = 4kΩ, RL = 2.2kΩ,

β = 100, ro = ∞Ω, Vcc = 20V

ol

us

vt

• Solution:

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a. To determine re for the dc conditions, let us check whether RE > 10R2

Here, RE = 200k, 10R2 = 100k. The condition is satisfied. Thus approximate

analysis can be carried out to find IE and thus re.

VB = R2VCC / ( R1+R2) = 4V

VE = VB – 0.7 = 3.3V

IE = 3.3V / 2k = 1.65mA

in

re = 26mV / 1.65mA = 15.76

Mid band gain:

AV = Vo / Vi = -RC||RL / re = - 90

n.

• Input impedance

Zi = R1 || R2|| re = 1.32K

• Cut off frequency due to input coupling capacitor ( fLs)

io

fLs = 1/ [2(Rs +Ri)CC1 = 6.86Hz.

fLc = 1 / [2(RC + RL) CC

= 1 / [ 6.28 (4k + 2.2k)1uF]

ut

= 25.68 Hz

Effect of CE:

RS = RS||R1||R2 = 0.889

ol

Re = RE || (RS/ + re) = 24.35

fLe = 1/2 ReCE = 327 Hz

fLe = 327 Hz

us

fLC = 25.68Hz

fLs = 6.86Hz

In this case, fLe is the lower cutoff frequency.

• In the high frequency region, the capacitive elements of importance are the inter-

vt

electrode ( between terminals) capacitances internal to the active device and the

wiring capacitance between leads of the network.

• The large capacitors of the network that controlled the low frequency response are

all replaced by their short circuit equivalent due to their very low reactance level.

• For inverting amplifiers, the input and output capacitance is increased by a

capacitance level sensitive to the inter-electrode capacitance between the input

and output terminals of the device and the gain of the amplifier.

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• Any P-N junction can develop capacitance. This was mentioned in the chapter on

diodes.

• In a BJT amplifier this capacitance becomes noticeable between: the Base-

Collector junction at high frequencies in CE BJT amplifier configurations.

• It is called the Miller Capacitance.

• It effects the input and output circuits.

in

n.

•

•

Ii = I1 + I2

•

io

Eqn (1)

ut

I1 = Vi / Zi,

I1 = Vi / R1

and I2 = (Vi – Vo) / Xcf

ol

= ( Vi – AvVi) / Xcf

I2 = Vi(1 – Av) / Xcf

Substituting for Ii, I1 and I2 in eqn(1),

us

1/ Zi = 1/Ri + [(1 – Av)] /Xcf

1/ Zi = 1/Ri + 1/ [Xcf / (1 – Av)]

1/ Zi = 1/Ri + 1/ XCM

vt

= 1/[ (1 – Av) Cf]

CMi = (1 – Av) Cf

CMi is the Miller effect capacitance.

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• For any inverting amplifier, the input capacitance will be increased by a Miller

effect capacitance sensitive to the gain of the amplifier and the inter-electrode

( parasitic) capacitance between the input and output terminals of the active

device.

in

n.

CMo Cf

Applying KCL at the output node results in: io

ut

Io = I1+I2

I1 = Vo/Ro

and I2 = (Vo – Vi) / XCf

ol

The resistance Ro is usually sufficiently large to permit ignoring the first term of the

equation, thus

us

Substituting Vi = Vo / AV,

= Vo ( 1 – 1/AV) / XCf

vt

Io / Vo = (1 – 1/AV) / XCf

Vo / Io = XCf / (1 – 1/AV)

= 1 / Cf (1 – 1/AV)

= 1/ CMo

CMo = ( 1 – 1/AV)Cf

13

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If the gain (Av) is considerably greater than 1:

CMo Cf

High frequency response – BJT Amplifier

in

• At the high – frequency end, there are two factors that define the – 3dB cutoff point:

– The network capacitance ( parasitic and introduced) and

– the frequency dependence of hfe()

n.

Network parameters

• In the high frequency region, the RC network of the amplifier has the configuration

shown below.

Vi

io

ut

Vo

ol

• At increasing frequencies, the reactance XC will decrease in magnitude, resulting

in a short effect across the output and a decreased gain.

Vo = Vi(-jXC) / R -jXC

us

AV = 1/[ 1+j(2fRC)];

AV = 1/[ 1+jf/f2]

o This results in a magnitude plot that drops off at 6dB / octave with increasing

frequency.

vt

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Network with the capacitors that affect the high frequency response

in

n.

• Capacitances that will affect the high-frequency response:

Cbe, Cbc, Cce – internal capacitances

CS, CC – coupling capacitors

CE – bypass capacitor io

Cwi, Cwo – wiring capacitances

ut

ol

us

The capacitors CS, CC, and CE are absent in the high frequency equivalent of the BJT

amplifier.The capacitance Ci includes the input wiring capacitance, the transition

capacitance Cbe, and the Miller capacitance CMi.The capacitance Co includes the

output wiring capacitance Cwo, the parasitic capacitance Cce, and the output Miller

capacitance CMo.In general, the capacitance Cbe is the largest of the parasitic

vt

As per the equivalent circuit,

fH = 1 / 2RthiCi

Rthi = Rs|| R1||R2||Ri

Ci = Cwi+Cbe+CMi = CWi + Cbe+(1- AV) Cbe

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At very high frequencies, the effect of Ci is to reduce the total impedance of the

parallel combination of R1, R2, Ri, and Ci.The result is a reduced level of voltage

across Ci, a reduction in Ib and the gain of the system.

For the output network,

fHo = 1/(2RThoCo)

RTho = RC||RL||ro

Co = Cwo+Cce+CMo

in

At very high frequencies, the capacitive reactance of Co will decrease and

consequently reduce the total impedance of the output parallel branches.

The net result is that Vo will also decline toward zero as the reactance Xc becomes

smaller.The frequencies fHi and fHo will each define a -6dB/octave asymtote.

n.

If the parasitic capacitors were the only elements to determine the high – cutoff

frequency, the lowest frequency would be the determining factor.However, the

decrease in hfe(or ) with frequency must also be considered as to whether its break

frequency is lower than fHi or fHo.

•

io

The variation of hfe( or ) with frequency will approach the following relationship

ut

hfe = hfe mid / [1+(f/f)]

• f is that frequency at which hfe of the transistor falls by 3dB with respect to its

mid band value.

• The quantity f is determined by a set of parameters employed in the hybrid

ol

model.

• In the hybrid model, rb includes the

• base contact resistance

• base bulk resistance

us

vt

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Hybrid model

in

• The resistance ru(rbc) is a result of the fact that the base current is somewhat

sensitive to the collector – to – base voltage.

n.

• Since the base – to – emitter voltage is linearly related to the base current through

Ohm’s law and the output voltage is equal to the difference between the base the

base – to – emitter voltage and collector – to – base voltage, we can say that the

base current is sensitive to the changes in output voltage.

• Thus,

f = 1/[2r(C+Cu)]

r = re = hfe mid re

io

ut

• Therefore,

f = 1/[2 hfemid re(C+Cu)]

OR

ol

f = 1/[2 mid re(C+Cu)]

• The above equation shows that, f is a function of the bias configuration.

• As the frequency of operation increases, hfe will drop off from its mid band value

us

• Common base configuration displays improved high frequency characteristics

over the common – emitter configuration.

• Miller effect capacitance is absent in the Common base configuration due to non

inverting characteristics.

• A quantity called the gain – bandwidth product is defined for the transistor by the

vt

condition,

| hfemid / [1+j(f/f)| = 1

• So that,

|hfe|dB = 20 log10 | hfemid / [1+j(f/f)|

= 20 log101 = 0 dB

• The frequency at which |hfe|dB = 0 dB is indicated by fT.

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| hfemid / [1+j(f/f)| = 1

hfemid / 1+ (fT/f)2 hfemid / (fT/f) =1

( by considering fT>>f)

• Thus, fT = hfemid f OR fT = mid f

• But, f = 1/[2 mid re(C+Cu)]

in

fT = (mid) 1/[2 mid re(C+Cu)]

fT = 1/[2 re(C+Cu)]

n.

Problem:

For the amplifier with voltage divider bias, the following parameters are given:

RS = 1k , R1 = 40k, R2 = 10k, Rc = 4k, RL = 10k

Cs = 10F, Cc = 1 F, CE= 20 F

= 100, ro = , VCC = 10

io

C = 36pF, Cu = 4pF, Cce=1pF, Cwi=6pF, Cwo=8pF

a. Determine fHi and fHo

ut

b. Find f and fT

Solution:

To find re, DC analysis has to be performed to find IE.

ol

VB = R2VCC / R1+R2 = 2V

VE = 2 – 0.7 = 1.3V

IE = 1.3/1.2K = 1.083mA

us

re = 26mV / 1.083mA

re = 24.01,

re = 2.4k

Ri = RS||R1||R2||re

vt

Ri = 1.85k

AV = - 119

RThi = Rs||R1||R2||Ri

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RThi = 0.6k

To determine fHi and fHo:

fHi = 1/[2RThiCi] ;

Ci = Cwi+Cbe+(1 – AV)Cbc

= 6pF + 36pF + (1 – (-119)) 4pF

Ci = 522pF

in

fHi = 1/2RThiCi

fHi = 508.16kHz

RTho = Rc||RL

n.

RTho = 2.86k

Co = Cwo+Cce+C Mo

= 8pF+1pF+(1 – (1/-119))4pF

Co = 13.03pF

fHo = 1/2RThoCo

fHo = 8.542MHz io

ut

f = 1/[2 mid re(C+Cu)]

f = 1.66MHz

fT = f

ol

fT = 165.72MHz

Summary – Frequency response of BJT Amplifiers

• Logarithm of a number gives the power to which the base must be brought to

us

• Since the decibel rating of any equipment is a comparison between levels, a

reference level must be selected for each area of application.

• For Audio system, reference level is 1mW

• The dB gain of a cascaded systems is the sum of dB gains of each stage.

• It is the capacitive elements of a network that determine the bandwidth of a

system.

vt

• The larger capacitive elements of the design determine the lower cutoff

frequencies.

• Smaller parasitic capacitors determine the high cutoff frequencies.

• The frequencies at which the gain drops to 70.7% of the mid band value are called

– cutoff, corner, band, break or half power frequencies.

• The narrower the bandwidth, the smaller is the range of frequencies that will

permit a transfer of power to the load that is atleast 50% of the midband level.

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in a 6dB change in gain.

• For a 10:1 change in frequency is equivalent to one decade results in a 20dB

change in gain.

• For any inverting amplifier, the input capacitance will be increased by a Miller

effect capacitance determined by the gain of the amplifier and the inter electrode

( parasitic) capacitance between the input and output terminals of the active

device.

in

CMi = (1 – AV)Cf

• Also, CMo Cf (if AV >>1)

• A 3dB drop in will occur at a frequency defined by f, that is sensitive to the DC

n.

operating conditions of the transistor.

• This variation in defines the upper cutoff frequency of the design.

Problems:

io

1. The total decibel gain of a 3 stage system is 120dB. Determine the dB gain of

each stage, if the second stage has twice the decibel gain of the first and the third

has 2.7 times decibel gain of the first. Also, determine the voltage gain of the each

stage.

ut

• Given: GdBT = 120dB

We have GdBT = GdB1+GdB2+GdB3

Given, GdB2 = 2GdB1

ol

GdB3 = 2.7GdB1

Therefore, 120dB = 5.7GdB1

GdB1 = 21.05,

us

GdB2 = 42.10

GdB3 =56.84

We have GdB = 10 log[Vo / Vi]

Vo / Vi = antilog ( GdB/10)

vt

G1 = 127.35

G2 = 16.21k

G3 = 483.05k

2. If the applied ac power to a system is 5W at 100mV and the output power is 48W,

determine

a. The power gain in decibels

20

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c. The voltage gain in decibels, if the output impedance is 40k.

d. The input impedance

a. GdB =10 log [48/ 5] = 69.82

b. Po = Vo2 /Ro,

in

Vo = PoRo = 1385.64V

c. Voltage gain in dB = 20 log [1385.64/100m] = 82.83

d. Ri = Vi2 / Pi = 2k

n.

General steps to solve a given problem:

Normally, the amplifier circuit with all the values of biasing resistors, value of and

•

io

values inter electrode capacitances ( Cbe, Cbc and Cce) will be given.

It is required to calculate: fLS, fLC and fLE

ut

– Find the value of Ri ( Zi) using the value of re

– Find the value of AVmid

• Step 2: Find fLS using the formula 1/2(Ri+RS)CS

ol

• Step 3: Find fLC using the formula 1/2(RC+RL)CC

• Step 4: Determine the value of fLE using the formula 1/2ReCE

where, Re = RE || [(RS)/ + re]

us

RS = RS||R1||R2

• Step 5: Determine fHi using the formula 1/2RThiCi

where RThi = R1||R2||RS||re

Ci = Cwi + Cbe + (1-AV)Cbc

vt

where RTho = RC||RL||ro

Co = Cwo + Cce+ C bc

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1. fLs

2. fLc

3. fLE

in

4. fHi

5. fHo

6. f and fT

n.

io

ut

ol

• Given:

VCC = 20V, RB = 470k, RC = 3k, RE = 0.91k, RS = 0.6k, RL = 4.7k

CS = CC = 1F, CE = 6.8 F

us

Cwi = 7pF, Cwo=11pF, Cbe = 6pF, Cbe = 20pF and Cce = 10pF

Solution:

IB = (VCC – VBE) / [RB + ( +1)RE]

IB = 3.434mA

vt

IE = IB

IE = 3.434mA

re = 26mV / IE

re = 7.56

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AV = - (RC||RL) / re

AV = -242.2

Zi = RB|| re

Zi = 754.78

fLS = 1/2(Ri+RS)CS

fLS = 117.47Hz

in

fLC = 1/2(RC+RL)CC

fLC = 20.66 Hz

fLE = 1/2ReCE ;

n.

where, Re = [(RS /)+ re] || RE

RS = RB || RS

fLE = 1.752kHz

Ci = 1.48nF

RThi = RS || RB|| re

io

Ci = Cwi + Cbe + (1 – AV) Cbc

ut

RThi = 334.27

fHi = 1 / 2(1.48nF)(334.37)

fHi = 321.70 KHz

ol

Co = CWo + Cce + (1 – 1/AV) Cbc

Co = 27.02pF

RTho = RC || RL

us

RTho = 1.83K

fHo = 1 / 2(27.02p)(1.83k)

fHo = 3.21MHz

f = 1 / 2 (100) (7.56)( 20p + 6p)

vt

f = 8.09MHz

fT = f

fT = 803MHz

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Equations - Logarithms

1. a = bx, x = logba

2. GdB = 10 log P2 / P1

3. GdB = 20 log V2 / V1

in

Equations – Low frequency response

1. AV = 1 / [1 – j(f1/f)],

where, f1 = 1/2RC

n.

Equations – BJT low frequency response

1. fLs = 1 / [2(RS+Ri)CS] ,

where, Ri = R1||R2||re

2. fLC = 1 /[2(Ro+RL)CC],

where, Ro = RC||ro

3. fLE = 1 / 2ReCE, io

ut

where, Re = RE || ( RS/ +re) and RS = RS||R1||R2

Miller effect Capacitance

CMi = (1 – AV)Cf,

ol

CMO = ( 1 – 1/AV)Cf

BJT High frequency response:

1. AV = 1/ [1 + j(f/f2)]

us

2. fHi = 1 / 2RThiCi,

where, RThi = RS||R1||R2||Ri, Ci = CWi+Cbe+ CMi

3. fHO = 1/ 2RThoCo,

where, RTho = RC||RL||ro

vt

Co = CWo+Cce+ CMo

4. f = 1/[2 mid re(C+Cu)]

5. fT = f

24

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in

Power Amplifiers

n.

• Introduction

• Definitions and amplifier types

• Series fed class A amplifiers

io

• Transformer coupled class A amplifier

• Transformer coupled amplifier continuation

ut

• Numerical

• Class B amplifier operation

• Class B amplifier circuits

ol

• Numerical

• Amplifier distortion

• Numerical

us

• Power transistor heat sinking

• Thermal analogy of power transistor

vt

• Numerical

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Introduction

Amplifier receives a signal from some pickup transducer or other input

source and provides larger version of the signal.

In small signal amplifiers the main factors are usually amplification,

linearity and magnitude of gain.

in

Classes of PAs

Amplifier classes represent the amount the output signal varies over one

cycle of operation for a full cycle of input signal

n.

So the following classes of PA are defined

Class A

Class B

Class AB

Class C io

ut

Class D

Class A amplifier

ol

• Class A amplifying devices operate over the whole of the input cycle such

that the output signal is an exact scaled-up replica of the input with no

clipping. Class A amplifiers are the usual means of implementing small-

us

signal amplifiers. They are not very efficient. a theoretical maximum of 50%

is obtainable with inductive output coupling and only 25% with capacitive

coupling.

• In a Class A circuit, the amplifying element is biased so the device is always

vt

conducting to some extent, and is operated over the most linear portion of its

characteristic curve Because the device is always conducting, even if there is

no input at all, power is drawn from the power supply. This is the chief

reason for its inefficiency.

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in

n.

Class B

io

ut

• Class B amplifiers only amplify half of the input wave cycle. As such they

create a large amount of distortion, but their efficiency is greatly improved

and is much better than Class A. Class B has a maximum theoretical

ol

efficiency of 78.5% (i.e., π/4). This is because the amplifying element is

switched off altogether half of the time, and so cannot dissipate power.

• A single Class B element is rarely found in practice, though it can be used in

us

RF power amplifier where the distortion levels are less important. However

Class C is more commonly used for this.

vt

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n.

Class AB

io

• A practical circuit using Class B elements is the complementary pair or

ut

"push–pull" arrangement. Here, complementary or quasi-complementary

devices are used to each amplify the opposite halves of the input signal,

ol

which is then recombined at the output. This arrangement gives excellent

efficiency, but can suffer from the drawback that there is a small mismatch

at the "joins" between the two halves of the signal..

us

always be less efficient (below 78.5%). It is typically much more efficient

than class A.

vt

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in

n.

io

ut

Class C

ol

• Class C amplifiers conduct less than 50% of the input signal and the

distortion at the output is high, but high efficiencies (up to 90%) are

possible. Some applications (for example, megaphones) can tolerate the

us

transmitters, where the distortion can be vastly reduced by using tuned loads

on the amplifier stage.

vt

• The input signal is used to roughly switch the amplifying device on and off,

which causes pulses of current to flow through a tuned circuit.

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in

n.

Class D

io

ut

• Class D amplifiers are much more efficient than Class AB power amplifiers.

As such, Class D amplifiers do not need large transformers and heavy

ol

heatsinks, which means that they are smaller and lighter in weight than an

equivalent Class AB amplifier. All power devices in a Class D amplifier are

operated in on/off mode.

us

vt

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in

n.

Series fed class A amplifiers

ut

ol

us

vt

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DC bias operation

IB

RB

in

Collector –emitter voltage

VCE=VCC-ICRC

Load line

n.

io

ut

ol

us

Power considerations

The power into an amplifier is provided by the power supply

With no input supply, current drawn is collector bias current ICq.

vt

pi(dc)=VCCICq

Output power

The output voltage and current varying around the bias point provide ac

power to the load.

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P0(ac)=VCE(rms)IC(rms)

=I2C(rms) Rc

=V2C(rms)/Rc

Using peak signals

in

The ac power delivered to the load is

p0={VCE(p) IC(p)} / 2

or = {I2c(p)/2} Rc

n.

={V2CE(p)}/2Rc

Using peak-peak signals

P0(ac)={VCE(p-p) IC(p-p)}/8

= {I2c(p-p)/8} Rc

={V2CE(p)}/8Rc io

ut

Efficiency

Efficiency of an amplifier represents the amount of ac power delivered from

dc source. It can be calculated using

ol

Po(ac)

% x100

Pi(dc)

us

Maximum Efficiency

Maximum voltage swing VCE(p-p)=VCC

Maximum current swing IC(p-p)=VCC/RC

vt

Maximum power

Vcc(Vcc / Rc)

Po(ac)

8

The maximum power input evaluated using dc bias current set to half of the

maximum value….

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Vcc / Rc

Vcc

2

maximum Pi(dc)} x100

in

V 2 cc / 8 Rc

x100

V 2 cc / 2 Rc

n.

= 25%

Maximum efficiency

io

The maximum efficiency of a class A series fed amplifier is thus seen to be

25%.

ut

The maximum efficiency occurs only for ideal conditions of both voltage

and current swing .thus practical circuits will have less than this percentage.

ol

Numerical

Calculate input power, output power and efficiency of the amplifier circuit for the

us

circuit shown below for an input voltage that increases the base current by 10mA

peak.

Data given

VCC=20V

vt

Rc=20 ohms

RB=1k ohms

β=25

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in

n.

io

ut

Solution

Hint: use the above derived formulae

Po(ac)=0.625W

ol

Pi(dc)=9.6W

Efficiency=6.5%

us

vt

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in

n.

io

ut

The transformer can step up or step down a voltage applied to primary coil .

ol

I 2 N1 V 2 N2

I1 N 2 V 1 N1

us

• A form of class A amplifier having maximum efficiency of 50% uses

transformer to couple the output signal to the load.

Impedance transformation

vt

2

RL R 2 V 2 / I 2 V 2 I1 N 2 N 2 N 2

RL1 R1 V 1 / I1 I 2 I 2 N1 N1 N1

2

RL1 R1 N1

2

RL R 2 N 2

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R1 2 R 2

OR

RL1 2 RL

in

Transformer coupled amplifier

• Drawing DC and AC load line

n.

• Signal swing and output AC power

I C ( p p ) I C max I C min

io

(VCE max VCE min )( I C max I C min )

ut

Po ( ac )

8

N2

VL V2 V1

ol

N1

Power across the load can be expressed as

us

VL ( rms )

PL

RL

vt

• IL=I2=N1/N2 IC

• with the output ac power then calculated using

PL=IL2(rms) RL

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Numerical

Calculate the ac power delivered to 8 ohm speaker for the circuit shown below.

The circuit component values result in a dc base current of 6mA, and the input

signal Vi results in a peak base current swing of 4mA.

in

n.

io

ut

Solution:

ol

VCEQ=VCC=10V

us

VCEQ=10V & ICQ=140mA

Step 3: the effective resistance seen at the primary is RL’=(N1/N2)2 RL =72 ohms.

Step 4: the ac load line can be drawn of slope 1/72.

vt

IC=VCE/RL’=10/72=139mA

Mark point A on graph..

ICEQ+IC=140mA+139mA

Connect point A through the point Q to obtain the ac load line.

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For a given base current of 4mA peak , the maximum and minimum collector

current and collector –emitter voltage obtained from graph ..

Po (ac)

8

in

(18.3 1.7)( 255m 25m)

Po ( ac) 0.477W

8

n.

Efficiency

io

The input dc power obtained from the supply is calculated from the supply dc

voltage and thus average power drawn from the supply Pi(dc)= VCC ICQ

ut

For the transformer coupled amplifier power dissipated by the transformer is small

(due to small resistance)

The only power loss considered here is that dissipated by the power transistor and

ol

calculated by

PQ=Pi(dc) - Po(ac)

us

Po(ac)

% x100

Pi(dc)

Maximum theoretical efficiency

vt

2

(VCE max VCE min)

% 50 %

(VCE max VCE min)

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Larger the value of VCEmax and smaller the value of VCEmin, the closer the

efficiency approaches the theoretical limit of 50%

Numerical

in

Calculate the efficiency of a transformer coupled class A amplifier for a supply of

12V and outputs of :

a. V(p)=12V

n.

b. V(p)=6V

c. V(p)=2V

Solution :

io

Here VCE=VCC=12V, the maximum and minimum of the voltage swing are

VCEmax=VCEQ+V(p)=12V+12V=24V

ut

VCEmin=VCEQ-V(p)=12V-12V=0V

This results in efficiency of ,

ol

24 0

2

% 50 50%

24 0

Case ii.

us

VCEmax=VCEQ+V(p)=12V+6V=18V

VCEmin=VCEQ-V(p)=12V-6V=6V

This results in efficiency of 12.5%

vt

Case iii.

VCEmax=VCEQ+V(p)=12V+2V=14V

VCEmin=VCEQ-V(p)=12V-2V=10V

This results in efficiency of 1.39%

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• Class B operation is provided when the dc bias leaves the transistor biased

just off, the transistor turning on when the ac signal is applied.

• This is essentially no bias and conducts for only one half cycle.

in

• To obtain output for full cycle , it is required to use two transistors and have

each conduct on opposite half-cycles, the combined operation providing a

full cycle of output on opposite half cycles of output signal.

n.

• Since one part of the circuit pushes the signal high during one half cycle and

other part pulls the signal low during the other half cycle, the circuit is

referred to as push-pull circuit.

io

• Class B operation provides greater efficiency than was possible using single

transistor in class A operation.

ut

Class B push-pull

ol

us

vt

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Power equations

• Input DC power

Pi(dc)=VCC Idc

Here Idc is the average current drawn 2

Idc I ( p)

Hence Idc can be written as

in

Hence input power is equal to

2

Pi (dc) Vcc I ( p )

n.

Output ac power can be evaluated as,

2

V (rms )

Po (ac) L

RL io

ut

Efficiency:

Po(ac)

% x100

ol

Pi(dc)

2

VL ( p ) / 2 RL

% x100%

us

VL ( p )

x 100 78.5%

4 Vcc

vt

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• P2Q=Pi(dc)-Po(ac)

• Power handled by each transistor =P2Q/2

Numerical:

in

For a class B amplifier providing a 20V peak signal to a load of 16 ohms (speaker)

and power supply of VCC=30V, determine the input power, output power, and

circuit efficiency.

n.

Solution:

Hint : use the above derived formulae

• Pi(dc)=23.9W

• Po(ac)=12.5W

• Efficiency=52.3% io

ut

For a class B amplifier using supply of VCC=30V and driving a load of 16ohms

determine the maximum input power, output power and transistor dissipation.

ol

Solution:

Hint : use the above derived formulae

Po(ac)=28.125W

us

Pi(dc)=35.81W

Efficiency=78.54%

Pq=5.7W

vt

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2

V ( p)

Po(ac) L

2 RL

2V ( p )

Pi (dc) VCC I dc VCC L

in

RL

VL 2( p ) / 2 RL

% x100

n.

2V ( p )

VCC L

RL

VL( p )

% 78.54

Vcc

%

io

ut

Numerical

1. Calculate the efficiency of a class B amplifier for a supply voltage of

VCC=24V with peak output voltages of

ol

a. VL(p)=22V

b. VL(p)=6V

us

vt

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• To obtain phase inverted signals .

– To use transformers using op-amps

– Using transistors

Phase splitter circuits

in

n.

io

ut

ol

Using BJT

us

vt

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Using op-amp

in

n.

io

Transformer coupled push-pull amplifier

ut

ol

us

vt

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in

n.

Working of the circuit io

ut

• Every transistor will conduct for half cycle

• Single input signal is applied to the base of both transistors

• npn transistor will be biased in conduction for positive half cycle of the

ol

input.

• During negative half cycle pnp transistor is biased into conduction when

us

Disadvantages

• One disadvantage is that the need of two separate voltage supplies.

• Cross over distortion in the output signal

vt

signal during cross over from positive to negative or vice-versa. This is due

to the fact that, none of the transistors are on near zero input and thus output

does not follow input.

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• This circuit provides higher output current and lower output resistance.

• Here the load resistance is matched by low output resistance of the driving

source.

in

n.

io

ut

ol

us

devices.

• Practical means of obtaining complementary operation while using same,

matched transistors for the output is provided by a quasi complementary

vt

circuit.

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Circuit

in

n.

io

ut

• Here push-pull operation is achieved by using complementary transistors(Q1

ol

and Q2) before the matched npn output transistors (Q3 and Q4)

• Q1 and Q3 forms a Darlington connection

us

impedance to drive the load.

• Resistor R2 can be adjusted to minimize cross over distortion by adjusting

the dc bias condition.

vt

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Numerical

For the circuit shown calculate input power, output power and power handled by

each transistor and circuit efficiency.

• Given Vcc=+25V and VEE=-25V

• Input vi=12V

in

• Load resistance=4 ohms

n.

io

ut

ol

Solution:

us

• Po(ac)=36.125W

• Pi(dc)=67.75W

vt

• PQ=15.8W

• Efficiency=53.3%

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Numerical

For the circuit calculate maximum input power, maximum output power, input

voltage for maximum power operation and power dissipated by the output

transistor at this voltage.

Solution:

in

Hint: use the above derived formulae

• Pi(dc)=99.47W

• Po(ac)=78.125W

n.

• Efficiency=78.54%

• To achieve maximum power operation the output voltage must be

VL(p)=VCC

• PQ=21.3W

io

ut

Numerical

For the circuit shown, determine the maximum power dissipated by the output

transistors and the input voltage at which this occurs.

ol

Solution:

• PQ=31.66W

us

• VL=15.9V

vt

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Amplifier distortion

• Any signal varying over less than the full 3600 cycle is considered to have

distortion.

• An ideal amplifier is capable of amplifying a pure sinusoidal signal to

provide a larger version, the resulting waveform being a pure sinusoidal

in

frequency sinusoidal signal.

• When distortion occurs, output will not be an exact duplicate of input signal

(except for magnitude)

n.

• Distortion can occur because the device characteristic is not linear. In this

case non linear or amplitude distortion occurs.

• Distortion can also occur because the circuit elements and devices respond

io

to the input signal differently at various frequencies, this being frequency

distortion.

ut

• One technique for describing distorted but period waveforms uses Fourier

analysis, a method that describes any periodic waveform in terms of its

fundamental frequency component and frequency components at integer

ol

multiples- these components are called harmonic components or

harmonics.

us

Example

A fundamental frequency of 1KHz could result in harmonics of 2KHz,3KHz,4KHz

so on.,

vt

• 2KHz is termed as second harmonic

• 3KHz is termed as third harmonic and so on.,

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Harmonic Distortion

• A signal is considered to have harmonic distortion when there are harmonic

frequency components.

• If fundamental frequency has amplitude A1, and nth frequency component

has an amplitude of An.

in

• Harmonic distortion can be defined as

An

% nth harmonic distortion= %D x100%

A1

n.

Numerical

io

Calculate the harmonic distortion components for an output signal having

fundamental amplitude of 2.5V, second harmonic amplitude of 0.1V, and fourth

ut

harmonic amplitude of 0.05V.

Solution:

A2 0.25

ol

%D x100% x100% 10%

A1 2 .5

A3 0 .1

%D x100% x100% 4%

us

A1 2 .5

A4 0.05

%D x100% x100% 2%

A1 2 .5

vt

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components, the signal can be seen to have a total harmonic distortion based on the

individual elements as combined by relation,

in

%THD D2 D3 D4 .....x100%

2 2 2

Numerical

n.

Calculate the total harmonic distortion for the amplitude components given in

previous example

Solution:

%THD D2 D3 D4 .....x100%

2 2

io 2

ut

%THD 0.12 0.04 2 0.02 2 .....x100%

%THD 10.95%

ol

us

IcQ quiescent current

Io additional dc current due to non zero average of the distorted

signal

vt

2 second harmonic current due to twice the fundamental frequency

Solving for I1 and I2,

Io I2

4

Ic max Ic min

I1

2 Vtusolution.in

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1

VCE max VCE min VCEQ

D2 2 x100%

VCE max VCE min

in

In voltage terms

n.

1

(VCEMAX VCEMIN ) VCEQ

D2 2 x100%

VCEMAX VCEMIN

io

ut

Numerical

ol

measurements,

i.VCEmin=1V; VCEmax=22V;VCEQ=12V

ii.VCEmin=4V;VCEmax=20V;VCEQ=12V

us

solution:

1

22 1 12

i..D 2 2 x100% 2.38%

22 1

vt

1

20 4 12

i..D 2 2 x100% 0%(no distotion )

22 4

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the distorted signal is

2

I R

P1 1 c

2

in

• Total power due to all the harmonic components of the distorted signal is,

Rc

P ( I1 I 2 I 3 ......)

2 2 2

n.

2

In terms of Total harmonic distortion

P (1 D2 D3 ......) I1

2

P (1 THD 2 ) P1

2 2

io

Rc

2

ut

Numerical

ol

For harmonic distortion reading of D2=0.1,D3=0.02 and D4=0.01, with I1=4A and

Rc=8 ohms, calculate THD, fundamental power component and total power.

us

Solution: THD=0.1

P1=64W

P=64.64W

vt

• Conclusion: any periodic signal can be represented by adding a fundamental

component and all harmonic components varying in amplitude and at

various phase angles.

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Heat is produced in transistors due to the current flowing through them. If you find

that a transistor is becoming too hot to touch it certainly needs a heat sink! The

heat sink helps to dissipate (remove) the heat by transferring it to the surrounding

air.

in

n.

Heat sink

io

• Maximum power handled by a particular device and the temperature of the

transistor junction are related since the power dissipated causes an increase

ut

in temperature at the junction of the device.

• Example : a 100 W transistor will provide more power than 10 W transistor.

ol

• Proper heat sinking techniques will allow operation of a device at about one-

half its maximum power rating.

• There are two types of bipolar transistors

us

Germanium

Junction temperature : 100 – 1100C

Silicon

Junction temperature : 150 – 2000C

vt

• Average power dissipated may be approximated by

PD=VCEIC

• This power dissipation is allowed only up to a maximum temperature.

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(derated) so that at higher temperature, power handling capacity is reduced.

• The limiting factor in power handling by a particular transistor is the

temperature of the device’s collector junction.

• Power transistors are mounted in large metal cases to provide a large area

in

from which the heat generated by the device may radiate.

• Even then the device power rating limited.

• Instead if the device is mounted on the heat sink power handling capacity is

n.

increased.

• The derated curve for silicon transistor given by

io

ut

ol

us

Mathematical definition.

vt

derating factor

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Numerical:

Determine what maximum dissipation will be allowed for an 80W silicon transistor

rated at 25 degree C. if derating s required above this temp by derating factor of

0.5W/degree C at case temp of 125 degree C.

Solution:

in

Using the above formula

Power derated is 30W

n.

Thermal analogy of power transistor

• θJA total thermal resistance (jn to ambient)

• θJC transistor thermal resistance (jn. To case)

io

• θCS insulator thermal resistance (case to heat-sink

• θSA heat-sink thermal resistance (heat sink to ambient)

• Usng electrcal analogy

ut

• θJA= θJC+ θCS + θSA

• This analogy can be used n applying kirchoff’s law as

TJ = PD θJA +TA

ol

• The thermal factor θ provides information about how much temp drop( or

rise) for amount of power dissipation .

us

• Eg: θJC =0.5 deg C/W means that power dissipation of 50W.the dffernce

between junton temp and case temp s gven by

TJ-TC = θJC PD = 0.5x50 =25 deg C.

• Value of thermal resistance from junction to free air (using HS) 40 deg

vt

C/W

• For this thermal resistance only 1W of power dissipation results n junction

temp 40 deg C greater than the ambient.

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• A HS can now be seen to provide a low thermal resistance between case and

air much less than 40 deg C/W value of case alone. Using HS having

• θSA 2 deg C/W

And insulating thermal resistance (case to HS)

• θCS 0. 8 deg C/W

in

• Finally for transistor

• θJC 0.5 deg C/W

• θJA= θJC+ θCS + θSA

n.

= 2.0 +0.8 +0.5

= 3.3 deg C/W

With HS thermal resistance between air and the junction is only 3.3 deg C/W

io

compared 40 deg C/W for transistor operating directly in to free air

ut

Numerical:

A silicon power transistor s operated with a HS θSA = 1.5 deg C/w. the transistor

ol

rated at 150W(25 deg C) has θJC =0.5 deg C/W and the mounting insulation has

θCS =0.6 deg C /W. what s the max power dissipated f the ambient temp s 40 deg

us

• Solution : pd =(TJ-TA)/ θSA + θJC + θCS

= 61.5W

vt

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in

n.

io

ut

Class C

• The circuit is biased to operate for less than 180 deg of input cycle. The

tuned circuit n the load provide a full cycle of output signal for fundamental

ol

frequency of tuned LC circuit. This type of operation s thus limited to one

fixed frequency as n communication systems.

• Not suitable for power amplification

us

Class D amplifier

• Class D designed to operate with digital or pulse type signals

• Efficiency of 90% can be achieved.

• Desirable for power amplifiers.

vt

• Necessary to convert any input signal in to pulse type wave before using to

drive a large power load and to convert the signal back to sinusoidal type

signal to recover the original signal .

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• Here class – D amplifier we can also consider D stands for Digital since that

s the name of the signal provided to the class D amplifier .

Block diagram of class D

in

n.

io

• Most of the power applied to the amplifier is transferred to the load the

ut

efficiency of the circuit s typically very high.

ol

us

vt

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Chapter.8: Oscillators

• Objectives:

– To understand

• The basic operation of an Oscillator

• the working of low frequency oscillators

– RC phase shift oscillator

in

– Wien bridge Oscillator

• the working of tuned oscillator

– Colpitt’s Oscillator, Hartley Oscillator

– Crystal Oscillator

• the working of UJT Oscillator

n.

Basic operation of an Oscillator

• An amplifier with positive feedback results in oscillations if the following

•

conditions are satisfied:

io

– The loop gain ( product of the gain of the amplifier and the gain of the

If the output signal is sinusoidal, such a circuit is referred to as sinusoidal

ut

oscillator.

ol

us

vt

1

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When the switch at the amplifier input is open, there are no oscillations. Imagine that a

voltage Vi is fed to the circuit and the switch is closed. This results in Vo = AV Vi and

Vo = Vf is fed back to the circuit. If we make Vf = Vi, then even if we remove the input

voltage to the circuit, the output continues to exist.

Vo = AV Vi

Vo = Vf

AV Vi = Vf

If Vf has to be same as Vi, then from the above equation, it is clear that, AV =1.

in

Thus in the above block diagram, by closing the switch and removing the input, we are

able to get the oscillations at the output if AV =1, where AV is called the Loop gain.

Positive feedback refers to the fact that the fed back signal is in phase with the input

signal. This means that the signal experiences 0 phase shift while traveling in the loop.

n.

The above condition along with the unity loop gain needs to be satisfied to get the

sustained oscillations. These conditions are referred to as ‘Barkhausen criterion’.

Another way of seeing how the feedback circuit provides operation as an oscillator is

obtained by noting the denominator in the basic equation

Af = A / (1+A).

io

When A = -1 or magnitude 1 at a phase angle of 180, the denominator becomes 0 and

the gain with feedback Af becomes infinite.Thus, an infinitesimal signal ( noise voltage)

can provide a measurable output voltage, and the circuit acts as an oscillator even without

an input signal.

ut

Phase shift oscillator

ol

us

• The phase shift oscillator utilizes three RC circuits to provide 180º phase shift that

when coupled with the 180º of the op-amp itself provides the necessary feedback

to sustain oscillations.

• The gain must be at least 29 to maintain the oscillations. The frequency of

resonance for the this type is similar to any RC circuit oscillator:

vt

fr = 1/26RC

2

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in

n.

• The amplifier stage is self biased with a capacitor bypassed source resistor Rs and

a drain bias resistor RD . The FET device parameters of interest are gm and rd.

•

•

•

io

|A| = gmRL, where RL = (RDrd / RD + rd)

At the operating frequency, we can assume that the input impedance of the

amplifier is infinite.

This is a valid approximation provided, the oscillator operating frequency is low

enough so that FET capacitive impedances can be neglected.

ut

• The output impedance of the amplifier stage given by R L should also be small

compared to the impedance seen looking into the feedback network so that no

attenuation due to loading occurs.

ol

us

vt

• If a transistor is used as the active element of the amplifier stage, the output of the

feedback network is loaded appreciably by the relatively low input resistance

( hie) of the transistor.

3

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could be used.If a single transistor stage is desired, the use of voltage – shunt

feedback is more suitable. Here, the feedback signal is coupled through the

feedback resistor R’ in series with the amplifier stage input resistance ( Ri).

in

Problem:

40 k , and a feedback circuit value of R = 10 k. Select the value of C for oscillator

n.

operation at 5 kHz and RD for A > 29 to ensure oscillator action.

Solution:

• |A| = gm RL

Let A = 40; RL = |A| / gm = 8 k

ut

ol

us

Wien Bridge

vt

4

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in

• When the bridge is balanced,

f = 1/[2 R3C1R4C2]

n.

Wien bridge Oscillator

io

ut

ol

us

• R and C are used for frequency adjustment and resistors R1 and R2 form part of

the feedback path.

• If R3 = R4 =R, C1 = C2 = C, the resulting frequency is f = 1/2RC

and R2 / R1 = 2

vt

Tuned Oscillators

5

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in

• A variety of circuits can be built using the above diagram, by providing tuning in

both the input and output sections of the circuit.

• Analysis of the above diagram shows that the following types of Oscillators are

n.

obtained when the reactance elements are as designated:

Oscillator type X1 X2 X3

Colpitts Oscillator

Hartley Oscillator

io C

L

C

L

L

C

ut

Tuned input, Tuned Output LC LC -

ol

us

Colpitts Oscillator

vt

6

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in

n.

• The Colpitts oscillator utilizes a tank circuit (LC) in the feedback loop. The

io

resonant frequency can be determined by the formula below. Since the input

impedance affects the Q, an FET is a better choice for the active device.

fr = 1/2LCT

ut

CT = C1C2 / C1 + C2

ol

us

vt

• An Op amp Colpitts Oscillator circuit can also be used wherein the Op amp

provides the basic amplification needed and the Oscillator frequency is set by an

LC feedback network.

Hartley Oscillator

7

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in

n.

The Hartley oscillator is similar to the Colpitts. The tank circuit has two inductors and

one capacitor. The calculation of the resonant frequency is the same.

io

f = 1/2LTC

LT = L1 + L2 + 2M

ut

where, M is mutual coupling

ol

us

vt

Crystal Oscillator

8

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crystal as a resonant circuit.

• The crystal ( usually quartz) has a greater stability in holding constant at

whatever frequency the crystal is originally cut to operate.

• Crystal Oscillators are used whenever great stability is required, such as

communication transmitters and receivers.

in

Characteristics of a Quartz Crystal

• A quartz crystal exhibits the property that when mechanical stress is applied

across one set of its faces, a difference of potential develops across the opposite

faces.

n.

• This property of a Crystal is called ‘ Piezoelectric effect’.

• Similarly, a voltage applied across one set of faces of the Crystal causes

mechanical distortion in the Crystal shape.

• When alternating voltage is applied to a crystal, mechanical vibrations are set up

– these vibrations having a natural resonant frequency dependent on the Crystal.

•

io

Although the Crystal has electromechanical resonance, we can represent the

Crystal action by equivalent electrical circuit as shown.

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•

The inductor L and the capacitor C represent electrical equivalents of Crystal mass

and compliance respectively, whereas resistance R is an electrical equivalent of the

crystal structures internal friction. The shunt capacitance CM represents the

capacitance due to mechanical mounting of the crystal. Because the crystal losses,

represented by R, are small, the equivalent crystal Q factor is high – typically 20,000.

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Values of Q up to almost 106 can be achieved by using Crystals. The Crystal can

have two resonant frequencies. One resonant condition occurs when the reactances of

the series RLC leg are equal. For this condition, the series – resonant impedance is

very low ( equal to R). The other resonant condition occurs at a higher frequency

when the reactance of the series resonant leg equals the reactance of the capacitor CM.

This is parallel resonance or antiresonance condition of the Crystal,

At this frequency, the crystal offers very high impedance to the external circuit.

9

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To use the crystal properly, it must be connected in a circuit so that its low

impedance in the series resonant operating mode or high impedance in the

antiresonant operating mode is selected.

• To excite a crystal for operation in the series – resonant mode, it may be

connected as a series element in a feedback path.

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• At the series resonant frequency of the crystal, its impedance is smallest and the

amount of feedback is largest.

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•

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R3 can be replaced with RF choke. Resistors R1, R2 and RE provide a voltage divider

stabililized dc bias circuit. Capacitor CE provides ac bypass of the emitter resistor,

RFC coil provides for dc bias while decoupling any ac signal on the power lines from

affecting the output signal. The voltage feedback from collector to base is a maximum

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when the crystal impedance is minimum ( in series – resonant mode). The resulting

circuit frequency of oscillation is set by the series – resonant frequency of the crystal.

The circuit frequency stability is set by the crystal frequency stability which is good.

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in shunt. The circuit is similar to a Colpitts circuit with Crystal connected as inductor

10

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element. Maximum voltage is developed across the crystal at its parallel resonant

frequency. The voltage is coupled to the emitter by a capacitor voltage divider

capacitors C1 and C2.

in

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•

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An Op – amp can be used in a crystal oscillator. The crystal is connected in the

series resonant path and operates at the crystal series resonant frequency.

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Unijunction Oscillator

Unijunction transistor( UJT) can be used in a single stage oscillator circuit to provide

a pulse signal suitable for digital circuit applications. The UJT can be used in

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relaxation oscillator.

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The operation of the circuit is as follows: C1 charges through R1 until the voltage

across it reaches the peak point. The emitter current then rises rapidly, discharging C1

through the base 1 region and R3. The sudden rise of current through R3 produces the

voltage pulse. When the current falls to IV the UJT switches off and the cycle is

repeated. Oscillator operating frequency fo = 1/{RTCTln[1/(1-)]} where, is

intrinsic standoff ratio, typically the value of it is between 0.4 and 0.6.

Using = 0.5, fo = 1.5 / RTCT

11

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Capacitor is charged through resistor RT toward supply voltage VBB. As long as the

capacitor voltage VE is below a stand – off voltage (VP) set by the voltage across

B1-B2 and the transistor stand – off ratio .

• VP = VB1VB2 – VD.

When the capacitor voltage exceeds this value, the UJT turns ON, discharging the

capacitor. When the capacitor discharges, a voltage rise is developed across R3.

The signal at the emitter of UJT / across the capacitor is saw tooth, at the base 1 are

positive going pulses and at the base 2 are negative going pulses.

in

Summary:

n.

• Wien bridge Oscillator f = 1/2RC

• Colpitts Oscillator, f = 1/2 LCeq

• Ceq = C1C2/(C1+C2)

• Hartley Oscillator, f = 1/2 LeqC

• Leq = L1+L2+2M

•

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UJT Oscillator: f = 1/{RTCTln[1/(1-)]}

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vt

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