BSNL TTA (JE) DIGITAL TECHNIQUES 200 EXPECTED

QUESTIONS (WWW.ALLEXAMREVIEW.COM)
ANSWER KEY-Correct answer is indicated by symbol (V) in options.
HINTS-In some questions options E-HINTS is indicating the hints of answer

1) Which of the following memories uses one transistor and one capacitor as basic
memory unit
A [ ]) SRAM
B [v]) DRAM
C [ ]) Both SRAM and DRAM
D [ ]) None

2) A latch is ________ sensitive

A [ ]) both level and edge
B [ ]) edge
C [v]) level
D [ ]) None

3) How many entries will be in the truth table of a 3 input NAND gate ?
A [ ]) 3
B [ ]) 6
C [v]) 8
D [ ]) 9

4) How many bits are required to store one BCD digit ?

A [ ]) 2
B [ ]) 3
C [ ]) 6
D [v]) 4

5) In binary number system the first digit (bit) from right to left is called as
A [v]) LSB, Least Significant Bit
B [ ]) MSB, Most Significant Bit
C [ ]) First Bit
D [ ]) Last Bit

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6) In an SR latch built from NOR gates, which condition is not allowed
A [ ]) S=0, R=0
B [ ]) S=0, R=1
C [ ]) S=1, R=0
D [v]) S=1, R=1

7) A D-flip-flop is said to be transparent when

A [ ]) the output is LOW
B [ ]) the output is HIGH
C [ ]) the output follows clock
D [v]) the output follow input

8) Which of these sets of logic gates are designated as universal gates?

A [v]) NOR, NAND.
B [ ]) XOR, NOR, NAND.
C [ ]) OR, NOT, AND.
D [ ]) NOR, NAND, XNOR.

9) In the toggle mode a JK flip-flop has

A [ ]) J = 0, K = 0.
B [v]) J = 1, K = 1.
C [ ]) J = 0, K = 1.
D [ ]) J = 1, K = 0.
E [ ]) HINTS-J = 0, K = 0; no change condition between pre-state and next state. J = 0, K = 1; it is
always reset condition means next state is always 0. J = 1, K = 0; it is always set condition means
next state is always 1. J = 1, K = 1; it is toggle condition means when pre-state is 1 then next state
is 0 or when pre-state is 0 then next state is 1.

10) A three-state buffer has the following output states

A [ ]) 1, 0, float
B [ ]) High, Low, Float
C [v]) Both A and B

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 D [ ]) Set, Reset, Halt

11) Which of the following is a digital device

A [ ]) Regulator of a fan
B [ ]) Microphone
C [ ]) Resistance of a material
D [v]) Light switch

12) If a Hexadecimal number needs to convert to binary. For each hexadecimal digit, there
will be how many bits
A [ ]) 2
B [ ]) 6
C [v]) 4
D [ ]) 8

13) Temperature variation is a/an

A [ ]) Digital quantity
B [v]) Analog quantity
C [ ]) Either Digital or Analog quantity
D [ ]) None

14) In Digital Logic Designs, GAL is abbreviated as

A [ ]) General Advance Logic
B [ ]) General Array Logic
C [ ]) Generic Advance Logic
D [v]) Generic Array Logic
E [ ]) HINTS-GAL is Generic Array Logic. It is a re programmable device used in Digital Systems.

15) In decimal number system what is MSD

A [v]) First digit from left to right
B [ ]) First digit from right to left
C [ ]) Middle digit
D [ ]) Mean of all digits

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16) A digital circuit that can store on bit is a
A [ ]) XOR gate
B [v]) flip-flop
C [ ]) gate
D [ ]) registor

17) Stack is also known as

A [ ]) FIFO memory
B [ ]) Flash memory
C [v]) LIFO memory
D [ ]) LILO memory

18) Queue is also known as

A [v]) FIFO memory
B [ ]) LIFO memory
C [ ]) Flash memory
D [ ]) LILO memory

19) 1 Kilo bits are equal to

A [ ]) 1000 bits
B [v]) 1024 bits
C [ ]) 1012 bits
D [ ]) 1008 bits

20) A Nibble is equal to ________ bit(s)

A [ ]) 1
B [ ]) 2
C [v]) 4
D [ ]) 8
E [ ]) HINTS-In digital systems, bit is the smallest unit of storage consisting of either 0 or 1.
Grouping of such 4 bits are called nibble and grouping of such 8 bits are called byte.

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21) If J = K (J and K are shorted) in a JK flip-flop, what circuit is made
A [ ]) SR flip-flop
B [ ]) Shorted JK flip-flop
C [v]) T flip-flop
D [ ]) K flip-flop
E [ ]) HINTS-A T flip-flop toggles its output when a 1 is provided at input, otherwise output does
not change. It is actually a JK flip-flop with the J and K inputs shorted.

22) In digital systems, 1 byte is equal to ________ bit(s).

A [ ]) 1
B [ ]) 2
C [ ]) 4
D [v]) 8

23) Which logic family provide minimum power dissipation

A [ ]) TTL
B [v]) CMOS
C [ ]) ECL
D [ ]) JFET

24) Boolean algebra is also known as

A [ ]) Gate algebra
B [ ]) Transistor algebra
C [v]) Switching algebra
D [ ]) Counting algebra

25) In a T flip-flop no of input circuit is

A [v]) 1
B [ ]) 2
C [ ]) 3
D [ ]) 4

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26) A boolean function can be transformed into logical ________.
A [ ]) graph
B [ ]) map
C [v]) diagram
D [ ]) matrix

27) The boolean algebra is mostly based on

A [ ]) Boolean theorem
B [v]) De Morgans theorem
C [ ]) De Morpans theorem
D [ ]) Standard theorem

28) In the boolean algebra, a variable has ________ different state(s)/value(s).

A [ ]) 1
B [v]) 2
C [ ]) 4
D [ ]) 8

29) In Boolean algebra A.A is equal to

A [v]) A
B [ ]) A²
C [ ]) 2A
D [ ]) 1

30) AND operation is equivalant to

A [ ]) Division
B [ ]) Union
C [v]) Intersection
D [ ]) Both B and C
E [ ]) HINTS-Logical AND operation means Y = A.B i.e. A AND B = A Intersection B. It results in
1, if and only if all the inputs are 1.

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31) OR operation is equivalant to
A [ ]) Division
B [v]) Union
C [ ]) Intersection
D [ ]) Both B and C
E [ ]) HINTS-Logical OR operation means A OR B = A Union B (Y = A + B). It results in 1, if at
least one input is 1.

32) X + X.Y = ?
A [ ]) 1
B [ ]) 0
C [ ]) Y
D [v]) X

33) Truth table is used to express

A [v]) Boolean expression
B [ ]) Boolean map
C [ ]) Boolean matrix
D [ ]) Boolean addition

34) Complement of NOR and OR gate is ________ and ________ respectively.

A [ ]) AND, NAND
B [ ]) NAND, AND
C [v]) OR, NOR
D [ ]) NOR, OR

35) A + ? is equal to
A [ ]) A
B [ ]) ?
C [ ]) 0
D [v]) 1
E [ ]) HINTS-Logical OR of a variable and its complement is always equal to 1, i.e. A + ? = 1.

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36) A . ? is equal to
A [ ]) A
B [ ]) ?
C [v]) 0
D [ ]) 1

37) Complement of XNOR and NOR is ________ and ________ respectively.

A [ ]) NOR, XNOR
B [ ]) OR, NOR
C [ ]) XOR, NOR
D [v]) XOR, OR

38) Convert the binary number (1111000011110000) to hexadecimal number

A [ ]) 1010
B [v]) F0F0
C [ ]) 7070
D [ ]) 5050

39) Maximum number in decimal that can be represented by 4 bits (binary) is

A [ ]) 4
B [ ]) 7
C [v]) 15
D [ ]) 16

40) 1s Complement of 11001010 is

A [ ]) 11001011
B [ ]) 11001001
C [v]) 00110101
D [ ]) 00110111

41) Positive integers must be represented by

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 A [ ]) signed numbers
B [v]) unsigned number
C [ ]) Both A and B
D [ ]) None of these
E [ ]) HINTS-Positive integers are represented using unsigned numbers and negative integers
are represented by signed numbers on the extreme left.

42) 2's Complement of 10101011 is

A [v]) 01010101
B [ ]) 00111100
C [ ]) 10101011
D [ ]) 10101100
E [ ]) HINTS-2's Complement = 1's Complement + 1. 1's Complement of 10101011 is 01010100.
2's Complement of 10101011 is 01010101.

43) The difference between the diagram of a NOR and OR gate is

A [ ]) OR has got a bubble at its output terminal
B [v]) NOR has got a bubble at its output terminal
C [ ]) OR is more squared than NOR
D [ ]) OR is more oval than NOR

44) Transfer of data from one register to another register is known as ________ register
operation.
A [v]) Inter
B [ ]) Intra
C [ ]) Inside
D [ ]) In between

45) EBCDIC is abbreviated as

A [ ]) Extended Bit Coded Decimal Interchange Code
B [ ]) Extended Binary Coded Dectation Interchange Code
C [ ]) Extended Binary Color Decimal Interchange Code
D [v]) Extended Binary Coded Decimal Interchange Code

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 E [ ]) HINTS-Extended Binary Coded Decimal Interchange Code is an eight bit code encoding
mainly used on IBM devices.

46) Extended Binary Coded Decimal Interchange Code is an ________ bit code
A [ ]) 2
B [ ]) 4
C [v]) 8
D [ ]) 7

47) All the integers and decimal numbers are represented by

A [ ]) whole numbers
B [v]) real numbers
C [ ]) even numbers
D [ ]) odd numbers

48) A sequence of binary digits is known as

A [v]) bit string
B [ ]) byte string
C [ ]) input string
D [ ]) word string

49) When will be the output of an AND gate is LOW ?

A [v]) When any input is LOW
B [ ]) When any input is HIGH
C [ ]) When all inputs are HIGH
D [ ]) When all input is LOW

50) Why decoder is used in the digital electronics ?

A [v]) To convert coded information into non coded form
B [ ]) To convert non coded information into coded form
C [ ]) It is used to separate address bus and data bus
D [ ]) None of the above

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51) When will be the output of a NOT gate is HIGH ?
A [ ]) the input is HIGH
B [v]) the input is LOW
C [ ]) the input is HIGH and LOW
D [ ]) none of the above

52) Which is the example of digital device from the given option ?
A [ ]) Sensors
B [ ]) Record players
C [v]) Microprocessors
D [ ]) Thermistors

53) How many input and output required for demultiplexer ?

A [ ]) one input and one output
B [ ]) number of selection inputs and one output
C [v]) one input and many output
D [ ]) None of the above

54) How many stable state/states present in flip-flop ?

A [ ]) 1
B [ ]) 0
C [v]) 2
D [ ]) 4
E [ ]) HINTS-Flip flop is a bistable multivibrator, so it has 2 stable states.

55) Why generic array logic (GAL) device was invented ?

A [ ]) Mask programmable
B [ ]) One-time programmable
C [v]) Reprogrammable
D [ ]) None of the above

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56) What is the radix of octal number system ?
A [ ]) 2
B [ ]) 16
C [ ]) 7
D [v]) 8

57) What is the requirement of fullsubstractor circuit ?

A [ ]) Three inputs and two outputs
B [ ]) Three inputs and one output
C [v]) Two inputs and two outputs
D [ ]) Two inputs and three outputs

58) When will be the output of an OR gate is LOW ?

A [v]) When all input is LOW
B [ ]) When any input is HIGH
C [ ]) When all inputs are HIGH
D [ ]) When any input is LOW

59) Why encoder is used in the digital electronics ?

A [v]) To convert non coded information into coded form
B [ ]) To convert coded information into non coded form
C [ ]) It is used to separate address bus and data bus
D [ ]) None of the above

60) How the digital signals is transmitted through a single conductor ?

A [ ]) Parallel
B [ ]) Analog
C [v]) Serial
D [ ]) None of the above

61) How many input and output required for multiplexer ?

A [v]) Many input and one output

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 B [ ]) One input and many output
C [ ]) One input and one output
D [ ]) None of the above

62) When will be the output of an AND gate is HIGH if there are three inputs, A, B, and C ?
A [ ]) A = 0, B = 0, C = 0
B [ ]) A = 1, B = 1, C = 0
C [ ]) A = 1, B = 0, C = 1
D [v]) A = 1, B = 1, C = 1

63) How many output is high of NOR GATE ?

A [ ]) 2
B [ ]) 3
C [v]) 1
D [ ]) 4

64) Why small bubble is given on the output of the NAND gate symbol ?
A [ ]) Tristate
B [v]) Output is inverted
C [ ]) Open collector output
D [ ]) None of the above

65) What is the Boolean expression for a two-input AND gate ?

A [ ]) A + B
B [v]) A.B
C [ ]) A & B
D [ ]) A - B

66) When will be the output of an exclusive-OR gate is HIGH ?

A [v]) The inputs are different
B [ ]) All inputs are LOW
C [ ]) All inputs are HIGH

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 D [ ]) The inputs are equal

67) Which of the following logic circuits is the fastest ?

A [ ]) DTL.
B [ ]) RTL.
C [v]) TTL.
D [ ]) All have same speed.

68) A single flip-flop can be cleared (reset) to

A [ ]) 1
B [v]) 0
C [ ]) Both A and B
D [ ]) None

69) The time required for a gate to change its output is called as
A [ ]) Decay time
B [ ]) start time
C [ ]) run time
D [v]) propagation time

70) At which the digital data can be applied to a a gate is known as ________ frequency.
A [ ]) Propagation
B [ ]) Truth
C [v]) Operating
D [ ]) Run-time

71) Combinations that are not listed for the input variables are
A [ ]) Overflow
B [ ]) Carry
C [ ]) Borrow
D [v]) Dont Cares

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72) what is the minimum number of 2 input NAND gates used to perform the function of 2
input OR gate
A [ ]) 1
B [ ]) 2
C [v]) 3
D [ ]) 4

73) Which circuit is used in between two systems having two different codes
A [ ]) Sequential
B [ ]) Combinational
C [ ]) Both A and B
D [v]) Conversion

74) A full adder has

A [ ]) 2 inputs, 2 outputs
B [v]) 3 inputs, 2 outputs
C [ ]) 2 inputs, 1 output
D [ ]) 3 inputs, 1 output

75) A half adder has

A [ ]) 1 input and 1 output
B [v]) 2 inputs and 1 output
C [ ]) 1 input and 2 outputs
D [ ]) 2 inputs and 2 outputs

76) The switch which clears a flip-flop is know as

A [ ]) Reset
B [ ]) Clear
C [v]) Both A and B
D [ ]) None

77) Master-slave flip flop consists of ________ flip-flop(s).

A [ ]) 1

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 B [v]) 2
C [ ]) 3
D [ ]) 4

78) The momentary change in the output/state of the flip-flops is known as

A [ ]) tri-state
B [ ]) unstable state
C [ ]) inverter
D [v]) trigger

79) The state of a flip-flop can be switched by changing its ________ signals.
A [v]) input
B [ ]) output
C [ ]) triggering
D [ ]) clearing

80) Which of the following is equivalant to an ODD function

A [v]) XOR
B [ ]) XNOR
C [ ]) NOR
D [ ]) AND-NOR
E [ ]) HINTS-The truth table of the XOR gate is similar to an ODD function. Output of XOR gate
will be One/High if and only if ODD number of inputs are One/High.,,

81) Odd parity of a bit stream can be tested using ________ gate.
A [ ]) OR
B [ ]) AND
C [ ]) NOR
D [v]) XOR

82) 1 Gigabyte is equal to

A [ ]) 1024 bytes
B [ ]) 1024 bits

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 C [ ]) 1024 kbytes
D [v]) 1024 Mbytes

83) 1 kb represents
A [v]) 1024 bits
B [ ]) 1000 bits
C [ ]) 100 bits
D [ ]) 10,000 bits

84) A multiplexer is a combinational logic circuit used to perform the operation

A [ ]) AND-AND
B [v]) AND-OR
C [ ]) NOR-OR
D [ ]) XOR-NAND

85) A small circle or dot on top of an IC represents

A [ ]) Pin2
B [ ]) Pin13
C [ ]) Pin14
D [v]) Pin1

86) Number of 2 input multiplexers need to construct a 210 inputs multiplexer is _________
A [ ]) 32
B [ ]) 9
C [ ]) 129
D [v]) 1023

87) If 4 input MUXes drive a 4 input multiplexer, it results a

A [v]) 16 input MUX
B [ ]) 8 input MUX
C [ ]) 6 input MUX
D [ ]) 4 input MUX

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88) The main equation for a D flip flop is
A [ ]) Q=0
B [ ]) Q=1
C [v]) Q=D
D [ ]) Q=D'

89) Simplified form of the function f = (x+y+xy)(x+z)

A [ ]) x+y
B [v]) x+yz
C [ ]) x+xyz
D [ ]) y+xz

90) A graphical representation of a products in a truth table is called as

A [ ]) Mapping
B [ ]) Graphing
C [ ]) T-Map
D [v]) K-Map

91) For 4 bit parallel addition, we need ________ half adder(s) and ________ full adder(s)
A [v]) 1 and 3
B [ ]) 1 and 4
C [ ]) 0 and 3
D [ ]) 0 and 4

92) A half adder is a ________ circuit.

A [v]) Combinational
B [ ]) Sequential
C [ ]) Both A and B
D [ ]) None

93) A flip flop is a _______ circuit.

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 A [ ]) Combinational
B [v]) Sequential
C [ ]) Both A and B
D [ ]) None

94) Which of these circuits have higher gate complexity 1. Carry look ahead adder 2. Ripple
carry adder
A [v]) 1
B [ ]) 2
C [ ]) both have same
D [ ]) none

95) Which of these circuits will give yield carry with more delay 1. Carry look ahead adder
2. Ripple carry adder
A [v]) 1
B [ ]) 2
C [ ]) both are same
D [ ]) none

96) Fastest memory element is

A [ ]) RAM
B [ ]) ROM
C [v]) Cache
D [ ]) Hard Drive

97) Slowest memory element is

A [ ]) RAM
B [ ]) ROM
C [ ]) Cache
D [v]) Hard Drive

98) Which of these sets of logic gates are designated as universal gates?
A [v]) NOR, NAND.

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 B [ ]) XOR, NOR, NAND.
C [ ]) OR, NOT, AND.
D [ ]) NOR, NAND, XNOR.

99) The number of comparators in a parallel conversion type 8-bit analog to digital
converter is
A [ ]) 8.
B [ ]) 16.
C [v]) 255.
D [ ]) 256.
E [ ]) HINTS-Number of comparators = ( 2POWER N - 1 ) = ( 2 POWER 8- 1 ) = 255 ( N = no. of
bits ).

100) Excess 3 code is known as

A [ ]) weighted code.
B [ ]) redundancy code.
C [v]) self complementing code.
D [ ]) algebraic code.

101) How many flip flops are required to build a binary counter circuit to count from 0 to
1024?
A [ ]) 6
B [v]) 10
C [ ]) 24
D [ ]) 12
E [ ]) HINTS- Total count = 1024, 2POWER N = 1024 or, 2POWER N = 210 or, N = 10 (no. of flip
flops).

102) In flip flop clock is present but in latch clock is

A [ ]) present always.
B [v]) absent always.
C [ ]) may be present/absent.
D [ ]) none.

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103) Counter is a
A [ ]) combinational circuit.
B [v]) sequential circuit.
C [ ]) both.
D [ ]) none.

104) A 10 bit A/D conveter is used to digitize an analog signal in the 0 to 6 volt. The
maximum peak to ripple voltage that can be allowed in the D.C. supply voltage is
A [ ]) 6 mV.
B [ ]) 5 mV.
C [v]) 5.85 mV.
D [ ]) 10 mV.
E [ ]) HINTS-Smallest incremental change = 1 / 2POWER10 = 1 / 1024. So for 6 Volt incremental
change = 6 / 1024 = 5.85 mV.

105) A switch-tail ring counter is made by using a single D-FF, the following circuit is
A [v]) T FF.
B [ ]) D FF.
C [ ]) S-R FF.
D [ ]) J-K FF.

106) The fast logic family is

A [v]) ECL.
B [ ]) DRL.
C [ ]) TRL.
D [ ]) All

107) Each term in the standard SOP form is called a

A [v]) minterm
B [ ]) maxterm
C [ ]) don’t care
D [ ]) literal

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108) Each term in the standard POS form is called a
A [ ]) minterm
B [v]) maxterm
C [ ]) don’t care
D [ ]) literal

109) The main criterion in the design of a digital circuit is reduction of

A [ ]) cost
B [v]) size
C [ ]) weight
D [ ]) volume

110) The binary number designations of the rows and columns of the K-map are in
A [ ]) binary code
B [ ]) BCD code
C [v]) Gray code
D [ ]) XS-3 code

111) An 8-square eliminates

A [ ]) 2 variables
B [v]) 3 variables
C [ ]) 4 variables
D [ ]) 8 variables
E [ ]) HINTS-Group of 8 cells is called as octet, it will eliminates 3 variables in given expression.
(2POWER 3 = 8)

112) An 8-square is called

A [ ]) a pair
B [ ]) a quad
C [v]) an octet
D [ ]) a cube

113) The terms which cannot be combined further in the tabular method are called

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 A [ ]) implicants
B [ ]) prime implicants
C [v]) essential prime implicants
D [ ]) selective prime implicants

114) The implicants which will definitely occur in the final expression are called
A [ ]) prime implicants
B [v]) essential prime implicants
C [ ]) selective prime implicants
D [ ]) redundent prime implicants

115) he Quine- McClusky method of minimization of a logic expression is a (i) graphical

method (ii) algebraic method (iii) tabular method (iv) a computer-oriented algorithm The
correct answers are
A [v]) (iii) and (iv)
B [ ]) (ii) and (iv)
C [ ]) (i) and (iii)
D [ ]) (i) and (ii)

116) In K-map simplification, a group of four adjacent 1s leads to a term with

A [ ]) one literal less than the total number of variables
B [v]) two literals less than the total number of variables
C [ ]) three literals less than the total number of variables
D [ ]) four literals less than the total number of variables

117) The NAND-NAND realization is equivalent to

A [ ]) AND-NOT realization
B [v]) AND-OR realization
C [ ]) OR-AND realization
D [ ]) NOT-OR realization

118) The NOR-NOR realization is equivalent to

A [ ]) AND-OR realization

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 B [ ]) NOT-AND realization
C [ ]) OR-NOT realization
D [v]) OR-AND realization

119) The voltages corresponding to LOW and HIGH levels respectively are given below.
Identify the voltages which correspond to positive logic system.
A [v]) 0 V and 5 V
B [ ]) -1.5 V and - 5 V
C [ ]) 5 V and 0 V
D [ ]) 1 V and -5 V

120) The voltages corresponding to LOW and HIGH levels respectively are given below.
Identify the voltages which correspond to negative logic system.
A [ ]) 0 V and 5 V
B [ ]) -1.5 V and - 0.5 V
C [v]) 5 V and 0 V
D [ ]) 1 V and 5 V

121) The voltage levels for positive logic system

A [ ]) must necessarily be positive
B [ ]) must necessarily be negative
C [v]) may be positive or negative
D [ ]) must necessarily be 0 V and 5 V

122) In SSI, the number of gate circuits per chip is

A [v]) < 6
B [ ]) < 12
C [ ]) < 20
D [ ]) < 25

123) In MSI, the number of gate circuits per chip is

A [ ]) < 50
B [v]) 12 to 99

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 C [ ]) 50 to 100
D [ ]) < 500

124) In LSI, the number of gate circuits per chip is

A [ ]) 100 to 999
B [v]) 100 to 9,999
C [ ]) 1000 to 10,000
D [ ]) < 10,000

125) In VLSI, the number of gate circuits per chip is

A [ ]) < 10,000
B [ ]) > 10,000
C [v]) 10,000 to 99,999
D [ ]) 50,000 to 99,999

126) In ULSI, the number of gate circuits per chip is

A [ ]) > 50,000
B [ ]) 50,000 to 99,999
C [v]) > 1,00,000
D [ ]) 1,00,000 to 10,00,000

127) A device which converts decimal number into BCD form is called
A [v]) encoder
B [ ]) decoder
C [ ]) code converter
D [ ]) multiplexer

128) A device which converts BCD into octal is called

A [ ]) encoder
B [v]) decoder
C [ ]) code converter
D [ ]) demultiplexer

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129) A multiplexer is a
A [ ]) 1-to-N device
B [v]) N-to-1 device
C [ ]) 1-to-1 device
D [ ]) N-to-N device

130) A demultiplexer is a
A [v]) 1-to-N device
B [ ]) N-to-1 device
C [ ]) 1-to-1 device
D [ ]) N-to-N device

131) A device which converts 2421 code into 8421code is called a

A [v]) code converter
B [ ]) code decoder
C [ ]) code encoder
D [ ]) coder

132) The code used in digital systems to represent decimal digits, letters, and other special
characters such as + , - , . , * , etc. is
A [ ]) hexadecimal
B [ ]) octal
C [ ]) natural BCD
D [v]) ASCII

133) The codes in which each successive code word differs from the preceding one in only
one bit position are called
A [ ]) BCD codes
B [ ]) sequential codes
C [ ]) self-complementing codes
D [v]) cyclic codes

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134) Unit distance code is the other name of
A [ ]) sequential code
B [ ]) self-complementing code
C [v]) cyclic code
D [ ]) XS-3 code
E [ ]) HINTS-In Gray code successive numbers will differ by only one bit. It is also known as unit
distance code or cyclic code or reflective code. It is a unweighted code.

135) (44)8 in BCD 8421 code is

A [ ]) 01000100
B [v]) 00100100
C [ ]) 00110110
D [ ]) 01100011

136) For a code to be self-complementing, the sum of all its weights must be
A [ ]) 6
B [v]) 9
C [ ]) 10
D [ ]) 12
E [ ]) HINTS-Weighted self complimented codes are 2421, 3321, 5211 and 4311. Therfore, the
sum of all its weights must be '9' for a self-complementing code.

137) The following code is not a BCD code.

A [ ]) Gray code
B [v]) XS-3 code
C [ ]) 8421 code
D [ ]) all of these
E [ ]) HINTS-XS-3 code is obtained by adding '0011' to the BCD code. Therefore, XS-3 code is
not a BCD code.

138) The parity of the binary number 11011001 is

A [ ]) even
B [ ]) not known

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 C [v]) odd
D [ ]) same as the number of zeros
E [ ]) HINTS-Parity of a binary number is even parity when the number of 1's present in the
number is even otherwise odd parity. Therefore, the given binary number is a odd parity number.

139) 2-out-of-5 code is

A [ ]) weighted code
B [ ]) self-complementing code
C [ ]) non-weighted code
D [v]) alphanumeric code
E [ ]) HINTS-A two-out-of-five code is an encoding scheme which uses five bits consisting of
exactly three 0s and two 1s. This provides ten possible combinations, enough to represent the
digits 0-9. This scheme can detect all single bit-errors, all odd numbered bit-errors and some even
numbered bit-errors (for example the flipping of both 1-bits). However it still cannot correct for any
of these errors.

140) 8421 code is

A [ ]) self-complementing code
B [v]) weighted code
C [ ]) non-weighted code
D [ ]) alphanumeric code

141) 2421 code is

A [v]) weighted self-complementing code
B [ ]) non-weighted self-complementing code
C [ ]) weighted non-self-complementing code
D [ ]) non-weighted and non-self-complementing code

142) The 7-bit Hamming code is used to transmit

A [ ]) 3 data bits
B [v]) 4 data bits
C [ ]) 7 data bits
D [ ]) no data bits

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143) ASCII and EBCDIC codes are
A [ ]) BCD codes
B [ ]) numeric codes
C [v]) alphanumeric codes
D [ ]) error correcting codes

144) ASCII code is a

A [ ]) 5-bit code
B [v]) 7-bit code
C [ ]) 8-bit code
D [ ]) 10-bit code

145) ASCII
A [ ]) is a subset of 8-bit EBCDIC
B [ ]) is used only in western countries
C [ ]) is version II of the ASC standard
D [v]) has 128 characters including control characters

146) Which of the following is a self-complementing code?

A [v]) XS-3 code
B [ ]) Gray code
C [ ]) Hamming code
D [ ]) cyclic code

147) A combinational circuit can be designed using only

A [ ]) AND gates
B [ ]) OR gates
C [ ]) OR and X-NOR gates
D [v]) NOR gates

148) What is the logic which controls a stair case light associated with two switches A and
B located at the bottom and top of the stair case respectively?
A [ ]) OR

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 B [ ]) AND
C [v]) X-OR
D [ ]) X-NOR

149) An exclusive NOR gate is logically equivalent to

A [ ]) inverter followed by an X-OR gate
B [v]) X-OR gate followed by an inverter
C [ ]) NOT gate followed by a NOR gate
D [ ]) complement of a NOR gate

150) The NAND gate can function as a NOT gate if

A [ ]) all inputs are connected together
B [ ]) inputs are left open
C [ ]) one input is set to 0
D [v]) one input is set to 1

151) The NOR gate can function as a NOT gate if

A [ ]) all inputs are connected together
B [ ]) inputs are left open
C [v]) one input is set to 0
D [ ]) one input is set to 1

152) Which of the following is known as a mod-2 adder?

A [v]) X-OR gate
B [ ]) X-NOR gate
C [ ]) NAND gate
D [ ]) NOR gate
E [ ]) HINTS-The output of mod-2 adder or half adder is A ⊕ B. Therefore, the output is X-OR
gate.

153) Which of the following gates is known as a coincidence detector?

A [ ]) AND gate
B [ ]) NAND gate

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 C [ ]) X-OR gate
D [v]) X-NOR gate

154) Which of the following gates is known as anticoincidence detector?

A [ ]) OR gate
B [v]) X-OR gate
C [ ]) AND gate
D [ ]) X-NOR gate

155) An AND gate can be imagined as

A [v]) switches connected in series
B [ ]) switches connected in parallel
C [ ]) transistors connected in series
D [ ]) transistors connected in paralle

156) An OR gate can be imagined as

A [ ]) switches connected in series
B [v]) switches connected in parallel
C [ ]) transistors connected in series
D [ ]) transistors connected in parallel

157) An all or nothing gate is the other name of

A [v]) AND gate
B [ ]) OR gate
C [ ]) X-OR gate
D [ ]) X-NOR gate
E [ ]) HINTS-AND gate is called an all or nothing gate. Because it produce high only when all its
inputs are high. In all other case its output is low.

158) An any or all gate is the other name of

A [ ]) AND gate
B [v]) OR gate
C [ ]) X-OR gate

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 D [ ]) X-NOR gate
E [ ]) HINTS-OR gate is called an any or all gate. Because it produces high when at least one
input is high and output is low when all inputs are low.

159) The most suitable gate for comparing two bits is

A [ ]) AND
B [ ]) OR
C [ ]) NAND
D [v]) X-OR

160) The number of rows in the truth table of a 4-input gate is

A [ ]) 2
B [ ]) 4
C [ ]) 8
D [v]) 16

161) Which of the following operations is commutative but not associative?

A [ ]) AND
B [ ]) OR
C [ ]) X-OR
D [v]) NAND

162) Which of the following operations is commutative but not associative?

A [ ]) AND
B [v]) NOR
C [ ]) OR
D [ ]) X-OR

163) A 32 × 10 ROM contains a decoder of size

A [v]) 5 × 32
B [ ]) 32 × 32
C [ ]) 32 × 10
D [ ]) 10 × 32

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 E [ ]) HINTS-The size of the decode is N×2 POWER N. Therefore, for given problem size of the
decoder is 5 × 32.

164) he address bus with a ROM of size 1024 × 8 bits is

A [ ]) 8 bits
B [v]) 10 bits
C [ ]) 12 bits
D [ ]) 16 bits
E [ ]) HINTS-The size of the ROM is 1024 × 8 = 2 POWER 10× 8 Here 10 indicate the address
bus. Therefore, the address bus with a ROM of size 1024 × 8 bits is 10 bits.

165) The decimal equivalent of the highest possible address for an 8-bit address bus is
A [ ]) 8
B [ ]) 128
C [v]) 255
D [ ]) 256
E [ ]) HINTS-The decimal equivalent of the highest possible address for an 8-bit address bus is =
2 POWER8 -1 = 255

166) The data bus width of a ROM of size 2048 × 8 bits is

A [v]) 8
B [ ]) 10
C [ ]) 12
D [ ]) 24
E [ ]) HINTS- The size of the ROM is 2048 × 8 = 2POWER 11× 8 Here 11 indicate the address
bus and 8 indicates the data bus width.

167) A read only memory in which the present contents must be erased before the new
information can be stored is
A [ ]) ROM
B [ ]) PROM
C [v]) EAROM
D [ ]) all of the above

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168) The process of entering information in EPROM is commonly known as
A [ ]) writing
B [v]) programming
C [ ]) storing
D [ ]) none of the above

169) When two n-bit binary numbers are added then the sum will contain at most
A [ ]) n-bit
B [v]) (n + 1)-bit
C [ ]) (n + 2)-bit
D [ ]) (n + n)-bit

170) 9’s complement of 52784630 is

A [ ]) 58326479
B [v]) 47215369
C [ ]) 48225469
D [ ]) 57316379

171) If two numbers in excess-3 code are added and the result is less than 9, then to get
equivalent binary
A [v]) 0011 is subtracted
B [ ]) 0011 is added
C [ ]) 0110 is subtracted
D [ ]) 0110 is added
E [ ]) HINTS-Excess-3 codes are derived from BCD code adding 3 with it. So if we want to get
back the equivalent binary from an excess-3 code which is less than 9 we have to subtract 3
(0011) from the code.

172) Which one of the following is an invalid state in 8-4-2-1 binary coded decimal counter
A [ ]) 1000
B [ ]) 1001
C [ ]) 0011
D [v]) 1100

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 E [ ]) HINTS-1100(>9) is the invalid BCD representation.

173) Which is typically the longest: bit,byte,nibble,word?

A [ ]) bit
B [ ]) byte
C [ ]) nibble
D [v]) word

174) What is a shift register that will accept a parallel input, or a bidirectional serial load
and internal shift features, called?
A [ ]) tristate
B [ ]) end around
C [v]) universal
D [ ]) conversion

175) How can parallel data be taken out of a shift register simultaneously?
A [ ]) Use the Q output of the first FF.
B [ ]) Use the Q output of the last FF.
C [ ]) Tie all of the Q outputs together.
D [v]) Use the Q output of each FF.

176) To operate correctly, starting a ring shift counter requires:

A [ ]) clearing all the flip-flops
B [v]) presetting one flip-flop and clearing all others
C [ ]) clearing one flip-flop and presetting all others
D [ ]) presetting all the flip-flops

177) A modulus-12 ring counter requires a minimum of ________.

A [ ]) 10 flip-flops
B [v]) 12 flip-flops
C [ ]) 6 flip-flops
D [ ]) 2 flip-flops

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178) A sequence of equally spaced timing pulses may be easily generated by which type of
counter circuit?
A [v]) ring shift
B [ ]) clock
C [ ]) Johnson
D [ ]) binary

179) A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by
________ position(s) for each clock pulse.
A [v]) right, one
B [ ]) right, two
C [ ]) left, one
D [ ]) left, three

180) How many clock pulses will be required to completely load serially a 5-bit shift
register?
A [ ]) 2
B [ ]) 3
C [ ]) 4
D [v]) 5

181) How is a strobe signal used when serially loading a shift register?
A [ ]) to turn the register on and off
B [v]) to control the number of clocks
C [ ]) to determine which output Qs are used
D [ ]) to determine the FFs that will be used

182) The primary purpose of a three-state buffer is usually:

A [v]) to provide isolation between the input device and the data bus
B [ ]) to provide the sink or source current required by any device connected to its output without
loading down the output device
C [ ]) temporary data storage
D [ ]) to control data flow

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183) What is the difference between a ring shift counter and a Johnson shift counter?
A [ ]) There is no difference.
B [ ]) A ring is fast
C [v]) The feedback is reversed.
D [ ]) The Johnson is faster.

184) By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a
________, ________, and ________-out register.
A [v]) parallel-in, serial, parallel
B [ ]) serial-in, parallel, serial
C [ ]) series-parallel-in, series, parallel
D [ ]) bidirectional in, parallel, series

185) What type of register would have a complete binary number shifted in one bit at a time
and have all the stored bits shifted out one at a time?
A [ ]) parallel-in, parallel-out
B [ ]) parallel-in, serial-out
C [v]) serial-in, parallel-out
D [ ]) serial-in, serial-out

186) Ring shift and Johnson counters are:

A [v]) synchronous counters
B [ ]) aynchronous counters
C [ ]) true binary counters
D [ ]) synchronous and true binary counters

187) Which type of device may be used to interface a parallel data format with external
equipment's serial format?
A [ ]) key matrix
B [v]) UART
C [ ]) memory chip
D [ ]) series in, parallel out

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188) What is the function of a buffer circuit?
A [ ]) to provide an output that is inverted from that on the input
B [v]) to provide an output that is equal to its input
C [ ]) to clean up the input
D [ ]) to clean up the output

189) What is the preset condition for a ring shift counter?

A [ ]) all FFs set to 1
B [ ]) all FFs cleared to 0
C [ ]) a single 0, the rest 1
D [v]) a single 1, the rest 0

190) To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a
________.
A [ ]) divide-by-4 clock pulse
B [ ]) sequence generator
C [v]) strobe line
D [ ]) multiplexer

191) In a 4-bit Johnson counter sequence there are a total of how many states, or bit
patterns?
A [ ]) 1
B [ ]) 2
C [ ]) 4
D [v]) 8

192) How much storage capacity does each stage in a shift register represent?
A [v]) One bit
B [ ]) Two bits
C [ ]) Four bits (one nibble)
D [ ]) Eight bits (one byte)

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193) When the output of a tristate shift register is disabled, the output level is placed in a:
A [ ]) float state
B [ ]) LOW state
C [ ]) high-impedance state
D [v]) float or high-impedance state

194) How many flip-flops are required to make a MOD-32 binary counter?
A [ ]) 3
B [ ]) 45
C [v]) 5
D [ ]) 32

195) A MOD-16 ripple counter is holding the count 1001. What will the count be after 31
clock pulses?
A [v]) 1000
B [ ]) 1010
C [ ]) 1011
D [ ]) 1101

196) The terminal count of a modulus-11 binary counter is ________.

A [v]) 1010
B [ ]) 1000
C [ ]) 1001
D [ ]) none

197) Synchronous construction reduces the delay time of a counter to the delay of:
A [ ]) all flip-flops and gates
B [ ]) all flip-flops and gates after a 3 count
C [ ]) a single gate
D [v]) a single flip-flop and a gate

198) A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the
input clock frequency is 60 MHz.

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 A [v]) 500 kHz
B [ ]) 1,500 kHz
C [ ]) 6 MHz
D [ ]) 5 MHz

199) Which segments of a seven-segment display would be required to be active to display

the decimal digit 2?
A [v]) a, b, d, e, and g
B [ ]) a, b, c, d, and g
C [ ]) a, c, d, f, and g
D [ ]) a, b, c, d, e, and f

200) How many AND gates would be required to completely decode ALL the states of a
MOD-64 counter, and how many inputs must each AND gate have?
A [ ]) 128 gates, 6 inputs to each gate
B [ ]) 64 gates, 5 inputs to each gate
C [v]) 64 gates, 6 inputs to each gate
D [ ]) 128 gates, 5 inputs to each gate

201) A BCD counter is a ________

A [ ]) binary counter
B [ ]) full-modulus counter
C [v]) decade counter
D [ ]) divide-by-10 counter

202) How many flip-flops are required to construct a decade counter?

A [ ]) 10
B [ ]) 8
C [ ]) 5
D [v]) 4

203) Which of the following is an invalid output state for an 8421 BCD counter?
A [v]) 1110

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 B [ ]) 0000
C [ ]) 0010
D [ ]) 0001

204) How many different states does a 3-bit asynchronous counter have?
A [ ]) 2
B [ ]) 4
C [v]) 8
D [ ]) 16

205) A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(tot)) is
A [ ]) 12 ms
B [ ]) 24 ns
C [ ]) 48 ns
D [v]) 60 ns

206) Three cascaded modulus-5 counters have an overall modulus of ________.

A [ ]) 5
B [ ]) 25
C [v]) 125
D [ ]) 500

207) An asynchronous 4-bit binary down counter changes from count 2 to count 3. How
many transitional states are required?
A [ ]) None
B [ ]) One
C [ ]) Two
D [v]) Fifteen

208) A counter with a modulus of 16 acts as a ________.

A [ ]) divide-by-8 counter
B [v]) divide-by-16 counter

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 C [ ]) divide-by-32 counter
D [ ]) divide-by-64 counter

209) A ripple counter's speed is limited by the propagation delay of:

A [v]) each flip-flop
B [ ]) all flip-flops and gates
C [ ]) the flip-flops only with gates
D [ ]) only circuit gates

210) A 4-bit counter has a maximum modulus of ________.

A [ ]) 2
B [ ]) 6
C [ ]) 8
D [v]) 16

211) The parallel outputs of a counter circuit represent the:

A [ ]) parallel data word
B [ ]) clock frequency
C [ ]) counter modulus
D [v]) clock count

212) Which of the following is an example of a counter with a truncated modulus?

A [ ]) 8
B [v]) 13
C [ ]) 16
D [ ]) 32

213) Which of the following is a type of shift register counter?

A [ ]) Decade
B [ ]) Binary
C [v]) Ring
D [ ]) BCD

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214) MOD-6 and MOD-12 counters and multiples are most commonly used as:
A [ ]) frequency counters
B [ ]) multiplexed displays
C [v]) digital clocks
D [ ]) power consumption meters

215) How many different states does a 2-bit asynchronous counter have?
A [ ]) 2
B [ ]) 3
C [v]) 4
D [ ]) 1

216) Which of the following is a type of error associated with digital-to-analog converters
(DACs)?
A [ ]) nonmonotonic error
B [ ]) incorrect output codes
C [ ]) offset error
D [v]) nonmonotonic and offset error

217) A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the
analog output for the input code 0101.
A [ ]) 0.3125 V
B [v]) 3.125 V
C [ ]) 0.78125 V
D [ ]) -3.125 V

218) What is the resolution of a digital-to-analog converter (DAC)?

A [ ]) It is the comparison between the actual output of the converter and its expected output.
B [ ]) It is the deviation between the ideal straight-line output and the actual output of the
converter.
C [v]) It is the smallest analog output change that can occur as a result of an increment in the
digital input

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 D [ ]) It is its ability to resolve between forward and reverse steps when sequenced over its entire
range.

219) The practical use of binary-weighted digital-to-analog converters is limited to:

A [ ]) R/2R ladder D/A converters
B [v]) 4-bit D/A converters
C [ ]) 8-bit D/A converters
D [ ]) op-amp comparators

220) The difference between analog voltage represented by two adjacent digital codes, or
the analog step size, is the:
A [ ]) quantization
B [ ]) accuracy
C [v]) resolution
D [ ]) monotonicity

221) The primary disadvantage of the flash analog-to digital converter (ADC) is that:
A [ ]) it requires the input voltage to be applied to the inputs simultaneously
B [ ]) a long conversion time is required
C [ ]) a large number of output lines is required to simultaneously decode the input voltage
D [v]) a large number of comparators is required to represent a reasonable sized binary number

222) What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared
to a binary-weighted digital-to-analog DAC converter?
A [v]) It only uses two different resistor values.
B [ ]) It has fewer parts for the same number of inputs.
C [ ]) Its operation is much easier to analyze.
D [ ]) The virtual ground is eliminated and the circuit is therefore easier to understand and
troubleshoot

223) The resolution of a 0-5 V 6-bit digital-to-analog converter (DAC) is:

A [ ]) 63%
B [ ]) 64%
C [v]) 1.56%

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 D [ ]) 15.6%

224) In a flash analog-to-digital converter, the output of each comparator is connected to

an input of a:
A [ ]) decoder
B [v]) priority encoder
C [ ]) multiplexer
D [ ]) demultiplexer

225) Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to:
A [ ]) sample and hold the output of the binary counter during the conversion process
B [ ]) stabilize the comparator's threshold voltage during the conversion process
C [v]) stabilize the input analog signal during the conversion process
D [ ]) sample and hold the D/A converter staircase waveform during the conversion process

226) Which is not an analog-to-digital (ADC) conversion error?

A [v]) differential nonlinearity
B [ ]) missing code
C [ ]) incorrect code
D [ ]) offset

227) What is one advantage to using a parallel-encoded (flash) ADC?

A [ ]) less expensive
B [v]) very fast conversion
C [ ]) less complicated circuit
D [ ]) none

228) What is the disadvantage to using a counter-ramp type ADC?

A [ ]) complex circuit
B [ ]) high cost
C [v]) very slow
D [ ]) none

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229) A simultaneous A/D converter is also known as a(n) ________ A/D converter.
A [v]) flash
B [ ]) synchronous
C [ ]) comparator
D [ ]) asynchronous

230) The main advantage of the successive-approximation A/D converter over the counter-
ramp A/D converter is its:
A [ ]) more complex circuitry
B [ ]) less complex circuitry
C [ ]) longer conversion time
D [v]) shorter conversion time

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