Electronics I Fall 2018 - Final Project

Due December 7, 2018

Your task is to design and simulate a multi-stage BJT amplifier to drive a speaker at 10 W of RMS
power. The signal source is sinusoidal, oscillating at 1 kHz with a peak voltage of 5 mV and an
output resistance of 100 Ω. The load is a speaker which can be modeled as a 4 Ω resistor. For the
BJT transistors, use the 2N5210 for the common emitter amplifier stages and the ZTX849 and
D45H11 for the Darlington pairs of the Class AB push-pull amplifier NPN and PNP BJTs,
respectively. Both of the aforementioned BJT parts can be found in the LTSpice library. The overall
circuit is shown below.

The overall circuit is formed by three separate discrete amplifiers: a first stage common emitter
amplifier, a second stage common emitter amplifier with Re, and a third stage class AB push-pull
amplifier. The first stage should provide the majority of the voltage gain. The second stage provides
additional gain as well as Re for gain adjustment. A push-pull amplifier provides the impedance
transformation such that the low resistance load can be driven with sufficient current. The
Darlington pair for the NPN transistor in the push-pull amplifier is necessary for current gain. Low
pass filter (LPF) and high pass filter (HPF) stages are included such that the mid-band gain falls
between a lower cutoff and higher cutoff frequency, respectively.
Your task is to determine the biasing component values for each of the stages. For the first stage
these are RB1_1, RB1_2, RC1. For the second stage these are RE1, RB2_1, RB2_2, RC2, and RE2. For
the push-pull amplifier these are R1, R2, R3, and R4. Finally, for the filters these are C_LPF, C_HPF,
and R_HPF. Your goal is to deliver an undistorted sinusoidal waveform to the load at an RMS power
level of at least 10 W.

Deliverables

Calculations:

For each of the 3 separate stages calculate the biasing resistors, input resistance, output resistance,
and gain. Indicate that the calculations use the Rules of Thumb discussed in class. The bias current,
IE, for the first 2 stages should be around 10 mA. The bias current for the push-pull amplifier should
be around 7 A.

Show your work using equation editor in Word. Alternatively, you could use a math software
program such as Mathcad or Maple.

Simulation results:

For a 1 kHz, 5 mV input signal provide transient simulation results for a period of 10 msec plotting:

signal voltage vsig

output voltage vout

Your output voltage waveform should be only slightly distorted (nearly a perfect sinusoid). If it is
not, then your biasing values and gains must be changed. A method to check for distortion is to plot
the FFT of the output signal looking for the amplitude of harmonics of the fundamental 1 kHz
frequency. The larger the amplitude of the harmonics the larger the distortion.
Also, provide simulation results of an AC sweep from 1 Hz to 1 MHz on a log-log scale of the output
voltage, vO. Choose C_LPF must be chosen for a lower cutoff frequency of 20 Hz. Choose C_HPF and
R_HPF must be chosen for an upper cutoff frequency of 20 kHz.

Discussion and Analysis:

Discussion topics should include (but are not limited to):

• Possible causes of the differences between your calculated overall voltage gain (from your
calculations) and the actual overall voltage gain (from the simulation)
• The role of Re_2 plays in the overall design
• Frequency response of the overall amplifier

Submission:

Submit your report on blackboard by 5:00PM on December 7, 2018. The report should be a Word
document that contains your calculations, simulation (schematics and waveforms), and
discussion/analysis. Additionally, submit your LT Spice (.asc) files appropriately named.

Grading

Projects will be graded from 0 to 100 on three primary criteria based on the performance of your
design (calculation and simulation results), quality of the discussion and analysis, and clarity of the
report (quality of figures, grammar, etc…).