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Colour Television Chassis

Q552.1E
LA

18770_000_100210.eps
100210

Contents Page Contents Page


1. Revision List 2 B06 820400089962 LVDS DVBS 138
2. Technical Specifications, Diversity, and Connections2 B06 820400089572 LVDS Non DVBS 142
3. Precautions, Notes, and Abbreviation List 6 B07 820400089602 DVBS FE 146
4. Mechanical Instructions 10 B08 820400089624 DVBS Supply 147
5. Service Modes, Error Codes, and Fault Finding 23 B09 820400089822 DVBS Con. 149
6. Alignments 41 B09 820400089812 Non DVBS Con. 150
7. Circuit Descriptions 47 B11 820400090693 TCON LGD 151
8. IC Data Sheets 60 B11 820400090704 TCON LGD 155
9. Block Diagrams B13 820400090732 TCON AL CPLD 159
Wiring diagram Rembrandt 32" 77 B13 820400090742 TCON AL CPLD 160
Wiring diagram Rembrandt 37" - 42" 78 B14 820400090714 TCON SHARP 161
Wiring diagram Van Gogh 32" - 40" 79 B14 820400090724 TCON SHARP 167
Wiring diagram Matisse 32" 80 310431363643 SSB Layout 173
Wiring Matisse 40" 81 310431364003 SSB Layout 175
Block Diagram Video 82 310431364025 SSB Layout 177
Block Diagram Audio 83 310431364064 SSB Layout 179
Block Diagram Control & Clock Signals 84 11. Styling Sheets
Block Diagram I2C 85 Rembrandt 32" 181
Supply Lines Overview 86 Rembrandt 37" & 42" 182
10. Circuit Diagrams and PWB Layouts Drawing PWB Van Gogh 32" - 52" 183
AL1 820400089786 AmbiLight Common 87 94 Matisse 32" - 46" 184
AL2 820400089773 3 LED LiteOn 89 94
AL1 820400089691 9 LED LiteOn 90 94
AL1 820400089703 15 LED LiteOn 92 94
AL1 820400090592 AmbiLight Common 95 102
AL1 820400090611 3 LED Everlight 97 102
AL1 820400090601 9 LED Everlight 98 102
AL1 820400090621 15 LED Everlight 100 102
B01 820400089943 Tuner, HDMI & CI 103
B02 820400089506 PNX85500 114
B03 820400089514 CLASS D 123
B04 820400089524 Analog I/O 131
B05 820400089832 DDR 136
B05 820400089535 DDR 137

©
Copyright 2010 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.

Published by ER/TY 1062 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18770
2010-Feb-19
EN 2 1. Q552.1E LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0
• First release.

2. Technical Specifications, Diversity, and Connections


Index of this chapter: 2.1 Technical Specifications
2.1 Technical Specifications
2.2 Directions for Use
For on-line product support please use the links in Table 2-1.
2.3 Connections Here is product information available, as well as getting started,
2.4 Chassis Overview
user manuals, frequently asked questions and software &
drivers.
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).

Table 2-1 Described Model numbers and diversity

SSB 2 4 7 9 10
Conn Mechanics Descriptions Wng Schematics
ALxx (Ambilight) Everlight
ALxx (Ambilight) LiteOn

B06 (non-DVBS-LVDS)

B09 (non-DVBS-conn.)
B03 (DC/DC / Class D)

B08 (DVBS-Supp.)

B11 (TCON-LGD)

B14 (TCON-SHP)
Layout Everlight

B02 (PNX85500)

B13 (Ambilight)
B07 (DVBS-FE)
Layout LiteOn

B01 (Tuner)
AmbiLight

B05 (DDR)
Assembly
Removal

Removal
3104 313

B04 (I/O)
Diagram
Layout

TCON
Tuner

Styling
Wire

LCD

PSU

CTN styling sh.


32PFL5405H/05 Rembrandt 64025 10-31 2.3 4-1 4.5 4.5.9 7.2 7.4.1 - 7.10 9-1 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-1 11 12 13 14 15
32PFL5405H/12 Rembrandt 64025 10-31 2.3 4-1 4.5 4.5.9 7.2 7.4.1 - 7.10 9-1 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-1 11 12 13 14 15
32PFL5405H/60 Rembrandt 64025 10-31 2.3 4-1 4.5 4.5.9 7.2 7.4.1 - 7.10 9-1 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-1 11 12 13 14 15
32PFL5605H/05 van Gogh 64003 10-30 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - - - 10- 10- 10- 10- 10- - - - - - 10-25 10-27
11-3 11 12 13 14 15
32PFL5605H/12 van Gogh 64003 10-30 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - - - 10- 10- 10- 10- 10- - - - - - 10-25 10-27
11-3 11 12 13 14 15
32PFL5605H/60 van Gogh 64003 10-30 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - - - 10- 10- 10- 10- 10- - - - - - 10-25 10-27
11-3 11 12 13 14 15
32PFL7605H/05 Matisse 64064 10-32 2.3 4-7 4.7 4.6.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-5 10-6 10- 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-4 10-2 10-7 10 11 12 13 14 16
32PFL7605H/12 Matisse 64064 10-32 2.3 4-7 4.7 4.6.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-5 10-6 10- 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-4 10-2 10-7 10 11 12 13 14 16
37PFL5405H/05 Rembrandt 64025 10-31 2.3 4-2 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-2 11 12 13 14 15
37PFL5405H/12 Rembrandt 64025 10-31 2.3 4-2 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-2 11 12 13 14 15
40PFL5605H/05 van Gogh 64003 10-30 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - - - 10- 10- 10- 10- 10- - - - - - 10-25 10-27
11-3 11 12 13 14 15
40PFL5605H/12 van Gogh 64003 10-30 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - - - 10- 10- 10- 10- 10- - - - - - 10-25 10-27
11-3 11 12 13 14 15
40PFL5605H/60 van Gogh 64003 10-30 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - - - 10- 10- 10- 10- 10- - - - - - 10-25 10-27
11-3 11 12 13 14 15
40PFL7605H/05 Matisse 63643 10-29 2.3 4-8 4.7 4.6.8 7.2 7.4.1 7.9 7.10 9-5 10-1 10-5 10-6 10- 10- 10- 10- 10- 10- 10-18 - - 10-22 - - -
11-4 10-3 10-8 10 11 12 13 14 16
40PFL7605H/12 Matisse 63643 10-29 2.3 4-8 4.7 4.6.8 7.2 7.4.1 7.9 7.10 9-5 10-1 10-5 10-6 10- 10- 10- 10- 10- 10- 10-18 - - 10-22 - - -
11-4 10-3 10-8 10 11 12 13 14 16
42PFL5405H/05 Rembrandt 64025 10-31 2.3 4-3 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-2 11 12 13 14 15
42PFL5405H/12 Rembrandt 64025 10-31 2.3 4-3 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-2 11 12 13 14 15
42PFL5405H/60 Rembrandt 64025 10-31 2.3 4-3 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - - - 10- 10- 10- 10- 10- - - - - 10-23 10-25 -
11-2 11 12 13 14 15

2.2 Directions for Use

You can download this information from the following websites:


http://www.philips.com/support
http://www.p4c.philips.com

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Technical Specifications, Diversity, and Connections Q552.1E LA 2. EN 3

2.3 Connections

5 6 7 8 9

10 11 12 12 13 14 15 16

18770_001_100210.eps
100210

Figure 2-1 Connection overview

Note: The following connector colour abbreviations are used 4 - Vdd Supply k
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= 5 - CLOCK Signal k
Grey, Rd= Red, Wh= White, Ye= Yellow. 6 - GND2 Gnd H
7 - DAT0/D0 Signal jk
2.3.1 Side Connections 8 - DAT1/IRQ Signal jk
9 - DAT2/NC Signal jk
10 - CD Signal j
1 - SD-Card: Secure Digital Card - In/Out (optional)
11 - GND Gnd H
14
GND 12 - WP Signal j
13 - GND Gnd H
WP 12
14 - GND Gnd H
GND 11
CD 10
8 DAT1/IRQ
2 - Common Interface
68p - See diagram B01F HDMI & CI jk
7 DAT0/D0
6 GND2
5 CLOCK
3 - USB2.0
4 VDD
3 GND1 1 2 3 4
2 CMD/DI 10000_022_090121.eps
1 DAT3/CS 090121

9 DAT2/NC
Figure 2-3 USB (type A)
GND
13
10000_049_100210.eps 1 - +5V k
100210
2 - Data (-) jk
Figure 2-2 SD-Card connector 3 - Data (+) jk
4 - Ground Gnd H
1 - DAT3/CS Signal jk
2 - CMD/DI Signal k
3 - GND1 Gnd H

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EN 4 2. Q552.1E LA Technical Specifications, Diversity, and Connections

4 - HDMI: Digital Video, Digital Audio - In 14 - Ground P50 Gnd H


15 - Video Red 0.7 VPP / 75 ohm j
19 1
18 2 16 - Status/FBL 0 - 0.4 V: INT
10000_017_090121.eps
1 - 3 V: EXT / 75 ohm j
090428 17 - Ground Video Gnd H
18 - Ground FBL Gnd H
Figure 2-4 HDMI (type A) connector 19 - Video CVBS/Y 1 VPP / 75 ohm k
20 - Video CVBS 1 VPP / 75 ohm j
1 - D2+ Data channel j 21 - Shield Gnd H
2 - Shield Gnd H
3 - D2- Data channel j 7 - Service Connector (UART)
4 - D1+ Data channel j 1 - Ground Gnd H
5 - Shield Gnd H 2 - UART_TX Transmit k
6 - D1- Data channel j 3 - UART_RX Receive j
7 - D0+ Data channel j
8 - Shield Gnd H 8 - EXT3: Cinch: Video YPbPr - In, Audio - In
9 - D0- Data channel j Gn - Video Y 1 VPP / 75 ohm jq
10 - CLK+ Data channel j Bu - Video Pb 0.7 VPP / 75 ohm jq
11 - Shield Gnd H Rd - Video Pr 0.7 VPP / 75 ohm jq
12 - CLK- Data channel j Rd - Audio - R 0.5 VRMS / 10 kohm jq
13 - Easylink/CEC Control channel jk Wh - Audio - L 0.5 VRMS / 10 kohm jq
14 - n.c.
15 - DDC_SCL DDC clock j
9 - Head phone (Output)
16 - DDC_SDA DDC data jk
Bk - Head phone 32 - 600 ohm / 10 mW ot
17 - Ground Gnd H
18 - +5V j
19 - HPD Hot Plug Detect j 2.3.3 Rear Connections - Bottom
20 - Ground Gnd H
10 - EXT1: Video RGB - In, CVBS - In/Out, Audio - In/Out
2.3.2 Rear Connections See 6 - EXT2: Video RGB - In, CVBS - In/Out, Audio - In/Out

5 - RJ45: Ethernet (optional) 11 - Cinch: S/PDIF - Out


Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq
12345678
12 - HDMI 2 (& 3 optional): Digital Video, Digital Audio - In
See 4 - HDMI: Digital Video, Digital Audio - In
10000_025_090121.eps
090121 13 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/
Out
Figure 2-5 Ethernet connector
19 1
18 2
1 - TD+ Transmit signal k
10000_017_090121.eps
2 - TD- Transmit signal k 090428
3 - RD+ Receive signal j
4 - CT Centre Tap: DC level fixation Figure 2-7 HDMI (type A) connector
5 - CT Centre Tap: DC level fixation
6 - RD- Receive signal j 1 - D2+ Data channel j
7 - GND Gnd H 2 - Shield Gnd H
8 - GND Gnd H 3 - D2- Data channel j
4 - D1+ Data channel j
6 - EXT2: Video RGB - In, CVBS - In/Out, Audio - In/Out 5 - Shield Gnd H
20 2 6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
21 1 9 - D0- Data channel j
10000_001_090121.eps
090121 10 - CLK+ Data channel j
11 - Shield Gnd H
Figure 2-6 SCART connector 12 - CLK- Data channel j
13 - Easylink/CEC Control channel jk
1 - Audio R 0.5 VRMS / 1 kohm k 14 - ARC Audio Return Channel k
2 - Audio R 0.5 VRMS / 10 kohm j 15 - DDC_SCL DDC clock j
3 - Audio L 0.5 VRMS / 1 kohm k 16 - DDC_SDA DDC data jk
4 - Ground Audio Gnd H 17 - Ground Gnd H
5 - Ground Blue Gnd H 18 - +5V j
6 - Audio L 0.5 VRMS / 10 kohm j 19 - HPD Hot Plug Detect j
7 - Video Blue 0.7 VPP / 75 ohm jk 20 - Ground Gnd H
8 - Function Select 0 - 2 V: INT
4.5 - 7 V: EXT 16:9 14 - Cinch: Audio - In (VGA/DVI)
9.5 - 12 V: EXT 4:3 j Rd - Audio R 0.5 VRMS / 10 kohm jq
9 - Ground Green Gnd H Wh - Audio L 0.5 VRMS / 10 kohm jq
10 - n.c.
11 - Video Green 0.7 VPP / 75 ohm j
15 - Aerial - In
12 - n.c.
- - IEC-type (EU) Coax, 75 ohm D
13 - Ground Red Gnd H

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Technical Specifications, Diversity, and Connections Q552.1E LA 2. EN 5

16 - VGA: Video RGB - In


1 5
10
6
11 15

10000_002_090121.eps
090127

Figure 2-8 VGA Connector

1 - Video Red 0.7 VPP / 75 ohm j


2 - Video Green 0.7 VPP / 75 ohm j
3 - Video Blue 0.7 VPP / 75 ohm j
4 - n.c.
5 - Ground Gnd H
6 - Ground Red Gnd H
7 - Ground Green Gnd H
8 - Ground Blue Gnd H
9 - +5VDC +5 V j
10 - Ground Sync Gnd H
11 - n.c.
12 - DDC_SDA DDC data j
13 - H-sync 0-5V j
14 - V-sync 0-5V j
15 - DDC_SCL DDC clock j

2.4 Chassis Overview

Refer to chapter Block Diagrams for PWB/CBA locations.

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EN 6 3. Q552.1E LA Precautions, Notes, and Abbreviation List

3. Precautions, Notes, and Abbreviation List


Index of this chapter: picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
3.1 Safety Instructions NTSC (channel 3).
3.2 Warnings • Where necessary, measure the waveforms and voltages
3.3 Notes with (D) and without (E) aerial signal. Measure the
3.4 Abbreviation List voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
3.1 Safety Instructions
3.3.2 Schematic Notes
Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation
• All resistor values are in ohms, and the value multiplier is
transformer (> 800 VA).
often used to indicate the decimal point location (e.g. 2K2
• Replace safety components, indicated by the symbol h,
indicates 2.2 kΩ).
only by components identical to the original ones. Any
• Resistor values with no multiplier may be indicated with
other component substitution (other than original type) may
either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
increase risk of fire or electrical shock hazard. Of de set
• All capacitor values are given in micro-farads (μ = × 10-6),
ontploft!
nano-farads (n = × 10-9), or pico-farads (p = × 10-12).
• Capacitor values may also use the value multiplier as the
Safety regulations require that after a repair, the set must be
decimal point indication (e.g. 2p2 indicates 2.2 pF).
returned in its original condition. Pay in particular attention to
• An “asterisk” (*) indicates component usage varies. Refer
the following points:
to the diversity tables for the correct values.
• Route the wire trees correctly and fix them with the
• The correct component values are listed on the Philips
mounted cable clamps.
Spare Parts Web Portal.
• Check the insulation of the Mains/AC Power lead for
external damage.
• Check the strain relief of the Mains/AC Power cord for 3.3.3 Spare Parts
proper function.
• Check the electrical DC resistance between the Mains/AC For the latest spare part overview, consult your Philips Spare
Power plug and the secondary side (only for sets that have Part web portal.
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire 3.3.4 BGA (Ball Grid Array) ICs
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position Introduction
(keep the Mains/AC Power cord unplugged!). For more information on how to handle BGA devices, visit this
3. Measure the resistance value between the pins of the URL: http://www.atyourservice-magazine.com. Select
Mains/AC Power plug and the metal shielding of the “Magazine”, then go to “Repair downloads”. Here you will find
tuner or the aerial connection on the set. The reading Information on how to deal with BGA-ICs.
should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the
BGA Temperature Profiles
two pins of the Mains/AC Power plug.
For BGA-ICs, you must use the correct temperature-profile.
• Check the cabinet for defects, to prevent touching of any
Where applicable and available, this profile is added to the IC
inner parts by the customer.
Data Sheet information section in this manual.

3.2 Warnings 3.3.5 Lead-free Soldering

• All ICs and many other semiconductors are susceptible to Due to lead-free technology some rules have to be respected
electrostatic discharges (ESD w). Careless handling by the workshop during a repair:
during repair can reduce life drastically. Make sure that, • Use only lead-free soldering tin. If lead-free solder paste is
during repair, you are connected with the same potential as required, please contact the manufacturer of your soldering
the mass of the set by a wristband with resistance. Keep equipment. In general, use of solder paste within
components and tools also at this same potential. workshops should be avoided because paste is not easy to
• Be careful during measurements in the high voltage store and to handle.
section. • Use only adequate solder tools applicable for lead-free
• Never replace modules or other components while the unit soldering tin. The solder tool must be able:
is switched “on”. – To reach a solder-tip temperature of at least 400°C.
• When you align the set, use plastic rather than metal tools. – To stabilize the adjusted temperature at the solder-tip.
This will prevent any short circuits and the danger of a – To exchange solder-tips for different applications.
circuit becoming unstable. • Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
3.3 Notes Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
3.3.1 General To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Measure the voltages and waveforms with regard to the • Mix of lead-free soldering tin/parts with leaded soldering
chassis (= tuner) ground (H), or hot ground (I), depending tin/parts is possible but PHILIPS recommends strongly to
on the tested area of circuitry. The voltages and waveforms avoid mixed regimes. If this cannot be avoided, carefully
shown in the diagrams are indicative. Measure them in the clear the solder-joint from old tin and re-solder with new tin.
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and

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Precautions, Notes, and Abbreviation List Q552.1E LA 3. EN 7

3.3.6 Alternative BOM identification 3.4 Abbreviation List

It should be noted that on the European Service website, 0/6/12 SCART switch control signal on A/V
“Alternative BOM” is referred to as “Design variant”. board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
The third digit in the serial number (example: format
AG2B0335000001) indicates the number of the alternative AARA Automatic Aspect Ratio Adaptation:
B.O.M. (Bill Of Materials) that has been used for producing the algorithm that adapts aspect ratio to
specific TV set. In general, it is possible that the same TV remove horizontal black bars; keeps
model on the market is produced with e.g. two different types the original aspect ratio
of displays, coming from two different suppliers. This will then ACI Automatic Channel Installation:
result in sets which have the same CTN (Commercial Type algorithm that installs TV channels
Number; e.g. 28PW9515/12) but which have a different B.O.M. directly from a cable network by
number. means of a predefined TXT page
By looking at the third digit of the serial number, one can ADC Analogue to Digital Converter
identify which B.O.M. is used for the TV set he is working with. AFC Automatic Frequency Control: control
If the third digit of the serial number contains the number “1” signal used to tune to the correct
(example: AG1B033500001), then the TV set has been frequency
manufactured according to B.O.M. number 1. If the third digit is AGC Automatic Gain Control: algorithm that
a “2” (example: AG2B0335000001), then the set has been controls the video input of the feature
produced according to B.O.M. no. 2. This is important for box
ordering the correct spare parts! AM Amplitude Modulation
For the third digit, the numbers 1...9 and the characters A...Z AP Asia Pacific
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be AR Aspect Ratio: 4 by 3 or 16 by 9
indicated by the third digit of the serial number. ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
Identification: The bottom line of a type plate gives a 14-digit bars without discarding video
serial number. Digits 1 and 2 refer to the production centre (e.g. information
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers ATSC Advanced Television Systems
to the Service version change code, digits 5 and 6 refer to the Committee, the digital TV standard in
production year, and digits 7 and 8 refer to production week (in the USA
example below it is 2006 week 17). The 6 last digits contain the ATV See Auto TV
serial number. Auto TV A hardware and software control
system that measures picture content,
MADE IN BELGIUM
and adapts image parameters in a
MODEL : 32PF9968/10
220-240V ~ 50/60Hz dynamic way
128W AV External Audio Video
PROD.NO: AG 1A0617 000001 VHF+S+H+UHF AVC Audio Video Controller
S BJ3.0E LA AVIP
B/G
Audio Video Input Processor
Monochrome TV system. Sound
10000_024_090121.eps carrier distance is 5.5 MHz
100105 BDS Business Display Solutions (iTV)
BLR Board-Level Repair
Figure 3-1 Serial number (example) BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
3.3.7 Board Level Repair (BLR) or Component Level Repair system, originating from the USA and
(CLR) used e.g. in LATAM and AP-NTSC
countries
If a board is defective, consult your repair procedure to decide B-TXT Blue TeleteXT
if the board has to be exchanged or if it should be repaired on C Centre channel (audio)
component level. CEC Consumer Electronics Control bus:
If your repair procedure says the board should be exchanged remote control bus on HDMI
completely, do not solder on the defective board. Otherwise, it connections
cannot be returned to the O.E.M. supplier for back charging! CL Constant Level: audio output to
connect with an external amplifier
CLR Component Level Repair
3.3.8 Practical Service Precautions
ComPair Computer aided rePair
CP Connected Planet / Copy Protection
• It makes sense to avoid exposure to electrical shock. CSM Customer Service Mode
While some sources are expected to have a possible CTI Color Transient Improvement:
dangerous impact, others of quite high potential are of manipulates steepness of chroma
limited current and are sometimes held in less regard. transients
• Always respect voltages. While some may not be CVBS Composite Video Blanking and
dangerous in themselves, they can cause unexpected Synchronization
reactions that are best avoided. Before reaching into a DAC Digital to Analogue Converter
powered TV set, it is best to test the high voltage insulation. DBE Dynamic Bass Enhancement: extra
It is easy to do, and is a good service precaution. low frequency amplification
DCM Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
DDC See “E-DDC”
D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion

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EN 8 3. Q552.1E LA Precautions, Notes, and Abbreviation List

DFU Directions For Use: owner's manual SDI), is a digitized video format used
DMR Digital Media Reader: card reader for broadcast grade video.
DMSD Digital Multi Standard Decoding Uncompressed digital component or
DNM Digital Natural Motion digital composite signals can be used.
DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,
reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote ITV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (color
Telecommunication Union relating to carrier= 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (color carrier PAL M=

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Precautions, Notes, and Abbreviation List Q552.1E LA 3. EN 9

3.575612 MHz and PAL N= 3.582056 SVHS Super Video Home System
MHz) SW Software
PCB Printed Circuit Board (same as “PWB”) SWAN Spatial temporal Weighted Averaging
PCM Pulse Code Modulation Noise reduction
PDP Plasma Display Panel SXGA 1280 × 1024
PFC Power Factor Corrector (or Pre- TFT Thin Film Transistor
conditioner) THD Total Harmonic Distortion
PIP Picture In Picture TMDS Transmission Minimized Differential
PLL Phase Locked Loop. Used for e.g. Signalling
FST tuning systems. The customer TS Transport Stream
can give directly the desired frequency TXT TeleteXT
POD Point Of Deployment: a removable TXT-DW Dual Window with TeleteXT
CAM module, implementing the CA UI User Interface
system for a host (e.g. a TV-set) uP Microprocessor
POR Power On Reset, signal to reset the uP UXGA 1600 × 1200 (4:3)
PSDL Power Supply for Direct view LED V V-sync to the module
backlight with 2D-dimming VESA Video Electronics Standards
PSL Power Supply with integrated LED Association
drivers VGA 640 × 480 (4:3)
PSLS Power Supply with integrated LED VL Variable Level out: processed audio
drivers with added Scanning output toward external amplifier
functionality VSB Vestigial Side Band; modulation
PTC Positive Temperature Coefficient, method
non-linear resistor WYSIWYR What You See Is What You Record:
PWB Printed Wiring Board (same as “PCB”) record selection that follows main
PWM Pulse Width Modulation picture and sound
QRC Quasi Resonant Converter WXGA 1280 × 768 (15:9)
QTNR Quality Temporal Noise Reduction XTAL Quartz crystal
QVCP Quality Video Composition Processor XGA 1024 × 768 (4:3)
RAM Random Access Memory Y Luminance signal
RGB Red, Green, and Blue. The primary Y/C Luminance (Y) and Chrominance (C)
color signals for TV. By mixing levels signal
of R, G, and B, all colors (Y/C) are YPbPr Component video. Luminance and
reproduced. scaled color difference signals (B-Y
RC Remote Control and R-Y)
RC5 / RC6 Signal protocol from the remote YUV Component video
control receiver
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 × 600 (4:3)

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EN 10 4. Q552.1E LA Mechanical Instructions

4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing Rembrandt series • Figures below can deviate slightly from the actual situation,
4.2 Cable Dressing Van Gogh styling due to the different set executions.
4.3 Cable Dressing Matisse styling
4.4 Service Positions
4.5 Assy/Panel Removal Rembrandt Styling
4.6 Assy/Panel Removal Van Gogh Styling
4.7 Assy/Panel Removal Matisse Styling
4.8 Set Re-assembly

4.1 Cable Dressing Rembrandt series

18770_100_100211.eps
100211

Figure 4-1 Cable dressing 32PFL5405H/xx

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Mechanical Instructions Q552.1E LA 4. EN 11

18770_101_100211.eps
100216

Figure 4-2 Cable dressing 37PFL5405H/xx

18770_102_100211.eps
100211

Figure 4-3 Cable dressing 42PFL5405H/xx

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EN 12 4. Q552.1E LA Mechanical Instructions

4.2 Cable Dressing Van Gogh styling

18770_103_100211.eps
100211

Figure 4-4 Cable dressing 32PFL5605H/xx

18770_105_100211.eps
100216

Figure 4-5 Cable dressing 40PFL5605H/xx without DVB-S

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Mechanical Instructions Q552.1E LA 4. EN 13

18770_104_100211.eps
100211

Figure 4-6 Cable dressing 40PFL5605H/xx with DVB-S

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EN 14 4. Q552.1E LA Mechanical Instructions

4.3 Cable Dressing Matisse styling

18770_106_100211.eps
100211

Figure 4-7 Cable dressing 32PFL7605H/xx

18770_107_100211.eps
100211

Figure 4-8 Cable dressing 40PFL7605H/xx

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Mechanical Instructions Q552.1E LA 4. EN 15

4.4 Service Positions The stand and -subframe do not need to be removed for
removing the central subwoofer.
For easy servicing of a TV set, the set should be put face down When defective, replace the whole unit.
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform 4.5.3 Mains Switch
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the The mains switch is mounted on the front bezel with one screw.
display. Caution: Failure to follow these guidelines can
seriously damage the display! 4.5.4 Main Power Supply
Ensure that ESD safe measures are taken.
Refer to Figure 4-10 and Figure 4-11 for details.
4.5 Assy/Panel Removal Rembrandt Styling
2
The instructions apply to the 42PFL5405H/xx. 2 2
1
4.5.1 Rear Cover
1
With the Rembrandt styling, a new concept of housing has
been introduced, having consequences for Service when
opening the set. 2 2

Part of the “back cover” now forms one assy with the LCD panel
and will be swapped together with this panel. For opening the 2 2
set, only remove the “smaller” part of the rear cover as 2 1
described below!
18770_122_100212.eps
100216
Warning!
The snaps on the backside of the LCD Panel secure the Figure 4-10 Main Power Supply
backlight units and should never be released! Release
destroys the LCD Panel and voids warranty.
Refer to Figure 4-18 for details.

Warning: Disconnect the mains power cord before you remove


the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.
Refer to Figure 4-9 for details.

18770_123_100215.eps
100215

Figure 4-11 Main Power Supply - back shielding

1. Unplug all connectors [1].


18770_120_100212.eps 2. Remove the fixation screws [2].
100216
3. Take the board out.
When defective, replace the whole unit.
Figure 4-9 Rear cover
When remounting, ensure that the back shielding plate is
positioned correctly.
1. Remove all screws of the rear cover; the part to be
removed [1] is indicated on Figure 4-9.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.

4.5.2 Speakers

Tweeters
Each tweeter unit is mounted with one screw.
When defective, replace the whole unit.

Subwoofer
The central subwoofer is located in the centre of the set, behind
the stand and the -subframe, and is secured by two bosses.

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EN 16 4. Q552.1E LA Mechanical Instructions

4.5.5 Small Signal Board (SSB)

Refer to Figure 4-12 and Figure 4-13 for details.

3
3
3
3
2 3
1

3 3
18770_125_100215.eps
100215

Figure 4-13 SSB - back shielding


18770_124_100215.eps
100217
1. Unplug all connectors [1] and [2].
Figure 4-12 SSB 2. Remove the fixation screws [3].
3. Take the board out.
When defective, replace the whole unit.
When remounting, ensure that the back shielding plate is
positioned correctly.

4.5.6 Front Bezel

Refer to Figure 4-14 for details.

3 3
3 3 3 3

3 3

3 3

2 2
1

3 2 3

18770_126_100215.eps
100215

Figure 4-14 Front Bezel

1. Remove the mains switch as earlier described [1]. 4.5.7 IR & LED Board
2. Remove the clamps [2].
3. Remove the screws [3]. Refer to Figure 4-15 for details.
The front bezel will now be detached from the set, together with
the IR & LED- and Keyboard Control Panel.

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Mechanical Instructions Q552.1E LA 4. EN 17

4.5.9 LCD Panel

Refer to Figure 4-17 and Figure 4-18 for details.


1

3 3

18770_127_100215.eps
100215

Figure 4-15 IR & LED board 3 3

1. Detach the front bezel from the set as earlier described. 2 2


2. Release the clips [1] that secure the IR & LED board in the
bezel and take the board out.
2 2
3. Unplug the connectors.
When defective, replace the whole unit. 18770_128_100215.eps
100215
4.5.8 Keyboard Control Board
Figure 4-17 LCD board -1-
Refer to Figure 4-16 for details.

1 2

18850_104_100203.eps
100203

Figure 4-16 Keyboard Control board

1. Detach the front bezel from the set as earlier described.


2. Unplug the connector [1].
3. Release the clips that secure the board [2] and take the
board out.
When defective, replace the whole unit.

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EN 18 4. Q552.1E LA Mechanical Instructions

Do not release

18770_121_100212.eps
100212

Figure 4-18 LCD board -2-

Warning!
The snaps on the backside of the LCD Panel secure the
backlight units and should never be released!
1. Remove the tweeters as earlier described.
2. Remove the central subwoofer as earlier described.
3. Remove the mains switch as earlier described.
4. Remove the Main Power Supply board as earlier
described, together with its back shielding.
5. Remove the Small Signal Board as earlier described,
together with its back shielding.
6. Remove the cable from the clamp [1].
7. Remove the stand [2] together with its subframe [3].
8. Detach the front bezel together with the IR & LED board
and Keyboard Control board as earlier described.
9. Ensure all (sub-) frames, boards and cables that do not
belong to the LCD panel are removed before sending the
LCD Panel in.

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Mechanical Instructions Q552.1E LA 4. EN 19

4.6 Assy/Panel Removal Van Gogh Styling

The instructions apply to the 46PFL5605H/xx.

4.6.1 Rear Cover

Warning: Disconnect the mains power cord before you remove


the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.
1. Remove all screws of the rear cover.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.

Special note for 40" sets


Refer to Figure 4-19 to Figure 4-22 for details.
18770_152_100218.eps
100218

Figure 4-21 Rear cover 40" -3-


2

1
2 2 3
2 4
2

18770_150_100218.eps
100219

Figure 4-19 Rear cover 40" -1-


18770_153_100218.eps
100218

Figure 4-22 Rear cover 40" -4-

1. Lift the rear cover on the bottom [1].


2. Push back the cover [2] to unlock the catches.
3. If the rear cover catches still lock, place a flat screwdriver
between flare and rear cover and turn it until the rear cover
and the flare are disassembled from the catch.
4. The location of the catches are indicated with [1], [2], [3]
and [4].

4.6.2 Speakers

Tweeters
Each tweeter unit is mounted with one screw.
When defective, replace the whole unit.
18770_151_100218.eps
100218 Subwoofer
The central subwoofer is located in the centre of the set, and is
Figure 4-20 Rear cover 40" -2- mounted with two screws.
When defective, replace the whole unit.

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EN 20 4. Q552.1E LA Mechanical Instructions

4.6.3 Main Power Supply

Refer to Figure 4-23 for details.

2 2
1

1
1 1
2 2

1 1

18770_142_100215.eps
100215
2 2
1
Figure 4-25 IR & LED Board -1-
18770_140_100215.eps
100217

Figure 4-23 Main Power Supply

1. Unplug all connectors [1].


2. Remove the fixation screws [2].
3. Take the board out.
When defective, replace the whole unit.

4.6.4 Small Signal Board (SSB) 2

Refer to Figure 4-24 for details.

3 18770_143_100215.eps
100215
3
1 Figure 4-26 IR & LED Board -2-

2
3
3
3

18770_141_100215.eps
100217

Figure 4-24 SSB

1. Unplug all connectors [1] and [2].


2. Remove the fixation screws [3].
3. Take the board out.
When defective, replace the whole unit.

4.6.5 Mains Switch

The mains switch is mounted on the front bezel with two


screws.

4.6.6 IR & LED Board

Refer to Figure 4-25, Figure 4-26 and Figure 4-27 for details.

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Mechanical Instructions Q552.1E LA 4. EN 21

3 3

18770_144_100215.eps
100215

Figure 4-27 IR & LED Board -3-

1. Remove the stand [1].


2. Remove the IR & LED board cover [2].
3. Release the clips [3] that secure the IR & LED board.
4. Remove the connectors [4] on the IR/LED board.

4.6.7 Keyboard Control Board

Refer to Figure 4-28 for details.

18770_145_100216.eps
100217

Figure 4-28 Keyboard Control board

1. Unplug the connector on the IR & LED board that leads to


the Keyboard Control board as earlier described.
2. Release the cable from its clamps.
3. Release the clip on top of the unit [1] and take the unit out.
When defective, replace the whole unit.

4.6.8 LCD Panel

Refer to Figure 4-29 for details.


1. Remove the stand as earlier described.
2. Remove the brackets [1].
3. Remove the stand support [2].
4. Remove the central subwoofer as earlier described.
5. Remove the tweeters as earlier described.
6. Remove the mains switch as earlier described.
7. Remove the IR & LED board as earlier described.
8. Remove the keyboard control board as earlier described.
9. Remove the clamps [3].
10. Remove the flare.
11. Remove all remaining screws [4].
Now the LCD Panel can be lifted from the front cabinet.

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EN 22 4. Q552.1E LA Mechanical Instructions

1 1

4 1 4 1 4
4 4 4

3 3

1 1

4 4

1 1

2 2 2
3 3
1 1

4 4 4 4
3 2 4 2 2 4 2 3

18770_146_100216.eps
100216

Figure 4-29 LCD Panel

4.7 Assy/Panel Removal Matisse Styling 4.8 Set Re-assembly

The Matisse styling is similar to the Van Gogh styling. No To re-assemble the whole set, execute all processes in reverse
detailed information is available at time of publishing. order.

Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 23

5. Service Modes, Error Codes, and Fault Finding


Index of this chapter: • All service-unfriendly modes (if present) are disabled, like:
5.1 Test Points – (Sleep) timer.
5.2 Service Modes – Child/parental lock.
5.3 Stepwise Start-up – Picture mute (blue mute or black mute).
5.4 Service Tools – Automatic volume levelling (AVL).
5.5 Error Codes – Skip/blank of non-favourite pre-sets.
5.6 The Blinking LED Procedure
5.7 Protections How to Activate SDM
5.8 Fault Finding and Repair Tips For this chassis there are two kinds of SDM: an analog SDM
5.9 Software Upgrading and a digital SDM. Tuning will happen according Table 5-1.
• Analogue SDM: use the standard RC-transmitter and key
in the code “062596”, directly followed by the “MENU” (or
5.1 Test Points
HOME) button.
Note: It is possible that, together with the SDM, the main
As most signals are digital, it will be difficult to measure menu will appear. To switch it “off”, push the “MENU”(or
waveforms with a standard oscilloscope. However, several key HOME) button again.
ICs are capable of generating test patterns, which can be • Digital SDM: use the standard RC-transmitter and key in
controlled via ComPair. In this way it is possible to determine the code “062593”, directly followed by the “MENU” (or
which part is defective. HOME) button.
Note: It is possible that, together with the SDM, the main
Perform measurements under the following conditions: menu will appear. To switch it “off”, push the “MENU” (or
• Service Default Mode. HOME) button again.
• Video: Colour bar signal. • Analogue SDM can also be activated by grounding for a
• Audio: 3 kHz left, 1 kHz right. moment the solder path on the SSB, with the indication
“SDM” (see Service mode pad).
5.2 Service Modes

Service Default mode (SDM) and Service Alignment Mode


(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.

This chassis also offers the option of using ComPair, a


hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section “5.4.1 ComPair”).

Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old “MENU”
button is now called “HOME” (or is indicated by a “house” icon).
SDM

5.2.1 Service Default Mode (SDM)

Purpose
• To create a pre-defined setting, to get the same
measurement results as given in this manual.
• To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
18770_249_100215.eps
section “5.3 Stepwise Start-up”. 100215
• To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section “5.5 Error Codes”). Figure 5-1 Service mode pad

Specifications After activating this mode, “SDM” will appear in the upper right
corner of the screen (when a picture is available).
Table 5-1 SDM default settings
How to Navigate
Default When the “MENU” (or HOME) button is pressed on the RC
Region Freq. (MHz) system transmitter, the TV set will toggle between the SDM and the
normal user menu.
Europe, AP(PAL/Multi) 475.25 PAL B/G
Europe, AP DVB-T 546.00 PID DVB-T
How to Exit SDM
Video: 0B 06 PID
Use one of the following methods:
PCR: 0B 06 PID
• Switch the set to STAND-BY via the RC-transmitter.
Audio: 0B 07
• Via a standard customer RC-transmitter: key in “00”-
sequence.
• All picture settings at 50% (brightness, colour, contrast).
• Sound volume at 25%.
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EN 24 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

5.2.2 Service Alignment Mode (SAM) button and “XXX” (where XXX is the 3 digit decimal display
code as mentioned in Table 6-9). Make sure to key in all three
Purpose digits, also the leading zero’s. If the above action is successful,
• To perform (software) alignments. the front LED will go out as an indication that the RC sequence
• To change option settings. was correct. After the display option is changed in the NVM, the
• To easily identify the used software version. TV will go to the Stand-by mode. If the NVM was corrupted or
• To view operation hours. empty before this action, it will be initialized first (loaded with
• To display (or clear) the error code buffer. default values). This initializing can take up to 20 seconds.

How to Activate SAM


Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” button. After activating SAM Display Option
with this method a service warning will appear on the screen, Code

continue by pressing the “OK” button on the RC.


39mm

Contents of SAM (see also Table 6-10) PHILIPS 040

27mm
MODEL:
• Hardware Info. 32PF9968/10

– A. SW Version. Displays the software version of the PROD.SERIAL NO:


AG 1A0620 000001

main software (example: Q555X-1.2.3.4 = (CTN Sticker)


AAAAB_X.Y.W.Z).
E_06532_038.eps
• AAAA= the chassis name. 240108
• B= the SW branch version. This is a sequential
number (this is no longer the region indication, as Figure 5-2 Location of Display Option Code sticker
the software is now multi-region).
• X.Y.W.Z= the software version, where X is the • Store - go right. All options and alignments are stored
main version number (different numbers are not when pressing “cursor right” (or the “OK” button) and then
compatible with one another) and Y.W.Z is the sub the “OK”-button.
version number (a higher number is always • SW Maintenance.
compatible with a lower number). – SW Events. Not useful for Service purposes. In case
– B. STBY PROC Version. Displays the software of specific software problems, the development
version of the stand-by processor. department can ask for this info.
– C. Production Code. Displays the production code of – HW Events. Not useful for Service purposes. In case
the TV, this is the serial number as printed on the back of specific software problems, the development
of the TV set. Note that if an NVM is replaced or is department can ask for this info.
initialized after corruption, this production code has to • Test settings. For development purposes only.
be re-written to NVM. ComPair will foresee in a • Development file versions. Not useful for Service
possibility to do this. purposes, this information is only used by the development
• Operation Hours. Displays the accumulated total of department.
operation hours (not the stand-by hours). Every time the • Upload to USB. To upload several settings from the TV to
TV is switched “on/off”, 0.5 hours is added to this number. an USB stick, which is connected to the SSB. The items are
• Errors (followed by maximum 10 errors). The most recent “Channel list”, “Personal settings”, “Option codes”,
error is displayed at the upper left (for an error explanation “Display-related alignments”, “Identification data” and
see section “5.5 Error Codes”). “History list”. First a directory “repair\” has to be created
• Reset Error Buffer. When “cursor right” (or the “OK in the root of the USB stick. To upload the settings select
button) is pressed and then the “OK” button is pressed, the each item separately, press “cursor right” (or the “OK”
error buffer is reset. button), confirm with “OK” and wait until “Done” appears. In
• Alignments. This will activate the “ALIGNMENTS” sub- case the download to the USB stick was not successful
menu. See Chapter 6. Alignments. “Failure” will appear. In this case, check if the USB stick is
• Dealer Options. Extra features for the dealers. connected properly and if the directory “repair” is present in
• Options. Extra features for Service. For more info the root of the USB stick. Now the settings are stored onto
regarding option codes, 6. Alignments. the USB stick and can be used to download onto another
Note that if the option code numbers are changed, these TV or other SSB. Uploading is of course only possible if the
have to be confirmed with pressing the “OK” button before software is running and if a picture is available. This
the options are stored. Otherwise changes will be lost. method is created to be able to save the customer’s TV
• Initialize NVM. The moment the processor recognizes a settings and to store them into another SSB.
corrupted NVM, the “initialize NVM” line will be highlighted. • Download to USB. To download several settings from the
Now, two things can be done (dependent of the service USB stick to the TV, same way of working needs to be
instructions at that moment): followed as with uploading. To make sure that the
– Save the content of the NVM via ComPair for download of the channel list from USB to the TV is
development analysis, before initializing. This will give executed properly, it is necessary to restart the TV and
the Service department an extra possibility for tune to a valid preset if necessary.
diagnosis (e.g. when Development asks for this). • NVM editor. For NET TV the set type must be installed.
– Initialize the NVM. Also the production code can be entered via the RC-
transmitter.
Note: When the NVM is corrupted, or replaced, there is a high
possibility that no picture appears because the display code is How to Navigate
not correct. So, before initializing the NVM via the SAM, a • In SAM, the menu items can be selected with the
picture is necessary and therefore the correct display option “CURSOR UP/DOWN” key on the RC-transmitter. The
has to be entered. Refer to Chapter 6. Alignments for details. selected item will be highlighted. When not all menu items
To adapt this option, it’s advised to use ComPair (the correct fit on the screen, move the “CURSOR UP/DOWN” key to
HEX values for the options can be found in Chapter 6. display the next/previous menu items.
Alignments) or a method via a standard RC (described below). • With the “CURSOR LEFT/RIGHT” keys, it is possible to:
Changing the display option via a standard RC: Key in the – (De) activate the selected menu item.
code “062598” directly followed by the “MENU” (or HOME) – (De) activate the selected sub menu.

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 25

• With the “OK” key, it is possible to activate the selected • Installed date. Indicates the date of the first installation of
action. the TV. This date is acquired via time extraction.
• Options 1. Gives the option codes of option group 1 as set
How to Exit SAM in SAM (Service Alignment Mode).
Use one of the following methods: • Options 2. Gives the option codes of option group 2 as set
• Switch the TV set to STAND-BY via the RC-transmitter. in SAM (Service Alignment Mode).
• Via a standard RC-transmitter, key in “00” sequence, or • 12NC SSB. Gives an identification of the SSB as stored in
select the “BACK” key. NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. ComPair will foresee in a possibility to do this. This
5.2.3 Customer Service Mode (CSM)
identification number is the 12nc number of the SSB.
• 12NC display. Shows the 12NC of the display.
Purpose • 12NC supply. Shows the 12NC of the supply.
When a customer is having problems with his TV-set, he can
• 12NC 200Hz board. Shows the 12NC of the 200Hz Panel.
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service Software versions
• Current main SW. Displays the build-in main software
technician can judge the severity of the complaint. In many
version. In case of field problems related to software,
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer. software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
The CSM is a read only mode; therefore, modifications in this
Example: Q555X_1.2.3.4
mode are not possible.
• Standby SW. Displays the build-in stand-by processor
software version. Upgrading this software will be possible
When in this chassis CSM is activated, a testpattern will be
via ComPair or via USB (see section 5.9 Software
displayed during 5 seconds (1 second Blue, 1 second Green
and 1 second Red, then again 1 second Blue and 1 second Upgrading).
Example: STDBY_88.68.1.2.
Green). This test pattern is generated by the PNX51X0. So if
• e-UM version. Displays the electronic user manual SW-
this test pattern is shown, it could be determined that the back
end video chain (PNX51X0, LVDS, and display) of the SSB is version.
working. For TV sets without the PNX51X0 inside, every menu
from CSM will be used as check for the back end video chain. Quality items
• Signal quality. bad / average /good
When CSM is activated and there is a USB stick connected to • Ethernet MAC address. Dispays the MAC address
the TV set, the software will dump the complete CSM content present in the SSB.
to the USB stick. The file (Csm.txt) will be saved in the root of • Wireless MAC address. Displays the wireless MAC
the USB stick. This info can be handy if no information is address to support the Wi-Fi functionality.
displayed. To have fast feedback from the field, a flashdump • BDS key. Indicates if the set is in the BDS status.
can be requested. While in CSM, push the red button + dial • CI slot present. If the common interface module is
serial digits ‘2679’ (same keys to form the word ‘COPY’ with a detected.
cellphone). A file Dump_settype_serienumber.bin will be • Event counter.
written on the connected USB device. This can take 1/2 minute,
depending on the quantity of data that needs to be dumped. How to Exit CSM
Press “MENU” (or HOME) / “Back” key on the RC-transmitter.
Also when CSM is activated, the LAYER 1 error is displayed via
blinking LED. Only the latest error is displayed. (see also
section 5.5 Error Codes).

How to Activate CSM

Key in the code “123654” via the standard RC transmitter.


Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!

How to Navigate
By means of the “CURSOR-DOWN/UP” knob on the RC-
transmitter, can be navigated through the menus.

Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.

General
• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this.
• Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee a in possibility to
do this.

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EN 26 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

5.3 Stepwise Start-up 7U0X or others FET’s on shortcircuit before activating SDM via
the service pads.
When the TV is in a protection state due to an error detected by
stand-by software (error blinking is displayed) and SDM is
activated via shortcutting the SDM solder path on the SSB, the
TV starts up until it reaches the situation just before protection. The abbreviations “SP” and “MP” in the figures stand for:
So, this is a kind of automatic stepwise start-up. In combination • SP: protection or error detected by the Stand-by
with the start-up diagrams below, you can see which supplies Processor.
are present at a certain moment. Caution: in case the start-up • MP: protection or error detected by the MIPS Main
in this mode with a faulty FET 7U0X is done, you can destroy Processor.
all IC’s supplied by the +1V8 and +1v1, due to overvoltage (12V
on XVX-line). It is recommended to measure first the FET

Mains
off Mains
on

- WakeUp requested
WakeUp
- Acquisition needed
requested
- Tact switch pushed

St by Semi Active
- stby requested and
no data Acquisition St by - St by requested
required - tact SW pushed

Tact switch
pushed
WakeUp
requested
- Tact switch pushed
(SDM)
- last status is hibernate
GoToProtection
after mains ON
Hibernate
GoToProtection

Protection

18770_250_100216.eps
100216

Figure 5-3 Transition diagram

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 27

Off
Mains is applied
Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.

st-by µP resets

If the protection state was left by short circuiting the


Initialise I/O pins of the st-by µP:
SDM pins, detection of a protection condition during
- Switch reset-AVC LOW (reset state)
startup will stall the startup. Protection conditions in a
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state) playing set will be ignored. The protection mode will
not be entered.
- Switch reset-USB LOW (reset state)
- Switch reset-DVBs LOW (reset state)
- keep Audio-reset and Audio-Mute-Up HIGH

- Switch Audio-Reset high.


start keyboard scanning, RC detection. Wake up reasons are It is low in the standby mode if the standby
off. mode lasted longer than 10s.

Switch ON Platform and display supply by switching


LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power


is switched on, followed by the +1V2 DCDC converter
Detect2 is moved to an interrupt. To be checked if
the detection on interrupt base is feasible or not or if
we should stick to the standard 40ms interval. 12V error:
Detect2 high received
No Layer1: 3
within 2 seconds?
Layer2: 16

Yes
Enter protection
Enable the DCDC converters
(ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set I²C slave address


of Standby µP to (A0h)

Detect EJTAG debug probe


(pulling pin of the probe interface to An EJTAG probe (e.g. WindPower ICE probe) can be
ground by inserting EJTAG probe) connected for Linux Kernel debugging purposes.

EJTAG probe
Yes
connected ?

No

No No Cold boot?

Yes

Release AVC system reset Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script Feed initializing boot script
disable alive mechanism

18770_251_100216.eps
100216

Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)

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EN 28 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

Reset-system is switched HIGH by the Reset-system is switched HIGH by the


AVC at the end of the bootscript AVC at the end of the bootscript

No

AVC releases Reset-Ethernet, Reset-USB and AVC releases Reset-Ethernet, Reset-USB and
This cannot be done through the bootscript, Reset-DVBs when the end of the AVC boot- Reset-DVBs when the end of the AVC boot-
the I/O is on the standby µP script is detected script is detected

Reset-Audio and Audio-Mute-Up are Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the switched by MIPS code later on in the
Timing need to be updated if startup process startup process
more mature info is available.

Bootscript ready
No
in 1250 ms?

Yes

Set I²C slave address


of Standby µP to (60h)

RPC start (comm. protocol)


Timing needs to
be updated if more
Flash to Ram mature info is
No image transfer succeeded available.
within 30s?
Code =
Layer1: 2
Layer2: 15 Yes
Timing needs to be
updated if more
Code = mature info is
Switch AVC PNX85500 in SW initialization
Layer1: 2 No available.
reset (active low) succeeded
Layer2: 53
within 20s?

Wait 10ms Yes

Enable Alive check mechanism


Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.

MIPS reads the wake up reason Wait until AVC starts to


from standby µP. communicate
Wait 5ms

Startup screen shall only be visible when there is a coldboot to


an active state end situation. The startup screen shall not be
Wake up reason visible when waking up for reboot reasons or waking up to semi-
switch off the remaining DC/DC coldboot & not semi-
converters standby? standby conditions or waking up to enter Hibernate mode..

yes
Switch Standby I/O line high
3-th try?
and wait 4 seconds
The first time after the option turn on of the startup screen or
Startup screen cfg file when the set is virgin, the cfg file is not present and hence
present? the startup screen will not be shown.
Yes

yes
Blink Code as
error code
200Hz set? yes

No
Enter protection
85500 sends out startup screen 85500 sends out startup screen

No
200Hz Tcon has started up the
85500 starts up the display.
display.
No

To keep this flowchart readable, the exact Startup screen visible 85500 requests Lamp on
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
Startup screen visible
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid. Initialize audio

initialize tuner and channel decoders

Initialize source selection

Initialize video processing IC’s

initialize AutoTV by triggering CHS AutoTV Init interface

Initialize Ambilight with Lights off.

Semi-Standby
18770_252_100216.eps
100216

Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 29

Constraints taken into account:


- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty
cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output
level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts,
the picture should only be unblanked after these first seconds.

The assumption here is that a fast toggle (<2s) can


only happen during ON->SEMI ->ON. In these states,
Semi Standby
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
Wait until previous on-state is left more than 2
made in less than 2s, because the standby state will
seconds ago. (to prevent LCD display problems)
be maintained for at least 4s.

Assert RGB video blanking


CPipe already generates a valid output and audio mute
clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.

Display already on?


(splash screen)

No

Switch on the display power by


The exact timings to switching LCD-PWR-ON low
switch on the
display (LVDS Yes
Wait x ms
delay, lamp delay)
are defined in the Initialize audio and video
display file. Switch on LVDS output in the 85500 processing IC's and functions
according needed use case.
Delay Lamp-on with the sum of the LVDS delay and
the Lamp delay indicated in the display file

Switch off the dimming backlight feature, set


the BOOST control to nominal and make sure
PWM output is set to maximum allowed PWM

Switch on LCD backlight (Lamp-ON)

Start POK line Wait until valid and stable audio and video, corresponding to the
detection algorithm requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
return

Switch Audio-Reset low and wait 5ms

A LED set does not normally need a


Release audio mute and wait 100ms before any other audio
preheat time. The preheat remains present
handling is done (e.g. volume change)
but is set to zero in the display file.

Restore dimming backlight feature, PWM and BOOST output


The higher level requirement is that audio and video
and unblank the video.
should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.
Switch on the Ambilight functionality according the last status
settings.

Startup screen Option


and Installation setting
Photoscreen ON?

Yes

Display cfg file present


and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_253_100216.eps
100216

Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)

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EN 30 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

The assumption here is that a fast toggle (<2s)


can only happen during ON->SEMI ->ON. In
Semi Standby
these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI-
>STBY->SEMI->ON can be made in less than 2s, Wait until previous on-state is left more than 2
we have to delay the semi -> stby transition until seconds ago. (to prevent LCD display problems)
the requirement is met.

Assert RGB video blanking


and audio mute

There is no need to define the Backlight already on?


display timings since the timing (splash screen)
implementation is part of the Tcon. Yes

No Initialize audio and video


processing IC's and functions
according needed use case.
Request Tcon to Switch on the backlight in a
direct LED or
set Lamp-on I/O line in case of a side LED

Start POK line


detection algorithm

Wait until valid and stable audio and video, corresponding to


the requested output is delivered by the AVC.

return
Switch Audio-Reset low and wait 5ms

Release audio mute and wait 100ms before any other audio
The higher level requirement is that audio and handling is done (e.g. volume change)
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblank the video.
unblanking of the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?

Yes

Display cfg file present


and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_254_100216.eps
100216

Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 31

Active

Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground


(I/O: audio reset)
And wait 5ms

switch off Ambilight

Wait until Ambilight has faded out: Output power


Observer should be zero

Switch off POK line


detection algorithm

switch off LCD backlight


(I/O or I²C)

Mute all video outputs

Yes 200Hz set?

No

Wait x ms (display file)

Instruct 200Hz
The exact timings to
Tcon to turn off Switch off LVDS output in 85500
switch off the
the display
display (LVDS
delay, lamp delay)
Wait x ms
are defined in the
display file.

Switch off the display power by


switching LCD-PWR-ON high

Semi Standby
18770_255_100216.eps
100216

Figure 5-8 “Active” to “Semi Stand-by” flowchart

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EN 32 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

Semi Stand by

If ambientlight functionality was used in semi-standby


(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by µP.

Switch Memories to self-refresh (this creates a more


stable condition when switching off the power).

Switch AVC system in reset state (reset-system and


reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Wait 10ms

Disable all supply related protections and switch off


the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the


Standby I/O line

Important remarks:

release reset audio 10 sec after entering


standby to save power

Also here, the standby state has to be


maintained for at least 4s before starting
another state transition.
Stand by

18770_256_100216.eps
100216

Figure 5-9 “Semi Stand-by” to “Stand-by” flowchart

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 33

5.4 Service Tools 5.5 Error Codes

5.4.1 ComPair 5.5.1 Introduction

Introduction The error code buffer contains all detected errors since the last
ComPair (Computer Aided Repair) is a Service tool for Philips time the buffer was erased. The buffer is written from left to
Consumer Electronics products. and offers the following: right, new errors are logged at the left side, and all other errors
1. ComPair helps to quickly get an understanding on how to shift one position to the right.
repair the chassis in a short and effective way. When an error occurs, it is added to the list of errors, provided
2. ComPair allows very detailed diagnostics and is therefore the list is not full. When an error occurs and the error buffer is
capable of accurately indicating problem areas. No full, then the new error is not added, and the error buffer stays
knowledge on I2C or UART commands is necessary, intact (history is maintained).
because ComPair takes care of this. To prevent that an occasional error stays in the list forever, the
3. ComPair speeds up the repair time since it can error is removed from the list after more than 50 hrs. of
automatically communicate with the chassis (when the µP operation.
is working) and all repair information is directly available. When multiple errors occur (errors occurred within a short time
4. ComPair features TV software up possibilities. span), there is a high probability that there is some relation
between them.
Specifications
ComPair consists of a Windows based fault finding program New in this chassis is the way errors can be displayed:
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an • If no errors are there, the LED should not blink at all in
USB cable. For the TV chassis, the ComPair interface box and CSM or SDM. No spacer must be displayed as well.
the TV communicate via a bi-directional cable via the service • There is a simple blinking LED procedure for board
connector(s). level repair (home repair) so called LAYER 1 errors
The ComPair fault finding program is able to determine the next to the existing errors which are LAYER 2 errors (see
problem of the defective television, by a combination of Table 5-2).
automatic diagnostics and an interactive question/answer – LAYER 1 errors are one digit errors.
procedure. – LAYER 2 errors are 2 digit errors.
• In protection mode.
– From consumer mode: LAYER 1.
How to Connect
– From SDM mode: LAYER 2.
This is described in the chassis fault finding database in
ComPair. • Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
TO TV
– From SDM mode: LAYER 2.
TO
UART SERVICE
TO
I2C SERVICE
TO
UART SERVICE • In CSM mode.
CONNECTOR CONNECTOR CONNECTOR
– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
ComPair II
Multi • In SDM mode.
RC in function
RC out
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Optional Power Link/ Mode
Switch Activity I2C RS232 /UART
• Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
PC
Basically there are three kinds of errors:
• Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure”).
ComPair II Developed by Philips Brugge
• Errors detected by the Stand-by software which not
Optional power
HDMI 5V DC lead to protection. In this case the front LED should blink
I2C only
the involved error. See also section “5.5 Error Codes, 5.5.4
Error Buffer, Extra Info”. Note that it can take up several
10000_036_090121.eps
091118 minutes before the TV starts blinking the error (e.g. LAYER
1 error = 2, LAYER 2 error = 15 or 53).
Figure 5-10 ComPair II interface connection • Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
Caution: It is compulsory to connect the TV to the PC as out via ComPair, via blinking LED method LAYER 1-2
shown in the picture above (with the ComPair interface in error, or in case picture is visible, via SAM.
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be 5.5.2 How to Read the Error Buffer
blown!
Use one of the following methods:
How to Order • On screen via the SAM (only when a picture is visible).
ComPair II order codes: E.g.:
• ComPair II interface: 3122 785 91020. – 00 00 00 00 00: No errors detected
• Software is available via the Philips Service web portal. – 23 00 00 00 00: Error code 23 is the last and only
• ComPair UART interface cable for Q55x.x. detected error.
(using 3.5 mm Mini Jack connector): 3138 188 75051. – 37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note: While encounting problems, contact the local support – Note that no protection errors can be logged in the
desk. error buffer.

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EN 34 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

• Via the blinking LED procedure. See section 5.5.3 How to content, as this history can give significant information). This to
Clear the Error Buffer. ensure that old error codes are no longer present.
• Via ComPair. If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
5.5.3 How to Clear the Error Buffer code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Use one of the following methods:
• Via error bits in the status registers of ICs.
• By activation of the “RESET ERROR BUFFER” command
in the SAM menu. • Via polling on I/O pins going to the stand-by processor.
• Via sensing of analog values on the stand-by processor or
• If the content of the error buffer has not changed for 50+
the PNX85500.
hours, it resets automatically.
• Via a “not acknowledge” of an I2C communication.

5.5.4 Error Buffer


Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
In case of non-intermittent faults, clear the error buffer before
problems wait 2 minutes from start-up onwards, and then
starting to repair (before clearing the buffer, write down the check if the front LED is blinking or if an error is logged.

Table 5-2 Error code overview

Monitored Error/ Error Buffer/


Description Layer 1 Layer 2 by Prot Blinking LED Device Defective Board
I2C3 2 13 MIPS E BL / EB SSB SSB
I2C2 2 14 MIPS E BL / EB SSB SSB
I2C4 2 18 MIPS E BL / EB SSB SSB
PNX doesn’t boot (HW cause) 2 15 Stby µP P BL PNX8550 SSB
12V 3 16 Stby µP P BL / Supply
Inverter or display supply 3 17 MIPS E EB / Supply
HDMI mux 2 23 MIPS E EB Sil9x87A SSB
I2C switch 2 24 MIPS E EB PCA9540 SSB
Channel dec DVB-S 2 28 MIPS E EB STV0903 SSB
Lnb controller 2 31 MIPS E EB LNBH23 SSB
Tuner 2 34 MIPS E EB DTT 71300 SSB
Main nvm 2 35 MIPS E EB STM24C64 SSB
Tuner DVB-S 2 36 MIPS E EB STV6110 SSB
T° sensor SSB/set 2 42 MIPS E EB LM 75 T° sensor
T° sensor LED driver/Tcon 7 42 MIPS E EB LM 75 T° sensor
PNX doesn’t boot (SW cause) 2 53 Stby µP P BL PNX8550 SSB
Display 5 64 MIPS E BL / EB Altera Display

Extra Info blocked (NVM). I2C1 can be indicated in the schematics as


• Rebooting. When a TV is constantly rebooting due to follows: SCL-UP-MIPS, SDA-UP-MIPS.
internal problems, most of the time no errors will be logged Other root causes for this error can be due to hardware
or blinked. This rebooting can be recognized via a ComPair problems regarding the DDR’s and the bootscript reading
interface and Hyperterminal (for Hyperterminal settings, from the PNX8550.
see section “5.8 Fault Finding and Repair Tips, 5.8.6 • Error 16 (12V). This voltage is made in the power supply
Logging). It’s shown that the loggings which are generated and results in protection (LAYER 1 error = 3) in case of
by the main software keep continuing. In this case absence. When SDM is activated we see blinking LED
diagnose has to be done via ComPair. LAYER 2 error = 16.
• Error 13 (I2C bus 3, SSB bus blocked). At the time of • Error 17 (Invertor or Display Supply). Here the status of
release of this manual, this error was not working as the “Power OK” is checked by software, no protection will
expected. Current situation: when this error occurs, the TV occur during failure of the invertor or display supply (no
will constantly reboot due to the blocked bus. The best way picture), only error logging. LED blinking of LAYER 1
for further diagnosis here, is to use ComPair. error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
• Error 14 (I2C bus 2, TV set bus blocked). At the time of • Error 23 (HDMI). When there is no I2C communication
release of this manual, this error was not working as towards the HDMI mux after start-up, LAYER 2 error = 23
expected. Current situation: when this error occurs, the TV will be logged and displayed via the blinking LED
will constantly reboot due to the blocked bus. The best way procedure if SDM is switched on.
for further diagnosis here, is to use ComPair. • Error 24 (I2C switch). When there is no I2C
• Error 18 (I2C bus 4, Tuner bus blocked). At the time of communication towards the I2C switch, LAYER 2
release of this manual, this error was not working as error = 24 will be logged and displayed via the blinking LED
expected. Current situation: when this error occurs, the TV procedure when SDM is switched on. Remark : this only
will constantly reboot due to the blocked bus. The best way works for TV sets with an I2C controlled screen included.
for further diagnosis here, is to use ComPair. • Error 28 (Channel dec DVB-S). When there is no I2C
• Error 15 (PNX8550 doesn’t boot). Indicates that the main communication towards the DVB-S channel decoder,
processor was not able to read his bootscript. This error will LAYER 2 error = 28 will be logged and displayed via the
point to a hardware problem around the PNX8550 blinking LED procedure if SDM is switched on.
(supplies not OK, PNX 8550 completely dead, I2C link • Error 31 (Lnb controller). When there is no I2C
between PNX and Stand-by Processor broken, etc...). communication towards this device, LAYER 2 error = 31
When error 15 occurs it is also possible that I2C1 bus is

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 35

will be logged and displayed via the blinking LED 6. The sequence starts again.
procedure if SDM is activated.
• Error 34 (Tuner). When there is no I2C communication 5.6.2 How to Activate
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
Use one of the following methods:
when SDM is switched on. • Activate the CSM. The blinking front LED will show only
• Error 35 (main NVM). When there is no I2C
the latest layer 1 error, this works in “normal operation”
communication towards the main NVM during start-up,
mode or automatically when the error/protection is
LAYER 2 error = 35 will be displayed via the blinking LED monitored by the standby processor.
procedure when SDM is switched “on”. All service modes
In case no picture is shown and there is no LED blinking,
(CSM, SAM and SDM) are accessible during this failure,
read the logging to detect whether “error devices” are
observed in the Uart logging as follows : "<< ERRO >>> mentioned. (see section “5.8 Fault Finding and Repair
PFPOW_.C : First Error (id19, Layer_1= 2 Layer_= 35)".
Tips, 5.8.6 Logging”).
• Error 36 (Tuner DVB-S). When there is no I2C
• Activate the SDM. The blinking front LED will show the
communication towards the DVB-S tuner during start-up, entire content of the LAYER 2 error buffer, this works in
LAYER 2 error = 36 will be logged and displayed via the
“normal operation” mode or when SDM (via hardware pins)
blinking LED procedure when SDM is switched “on”.
is activated when the tv set is in protection.
• Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
• Error 53. This error will indicate that the PNX8550 has 5.7 Protections
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because 5.7.1 Software Protections
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
Most of the protections and errors use either the stand-by
is no valid software loaded (try to upgrade to the latest main
microprocessor or the MIPS controller as detection device.
software version). Note that it can take a few minutes
Since in these cases, checking of observers, polling of ADCs,
before the TV starts blinking LAYER 1 error = 2 or in SDM,
and filtering of input values are all heavily software based,
LAYER 2 error = 53.
these protections are referred to as software protections.
• Error 64. Only applicable for TV sets with an I2C controlled
There are several types of software related protections, solving
screen .
a variety of fault conditions:
• Related to supplies: presence of the +5V, +3V3 and 1V2
5.6 The Blinking LED Procedure needs to be measured, no protection triggered here.
• Protections related to breakdown of the safety check
5.6.1 Introduction mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
The blinking LED procedure can be split up into two situations:
guaranteed any more.
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
referring to the defective board (see table “5-2 Error code
playing of the set does not lead to a protection, but to a cold
overview”) which causes the failure of the TV. This
approach will especially be used for home repair and call reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
centres. The aim here is to have service diagnosis from a
distance.
• Blinking LED procedure LAYER 2 error. Via this procedure, Protections during Start-up
the contents of the error buffer can be made visible via the During TV start-up, some voltages and IC observers are
front LED. In this case the error contains 2 digits (see table actively monitored to be able to optimise the start-up speed,
“5-2 Error code overview”) and will be displayed when SDM and to assure good operation of all components. If these
(hardware pins) is activated. This is especially useful for monitors do not respond in a defined way, this indicates a
fault finding and gives more details regarding the failure of malfunction of the system and leads to a protection. As the
the defective board. observers are only used during start-up, they are described in
Important remark: the start-up flow in detail (see section “5.3 Stepwise Start-up”).
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed. 5.7.2 Hardware Protections

When one of the blinking LED procedures is activated, the front The only real hardware protection in this chassis appears in
LED will show (blink) the contents of the error buffer. Error case of an audio problem e.g. DC voltage on the speakers. This
codes greater then 10 are shown as follows: protection will only affect the Class D audio amplifier (item
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit 7D10; see diagram B03A) and puts the amplifier in a
2. A pause of 1.5 s continuous burst mode (cyclus approximately 2 seconds).
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s, Repair Tip
5. When all the error codes are displayed, the sequence • There still will be a picture available but no sound. While
finishes with a LED blink of 3 s (spacer). the Class D amplifier tries to start-up again, the cone of the
6. The sequence starts again. loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
Example: Error 12 8 6 0 0. starts over and over again. The headphone amplifier will
After activation of the SDM, the front LED will show: also behaves similar.
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence (spacer).
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EN 36 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

5.8 Fault Finding and Repair Tips +12V is considered OK (=> DETECT2 signal becomes high,
+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra can be started up) if it rises above 10V and doesn’t drop below
9V5. A small delay of a few milliseconds is introduced between
Info”.
the start-up of 12V to +1V8 DC-DC converter and the two other
DC-DC converters via 7U48 and associated components.
5.8.1 Ambilight
Description DVB-S2:
Due to degeneration process of the LED’s fitted on the ambi • LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
module, there can be a difference in the colour and/or light LNB supply generated via the second conversion channel
output of the spare ambilight modules in comparison with the of 7T03 followed by 7T50 LNB supply control IC.It provides
originals ones contained in the TV set. Via SAM => alignments supply voltage that feeds the outdoor satellite reception
=> ambilight, the spare module can be adjusted. equipment.
• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
5.8.2 Audio Amplifier and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
The Class D-IC 7D10 has a powerpad for cooling. When the IC via a 5V to 1V DC-DC converter and is stabilized at the
is replaced it must be ensured that the powerpad is very well point of load (channel decoder) by means of feedback
pushed to the PWB while the solder is still liquid. This is needed signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
to insure that the cooling is guaranteed, otherwise the Class D- are generated via linear stabilizers from +5V-DVBS that by
IC could break down in short time. itself is generated via the first conversion channel of 7T03.

At start-up, +24V becomes available when STANDBY signal is


5.8.3 CSM
low (together with +12V for the basic board), when +3V3 from
the basic board is present the two DC-DC converters channels
When CSM is activated and there is a USB stick connected to
inside 7T03 are activated. Initially only the 24V to 5V converter
the TV, the software will dump the complete CSM content to the
(channel 1 of 7T03 generating +5V-DVBS) will effectively work,
USB stick. The file (Csm.txt) will be saved in the root of the USB while +V-LNB is held at a level around 11V7 via diode 6T55.
stick. If this mechanism works it can be concluded that a large
After 7T05 is initialized, the second channel of 7T03 will start
part of the operating system is already working (MIPS, USB...)
and generates a voltage higher then LNB-RF1 with 0V8. +5V-
DVBS start-up will imply +3V3-DVBS start-up, with a small
5.8.4 DC/DC Converter delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will
be enabled.
Description basic board
If +24V drops below +15V level then the DVB-S2 supply will
The basic board power supply consists of 4 DC/DC converters stop, even if +3V3 is still present..
and 5 linear stabilizers. All DC/DC converters have +12V input
voltage and deliver : Debugging
• +1V1 supply voltage (1.15V nominal), for the core voltage The best way to find a failure in the DC/DC converters is to
of PNX85500, stabilized close to the point of load; check their start-up sequence at power-on via the mains cord,
SENSE+1V1 signal provides the DC-DC converter the presuming that the standby microprocessor and the external
needed feedback to achieve this. supply are operational. Take STANDBY signal high-to-low
• +1V8 supply voltage, for the DDR2 memories and DDR2 transition as time reference.
interface of PNX85500. When +12V becomes available (maximum 1 second after
• +3V3 supply voltage (3.30V nominal), overall 3.3 V for STANDBY signal goes low) then +1V1 is started immediately.
onboard IC’s, for non-5000 series SSB diversities only. After ENABLE-3V3 goes low, all the other supply voltages
• +5V (5.15V nominal) for USB, WIFI and Conditional should rise within a few milliseconds.
Access Module and +5V5-TUN for +5V-TUN tuner
stabilizer. Tips
• Behaviour comparison with a reference TV550 platform
The linear stabilizers are providing:
can be a fast way to locate failures.
• +1V2 supply voltage (1.2V nominal), stabilized close to • If +12V stays low, check the integrity of fuse 1U40.
PNX85500 device, for various other internal blocks of
• Check the integrity (at least no short circuit between drain
PNX85500; SENSE+1V2 signal provides the needed
and source) of the power MOS-FETs before starting up the
feedback to achieve this. platform in SDM, otherwise many components might be
• +2V5 supply voltage (2.5V nominal) for LVDS interface and
damaged. Using a ohmmeter can detect short circuits
various other internal blocks of PNX85500; for 5000 series
between any power rail and ground or between +12V and
SSB diversities the stabilizer is 7UD2 while for the other any other power rail.
diversities 7UC0 is used.
• Short circuit at the output of an integrated linear stabilizer
• +3V3 supply voltage (3V3 nominal) for 5000 series SSB
(7UC0, 7UD2 or 7UD3) will heat up this device strongly.
diversities, provided by 7UD3; in this case the 12V to 3V3 • Switching frequencies should be 500 kHz ...600 kHz for
DC-DC converter is not present.
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
• +5V-TUN supply voltage (5V nominal) for tuner and IF
900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC
amplifier. converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V
LNB DC-DC converters operates at 300 kHz while for 5 V
+3V3-STANDY (3V3 nominal) is the permanent voltage,
to 1.1 V DC-DC converter 900 kHz is used.
supplying the standby microprocessor inside PNX85500.

5.8.5 Exit “Factory Mode”


Supply voltage +1V1 is started immediately when +12V voltage
becomes available (+12V is enabled by STANDBY signal when
low). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN When an “F” is displayed in the screen’s right corner, this
are switched on by signal ENABLE-3V3 when low, provided means the set is in “Factory” mode, and it normally
that +12V (detected via 7U40 and 7U41) is present. happens after a new SSB is mounted. To exit this mode, push
the “VOLUME minus” button on the TV’s local keyboard for 10
seconds (this disables the continuous mode).

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 37

Then push the “SOURCE” button for 10 seconds until the “F”
disappears from the screen.

5.8.6 Logging

When something is wrong with the TV set (f.i. the set is


rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a “ComPair UART”-
cable (3138 188 75051) from the service connector in the TV to
the “multi function” jack at the front of ComPair II box.
Required settings in ComPair before starting to log :
- Start up the ComPair application.
- Select the correct database (open file “Q55X.X”, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. “logging”)
in the “Connection Description” box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the “Display Option Code” (useful when there is no picture),
look for item “DisplayRawNumber” in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for “error devices” in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.

5.8.7 Loudspeakers

Make sure that the volume is set to minimum during


disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!

5.8.8 PSL

In case of no picture when CSM (test pattern) is activated and


backlight doesn’t light up, it’s recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
in SDM).

5.8.9 Tuner

Attention: In case the tuner is replaced, always check the tuner


options!

5.8.10 Display option code

Attention: In case the SSB is replaced, always check the


display option code in SAM, even when picture is available.
Performance with the incorrect display option code can lead to
unwanted side-effects for certain conditions.

New in this chassis:


While in the download application (start up in TV mode + “OK”
button pressed), the display option code can be changed via
062598 HOME XXX special SAM command (XXX=display
option in 3 digits).

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EN 38 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

5.8.11 SSB Replacement

Follow the instructions in the flowchart in case a SSB has to be


exchanged. See figure “SSB replacement flowchart”.

In st ru ct io n n o t e SSB rep lacem en t Q543.x - Q548.x - Q549.x

Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No

Yes

C onnect the U SB stick to the set,


go to SAM and save the current TV settings via “Upload to USB”

1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.

Start-up the set


Due to a possible wrong display option code in the received Service
SSB (NVM), it’s possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback). Set behaviour?
No pictur e displayed Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB,


and enable the UART logging on the PC. Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.

1) Plug the USB stick into the TV set and select


3) Plug the prepared USB stick into the TV set. Follow the the “autorun .upg” file in the displayed browser.
instructions in the UART log file, press “Right” cursor key to enter
the list. Navigate to the “autorun.upg” file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press “Ok”.
2) Now the main software will be loaded automatically,
supported by a progress bar.
4) Press "Down" cursor and “Ok” to start flashing the main
TV software. Printouts like: “L: 1-100%, V: 1-100% and
P: 1-100%” should be visible now in the UART logging.

3) Wait until the message “Operation successful !” is displayed


5) Wait until the message “Operation successful !” is logged in and remove all inserted media. Restart the TV set.
the UART log and remove all inserted media. Restart the TV set.

Set the correct “Display code” via “062598 -HOME- xxx” where
“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the “Display Option” code, the set is going to


Standby
(= validation of code)

Restart the set


No

Connect PC via the ComPair interface to Service connector.


Saved settings
on USB stick?

Start TV in Jett mode (DVD I + (OSD)) Yes


Open ComPair browser Q54x
In case of settings reloaded from USB, the set type,
Go to SAM and reload settings serial number, display 12 NC, are automatically stored
via “Download from USB” function. when entering display options.
Program set type number, serial number, and display 12 NC
Program E - DFU if needed.

If not already done:


Check latest software on Service website. - Check if correct “display option” code is programmed.
Update main and Stand-by software via USB. - Verify “option codes” according to sticker inside the set.
- Default settings for “white drive” > see Service Manual.
Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.
Check and perform alignments in SAM according to the
Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.


Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End Q54x.E SSB Board swap – VDS


Updated 19-08-2009

H_16771_007a.eps
091119

Figure 5-11 SSB replacement flowchart

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Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 39

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the An “F” is displayed and the HDMI 1
RED LED is continuous on. input is displayed.

- Press the “volume minus” button on the TVs local keyboard for 10
seconds

- Press the “SOURCE” button for 10 seconds until the “F” disappears
from the screen or the noise on the screen is replaced by “blue mute”

The noise on the screen is replaced


with the blue mute or the “F” is disappeared!

Unplug the mainscord to verify the correct


disabling of the factory-mode.

Program display option code


via “062598 MENU”, followed by
the 3 digits code of the display
(this code can be found
on a sticker inside the set).

After entering “display option” code, the set is


going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
091119

Figure 5-12 SSB replacement flowchart - Factory mode

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EN 40 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding

5.9 Software Upgrading Back-up Software Upgrade Application


If the default software upgrade application does not start (could
5.9.1 Introduction be due to a corrupted boot sector) via the above described
method, try activating the “back-up software upgrade
application”.
The set software and security keys are stored in a NAND-
How to start the “back-up software upgrade application”
Flash, which is connected to the PNX85500. manually:
1. Disconnect the TV from the Mains/AC Power.
It is possible for the user to upgrade the main software via the 2. Press the “CURSOR DOWN”-button on a Philips TV
USB port. This allows replacement of a software image in a remote control while reconnecting the TV to the Mains/AC
stand alone set, without the need of an E-JTAG debugger. A Power.
description on how to upgrade the main software can be found 3. The back-up software upgrade application will start.
in the electronic User Manual.
5.9.3 Stand-by Software Upgrade via USB
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
In this chassis it is possible to upgrade the Stand-by software
(CI +, MAC address, ...).
via a USB stick. The method is similar to upgrading the main
Perform the following actions after SSB replacement: software via USB.
1. Set the correct option codes (see sticker inside the TV).
Use the following steps:
2. Update the TV software => see the eUM (electronic User
1. Create a directory “UPGRADES” on the USB stick.
Manual) for instructions. 2. Copy the Stand-by software (part of the one-zip file, e.g.
3. Perform the alignments as described in chapter 6 (section
StandbySW_CFT72_88.0.0.0.upg) into this directory.
6.5 Reset of Repaired SSB).
3. Insert the USB stick into the TV.
4. Check in CSM if the CI + key, MAC address.. are valid. 4. Start the download application manually (see section “
For the correct order number of a new SSB, always refer to the
Manual Software Upgrade”.
Spare Parts list!
5. Select the appropriate file and press the “OK” button to
upgrade.
5.9.2 Main Software Upgrade
5.9.4 Content and Usage of the One-Zip Software File
• The “UpgradeAll.upg” file is only used in the factory.
Below the content of the One-Zip file is explained, and
Automatic Software Upgrade instructions on how and when to use it.
In “normal” conditions, so when there is no major problem with • FUS_Q5492_x.x.x.x_commercial.zip. Contains the
the TV, the main software and the default software upgrade “autorun.upg” which is needed to upgrade the TV main
application can be upgraded with the “AUTORUN.UPG” software and the software download application.
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS • StandbySW_CFTxx_x.x.x.x_commercial.zip. Contains
_Q555X_ x.x.x.x_commercial.zip). This can also be done by the Stand-by software in “upg” and “hex” format.
the consumers themselves, but they will have to get their – The “StandbySW_xxxxx_prod.upg” file can be used to
software from the commercial Philips website or via the upgrade the Stand-by software via USB.
Software Update Assistant in the user menu (see eUM). The – The “StandbySW_xxxxx.hex” file can be used to
“autorun.upg” file must be placed in the root of the USB stick. upgrade the Stand-by software via ComPair.
How to upgrade: – The files “StandbySW_xxxxx_exhex.hex” and
1. Copy “AUTORUN.UPG” to the root of the USB stick. “StandbySW_xxxxx_dev.upg” may not be used by
2. Insert USB stick in the set while the set is operational. The Service technicians (only for development purposes).
set will restart and the upgrading will start automatically. As • UpgradeAll_Q555X_x.x.x.x_commercial.zip. Only for
soon as the programming is finished, a message is shown production purposes, not to be used by Service
to remove the USB stick and restart the set. technicians.
• ProcessNVM_Q55XX_x.x.x.x.zip. Default NVM content.
Manual Software Upgrade Must be programmed via ComPair or can be loaded via
In case that the software upgrade application does not start USB, be aware that all alignments stored in NVM are
automatically, it can also be started manually. overwritten here.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power. 5.9.5 UART logging 2K10 (see section “5.8 Fault Finding and
2. Press the “OK” button on a Philips TV remote control or a Repair Tips, 5.8.6 Logging)
Philips DVD RC-6 remote control (it is also possible to use
a TV remote in “DVD” mode). Keep the “OK” button
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.

Attention!
In case the download application has been started manually,
the “autorun.upg” will maybe not be recognized.
What to do in this case:
1. Create a directory “UPGRADES” on the USB stick.
2. Rename the “autorun.upg” to something else, e.g. to
“software.upg”. Do not use long or complicated names,
keep it simple. Make sure that “AUTORUN.UPG” is no
longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.
4. Insert USB stick into the TV.
5. The renamed “upg” file will be visible and selectable in the
upgrade application.

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Alignments Q552.1E LA 6. EN 41

6. Alignments
Index of this chapter: For the next alignments, supply the following test signals via a
6.1 General Alignment Conditions video generator to the RF input:
6.2 Hardware Alignments • EU/AP-PAL models: a PAL B/G TV-signal with a signal
6.3 Software Alignments strength of at least 1 mV and a frequency of 475.25 MHz
6.4 Option Settings • US/AP-NTSC models: an NTSC M/N TV-signal with a
6.5 Reset of Repaired SSB signal strength of at least 1 mV and a frequency of 61.25
6.6 Service SSB delivered without main software loaded MHz (channel 3).
6.7 Total Overview SAM modes • LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).
6.1 General Alignment Conditions
6.3.1 White Point
Perform all electrical adjustments under the following
conditions:
• Choose “TV menu”, “Setup”, “More TV Settings” and then
• Power supply voltage (depends on region):
“Picture” and set picture settings as follows:
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%).
– AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%). Picture Setting

– EU: 230 VAC / 50 Hz (± 10%). Contrast 100

– LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%). Brightness 50

– US: 120 VAC / 60 Hz (± 10%). Colour 0

• Connect the set to the mains via an isolation transformer Light Sensor Off

with low internal resistance. Picture format Unscaled

• Allow the set to warm up for approximately 15 minutes.


• Measure voltages and waveforms in relation to correct • In menu “Picture”, choose “Pixel Plus HD” and set picture
ground (e.g. measure audio signals in relation to settings as follows:
AUDIO_GND). Picture Setting
Caution: It is not allowed to use heat sinks as ground. Dynamic Contrast Off
• Test probe: Ri > 10 MΩ, Ci < 20 pF. Dynamic Backlight Off
• Use an isolated trimmer/screwdriver to perform Colour Enhancement Off
alignments. Gamma 0

6.1.1 Alignment Sequence • Go to the SAM and select “Alignments”-> “White point”.

• First, set the correct options: White point alignment LCD screens:
– In SAM, select “Option numbers”. • Use a 90% white screen to the HDMI input and set the
– Fill in the option settings for “Group 1” and “Group 2” following values:
according to the set sticker (see also paragraph 6.4 – “Colour temperature”: “Normal”.
Option Settings). – All “White point” values to: “127”.
– Press OK on the remote control before the cursor is
moved to the left. In case you have a colour analyser:
– In submenu “Option numbers” select “Store” and press • Measure with a calibrated contactless colour analyser
OK on the RC. (Minolta CA-210 or Minolta CS-200) in the centre of the
• OR: screen. Consequently, the measurement needs to be done
– In main menu, select “Store” again and press OK on in a dark environment.
the RC. • Adjust the correct x, y coordinates (while holding one of the
– Switch the set to Stand-by. White point registers R, G or B on 127) by means of
• Warming up (>15 minutes). decreasing the value of one or two other white points to the
correct x, y coordinates (see Table 6-1 White D alignment
values CCFL backlight panels, 6-2 White D alignment
6.2 Hardware Alignments values LED backlight panels - colour analyser Minolta CA-
210 or 6-3 White D alignment values LED backlight panels
Not applicable. - colour analyser Minolta CS-200). Tolerance: dx: ± 0.002,
dy: ± 0.002.
• Repeat this step for the other colour temperatures that
6.3 Software Alignments need to be aligned.
• When finished press OK on the RC and then press STORE
Put the set in SAM mode (see Chapter 5. Service Modes, Error (in the SAM root menu) to store the aligned values to the
Codes, and Fault Finding). The SAM menu will now appear on NVM.
the screen. Select ALIGNMENTS and go to one of the sub • Restore the initial picture settings after the alignments.
menus. The alignments are explained below.
The following items can be aligned: Table 6-1 White D alignment values CCFL backlight panels
• White point
• Ambilight Value Cool (11000K) Normal (9000K) Warm (6500K)
• TCON Alignment x 0.276 0.287 0.313
• Reset TCON Alignment. y 0.282 0.296 0.329

To store the data:


• Press OK on the RC before the cursor is moved to the
left
• In main menu select “Store” and press OK on the RC
• Switch the set to stand-by mode.

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EN 42 6. Q552.1E LA Alignments

Table 6-2 White D alignment values LED backlight panels - 6.4 Option Settings
colour analyser Minolta CA-210
6.4.1 Introduction
Value Cool (9420K) Normal (8120K) Warm (6080K)
x 0.282 0.292 0.320
The microprocessor communicates with a large number of I2C
y 0.298 0.311 0.345
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
Table 6-3 White D alignment values LED backlight panels - which ICs to address. The presence / absence of these
colour analyser Minolta CS-200 PNX51XX ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
Value Cool (11000K) Normal (9000K) Warm (6500K)
is made known by the option codes.
x 0.276 0.287 0.313
y 0.282 0.296 0.329
Notes:
• After changing the option(s), save them by pressing the OK
button on the RC before the cursor is moved to the left,
If you do not have a colour analyser, you can use the default select STORE in the SAM root menu and press OK on the
values. This is the next best solution. The default values are RC.
average values coming from production. • The new option setting is only active after the TV is
• Select a COLOUR TEMPERATURE (e.g. COOL, switched “off” / “stand-by” and “on” again with the mains
NORMAL, or WARM). switch (the NVM is then read again).
• Set the RED, GREEN and BLUE default values according
to the values in Table 6-4. 6.4.2 Dealer Options
• When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.
For dealer options, in SAM select “Dealer options”.
• Restore the initial picture settings after the alignments.
See Table 6-10 SAM mode overview.

Table 6-4 White tone default setting 32" 6.4.3 (Service) Options

White Tone Black level


offset Select the sub menu's to set the initialisation codes (options) of
Colour Temp R G B R G the model number via text menus.
Normal t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. See Table 6-10 SAM mode overview.
Cool t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
Warm t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. 6.4.4 Opt. No. (Option numbers)

Table 6-5 White tone default setting 37" Select this sub menu to set all options at once (expressed in
two long strings of numbers).
White Tone Black level
An option number (or “option byte”) represents a number of
offset different options. When you change these numbers directly,
Colour Temp R G B R G you can set all options very quickly. All options are controlled
Normal t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. via eight option numbers.
Cool t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. When the NVM is replaced, all options will require resetting. To
Warm t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set and in Table 6-9
Table 6-6 White tone default setting 40"
Option and display code overview.
Example: The options sticker gives the following option
White Tone Black level
offset
numbers:
Colour Temp R G B R G
• 08192 00133 01387 45160
Normal t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
• 12232 04256 00164 00000
Cool t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
The first line (group 1) indicates hardware options 1 to 4, the
Warm t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
Table 6-7 White tone default setting 42" When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
White Tone Black level See Table 6-9 Option and display code overview for the
offset
options.
Colour Temp R G B R G
Normal 127 109 106 t.b.d. t.b.d.
Diversity
Cool 124 112 127 t.b.d. t.b.d.
Not all sets with the same Commercial Type Number (CTN)
Warm 127 95 61 t.b.d. t.b.d.
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
Table 6-8 TCON default settings indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
Screen size TCON Alignment Refer to Chapter 2. Technical Specifications, Diversity, and
32" t.b.d. Connections.
37" t.b.d.
40" t.b.d.
42" t.b.d.

6.4.5 Option Code Overview

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Alignments Q552.1E LA 6. EN 43

Table 6-9 Option and display code overview 6.6 Service SSB delivered without main software
loaded
CTN Options Group 1 Options Group 2 Disp.
(Alt. BOM#) code
32PFL5405H/xx 00008 00000 15421 02176 43798 34315 00000 00000 278 Due to a changed manufacturing process, new Service SSB’s
32PFL5605H/xx 00008 00000 15421 08192 44009 34315 00000 00000 233 can be delivered to the warehouse without main TV
32PFL7605H/xx 02060 00000 12351 30911 43795 34315 00000 00000 275 software loaded. Below you find the steps to follow when such
37PFL5405H/xx 00008 00000 15421 02176 43798 34315 00000 00000 278 an SSB is received.
40PFL5605H/xx 00008 00000 15421 08192 44009 34315 00000 00000 233
40PFL7605H/xx 02060 00000 12351 30911 43795 34315 00000 00000 275 6.6.1 When a picture is available
42PFL5405H/xx 00008 00000 15421 02176 43798 34315 00000 00000 278
1. Mount the Service SSB into the TV set. After start-up,
Important: after having edited the option numbers as normally the download application will appear on the
described above, you must press OK on the remote control screen.
before the cursor is moved to the left! 2. Download the latest main software (FUS) from the
www.p4c.philips.com website.
3. Create a folder “upgrades” in the root of a USB stick (size
6.5 Reset of Repaired SSB > 50 MB) and save the “autorun.upg” file in this “upgrades”
folder. Note: it is possible to rename this file, e.g.
A very important issue towards a repaired SSB from a service “Q555_SW_version.upg”, this in case there are more than
repair shop (SSB repair on component level) implies the reset one “autorun.upg” files on your USB stick
of the NVM on the SSB. 4. Plug the prepared USB stick into the TV set, and select the
A repaired SSB in service should get the service Set type “autorun” file in the displayed browser on the screen
“00PF0000000000” and Production code “00000000000000”. 5. Now the main TV software will be loaded automatically,
Also the virgin bit is to be set. To set all this, you can use the supported by a progress bar
ComPair tool. 6. Set the correct “display code” via “062598-HOME-xxx”,
where “xxx” is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).
After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For 6.6.2 When no picture is available
this (new in this platform), you can use the NVM editor in
SAM. This action also ensures the correct functioning of the Due to a possible wrong display option code in the received
“Net TV” feature and access to the Net TV portals. The loading Service SSB (NVM), no picture can be available at start-up and
of the CTN and production code can also be done via ComPair thus no download application will be visible. Here you can
(Model number programming). proceed and finalize step by step to load the main TV software
via the UART logging on the PC (for visual feedback).
In case of a display replacement, reset the “Operation hours 1. Start-up the TV set, equipped with the Service SSB, and
display” to “0”, or to the operation hours of the replacement enable the UART logging on the PC (see for settings 5.8
display. Fault Finding and Repair Tips 5.8.6 Logging)
2. The TV set will start-up automatically in the download
application if main TV software is not loaded
6.5.1 SSB identification
3. Plug the prepared USB stick into the TV set, press cursor
“Right” to enter the list, and navigate to the “autorun” file in
Whenever ordering a new SSB, it should be noted that the
the UART logging printout via the cursor keys on the
correct ordering number (12nc) of a SSB is located on a sticker
remote control. When the correct file is selected, press
on the SSB. The format is <12nc SSB><serial number>. The “OK”
ordering number of a “Service” SSB is the same as the ordering
4. Press cursor “Down” and “OK” to start the flashing of the
number of an initial “factory” SSB.
main TV software. Printouts like: “L: 1-100%, V: 1-100%
and P: 1-100%” should be visible now in the UART logging
5. Wait until the message “Operation successful!” is displayed
and remove all inserted media. Restart the TV set
6. Set the correct “display code” via “062598-HOME-xxx”,
where “xxx” is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).

6.6.3 Use of repaired SSBs instead of new

Repaired SSBs on stock will obviously already contain main TV


software. This implies that only a main software upgrade is
required if you use a “repaired” SSB for board swap instead of
a “new” SSB.

18310_221_090318.eps
090319

Figure 6-1 SSB identification

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EN 44 6. Q552.1E LA Alignments

6.7 Total Overview SAM modes

Table 6-10 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description


Hardware Info A. SW version e.g. “Q5521_0.33.0.0 Display TV & Standby SW version and CTN serial
number
B. Standby processor version e.g. “STDBY_42.42.0.0”
C. Production code e.g. “see type plate”
Operation hours Displays the accumulated total of operation hours.TV
switched “on/off” & every 0.5 hours is increase one
Errors Displayed the most recent errors
Reset error buffer Clears all content in the error buffer
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be se-
lected
Warn
Cool
White point red LCD White Point Alignment. For values,
White point green see Table 6-4 White tone default setting 32" until 6-7
White tone default setting 42"
White point blue
Ambilight Select module
Brightness
Select matrix
TCON alignment used when a new display code (after a SSB
exchange) is keyed-in and if you have alignment
values from production; see Table 6-8 TCON default
settings
Reset TCON alignment used when a new display code (after a SSB
exchange) is keyed-in and if you do not have
alignment values from production
Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not
start up (once) with a language selection menu after
the mains switch is turned “on” for the first time (virgin
mode)
E-sticker Off/On Select E-sticker On/Off (USP’s on-screen)
Auto store mode None
PDC/VPS
TXT page
PDC/VPS/TXT

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Alignments Q552.1E LA 6. EN 45

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description


Options Digital broadcast DVB Off/On Select DVB On/Off
DVB - T installation Off/On or Country dependent Select DVB T installation On/Off or by country
DVB - T light Off/On Select DVB T light On/Off
DVB - C Off/On Select DVB C On/Off
DVB - C installation Off/On or Country dependent Select DVB C installation On/Off or by country
DVB - C light Off/On Select DVB C light On/Off
DVB - S Off/On Select DVB S On/Off
Over the air download Off/On or Country dependent Select Over the air download On/Off or by country
8 days EPG Off/On Select 8 day EPG On/Off
Digital features Ethernet Off/On Select Ethernet On/Off
Wi-Fi Off/On Select Wi-Fi On/Off
DLNA Off/On Select DLNA On/Off
On-line service On On-line service is On
Videostore SD card slot Off/On Select Videostore SD card slot On/Off
Multiview Off/On Select Multiview On/Off
Internet software update Off Internet software update is Off
Display Screen 237 / LCD Sharp D3GA23 46" Displayed the panel code & type model
LightGuide Off/On Select LightGuide On/Off
Display fans Not present/Present Select Display fans Present/Not present
Temperature sensor No sensor/On backside/In display/ Sensor present Yes/No and in case Yes, where
On SSB
Temperature LUT 0 N.A.
E-box & monitor Off/On Select E-box & monitor On/Off
Video reproduction Light sensor Off/On Select Light sensor On/Off
Light sensor type 0/1/2/3 Select Light sensor type form 0 to 3 (for difference
styling)
Super resolution Off/On Super resolution Off/On
Smart bit enhancement Off/On Smart bit enhancement Off/On
Pixel Plus type Pixel Plus HD Select type of picture improvement
Perfect Pixel HD
Pixel Precise HD
Natural motion type Perfect Natural Motion Natural motion type selection
HD Natural Motion
Ambilight None Select type of Ambilight modules use
2 sided 3/3
2 sided 4/4
2 sided 5/5
2 sided 6/6
2 sided 7/7
3 sided 5/5/5
3 sided 6/6/6
3 sided 7/7/7
3 sided 6/9/6
Ambilight sunset Off/On Ambilight sunset On/Off
Audio reproduction Acoustic system Cabinet design used for setting dynamic audio pa-
rameters
Source selection EXT1/AV1 type SCART CVBS RGB LR Select input source when connected with external
equipment
CVBS Y/C YPbPr LR
CVBS Y/C YPbPr HV LR
EXT2/AV2 type SCART CVBS RGB LR Select input source when connected with external
equipment
CVBS LR
YPbPr LR
None
EXT3/AV3 type None Select input source when connected with external
equipment
CVBS
CVBS LR
CVBS Y/C LR
YPbPr
YPbPr LR
YPbPr HV LR
SIDE I/O Off/On Select SIDE I/O On/Off
S-VIDEO (Y/C) Off/On Select S-VIDEO (Y/C) On/Off
HDMI 2 Off/On Select HDMI 2 On/Off
HDMI 3 Off/On Select HDMI 3 On/Off
HDMI side Off/On Select HDMI side On/Off
HDMI CEC Viewport 21:9 Off/On Select HDMI CEC Viewport 21:9 On/Off
HDMI CEC OneUX seamless Off/On Select HDMI CEC OneUX seamless On/Off
Miscellaneous Region Europe Select Region/country
AP-PAL-Multi
China
Australia
Latam
Russia
Tuner type Select type of Tuner used
Hotel mode Off Hotel mode is Off

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EN 46 6. Q552.1E LA Alignments

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description


Option numbers Group 1 e.g. “00008.01793.15421.08192” The first line (group 1) indicates hardware options 1
to 4
Group 2 e.g. “44013.34315.00000.00000” The second line (group 2) indicates software options
5 to 8
Store Store after changing
Initialise NVM N.A.
Store Select Store in the SAM root menu after making any
changes
Operation hours display 0003 In case the display must be swapped for repair, you
can reset the “”Display operation hours” to “0”. So,
this one does keeps up the lifetime of the display it-
self (mainly to compensate the degeneration behav-
iour)
Software maintenance Software events Display Display information is for development purposes
Clear
Test reboot
Test cold reboot
Test application crash
Hardware events Display Display information is for development purposes
Clear
Test setting Digital info Centre frequency: 774605208
QAM modulation: None Display information is for development purposes
Symbol rate:
Original network ID: 0
Network ID: 0
Transport stream ID: 0
Service ID: 0
Hierarchical modulation: 0
Selected video PID: 0
Selected main audio PID: 0
Selected 2nd audio PID: 0
Install start frequency 000 Install start frequency from “0” MHz
Install end frequency 999 Install end frequency as “999” MHz
Default install frequency
Installation Digital only Select Digital only or Digital + Analogue before instal-
lation
Digital + Analogue
Development file ver- Development 1 file version Display parameters DISPT6.0.9.8 Display information is for development purposes
sions Acoustics parameters ACSTS
0.39.6.16
PQ - TV550 1.0.22.1
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM 5.0.2.4
Development 2 file version 12NC one zip software Display information is for development purposes
Initial main software
NVM version Q55x1_0.3.1.0
Flash units software
Temp com file version none
Upload to USB All To upload several settings from the TV to an USB
Channel list stick
Personal settings
Option codes
Alignments
Identification data
History list
Download from USB All To download several settings from the USB stick to
Channel list the TV
Personal settings
Option codes
Alignments
Identification data
NVM editor Type number see type plate NVM editor; re key-in type number and production
AG code see type plate code after SSB replacement

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Circuit Descriptions Q552.1E LA 7. EN 47

7. Circuit Descriptions
Index of this chapter: 7.1 Introduction
7.1 Introduction
7.2 Power Architecture
The Q552.1E LA chassis is part of the TV550 platform and
7.3 DC/DC Converters
comes with the following stylings: “Rembrandt” (series
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception xxPFL54xx), “van Gogh” (series xxPFL56xx), and “Matisse”
7.5 Front-End DVB-S(2) reception
(series xxPFL76xx). The TV550 platform is the successor of
7.6 HDMI
the TV543 platform.
7.7 Video and Audio Processing - PNX85500
7.8 Back-End
7.1.1 Implementation
7.9 Ambilight
7.10 TCON
Key components of this chassis are:
Notes: • PNX85500 System-On-Chip (SOC) TV Processor
• TX31XX Hybrid Tuner (DVB-T/C, analogue)
• Only new circuits (circuits that are not published recently)
• STV6110AT DVB-S tuner
are described.
• Figures can deviate slightly from the actual situation, due • SII9x87 HDMI Switch
• TPA312xD2PWP Class D Power Amplifier
to different set executions.
• LAN8710 Dual Port Gigabit Ethernet media access
• For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter controller.
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary, 7.1.2 TV550 Architecture Overview
you will find a separate drawing for clarification.
• For details about the chassis block diagrams refer to
chapter 9. Block Diagrams. An overview of the TV550
architecture can be found in Figure 7-1.

18770_244_100203.eps
100219

Figure 7-1 Architecture of TV550 platform - TCON integrated in display

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EN 48 7. Q552.1E LA Circuit Descriptions

18770_245_100203.eps
100219

Figure 7-2 Architecture of TV550 platform - TCON integrated on SSB

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Circuit Descriptions Q552.1E LA 7. EN 49

7.1.3 SSB Cell Layout

1M 20 1M 71 1 M 59 2D D IM 1M 3 6 1G 51 1G 50

F LASH
D D R2 FPGA

L O W P RO F IL E
1M99

D C /D C

CA
D D R2
LVD S - O U T
S D- S L O T

D DR
CA
PN X85500
M1
27 x27 TS - IN
USB
1.00 m m
1M 9 5

20,00 H D MI

D D R2 E TH G P IO

I²S ANA ANA S TD B Y


S P D IF AUD V ID
C la ss -

1
7 D D R2
USB
2 .0
D

3
5

NO S P LIT TE R !!!
1 R J4 5
D
3 ser v
8
USB

Tuner
2 .0
Pb

S ca rt2 /Y P b P r
Pr

L /R
Y

R
L
HD
CT RL
MI
OUT

1 .3
9187

3
0

1 2

S ca rt1 /Y P b P r SPO
VGA
HD

HD

HD
1 .3

1 .3

1 .3
MI

MI

MI

18770_246_100203.eps
100203

Figure 7-3 SSB layout cells (top view) (non-DVBS without TCON)

1 M20 1M 71 1 M59 2 D D IM 1M36 1 G 51 1G 50

D V B -S D V B -S

Quad LVDS

1 M20 1M 71 1 M59 2D D IM 1M36 1 G 51 1G 50


FLASH

D D R2
FPGA
LO W P RO F IL E
1M99

D C /D C
CA

D D R2
LVD S -O U T
S D -S L O T
D DR

CA
PN X85500
M1
27 x27 T S -IN
USB
1.00 m m
1 M 95

20,00 H D MI

D D R2 E TH G P IO

I²S ANA ANA S TD B Y


S P D IF AUD V ID
C lass-

1
7 D D R2
USB
2.0
D

3
5
NO S P LIT T ER !!!

1 R J4 5
D
3 serv
8
USB
T uner

2.0

S ca rt2 /Y P b P r
Pb
Pr

L /R
Y

R
L

HD
CT RL
MI
OUT

1 .3
9187

3
0

1 2

S ca rt1 /Y P b P r SPO
VGA
HD

HD

HD
1 .3

1 .3

1 .3
MI

MI

MI

18770_247_100203.eps
100219

Figure 7-4 SSB layout cells (top view) (DVBS without TCON)

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EN 50 7. Q552.1E LA Circuit Descriptions

1 M20 1M 71 1 M59 2 D D IM 1M36 1 G 51 1G 50

TDC ON
V B -S
Quad LVDS

1 M20 1M 71 1 M59 2D D IM 1M36 1 G 51 1G 50

FLASH
D D R2
FPGA

LO W P RO F IL E
1M99

D C /D C

CA
D D R2
LVD S -O U T
S D -S L O T

D DR
CA
PN X85500
M1
27 x27 T S -IN
USB
1.00 m m
1 M 95

20,00 H D MI

D D R2 E TH G P IO

I²S ANA ANA


S TD B Y
S P D IF AUD V ID
C lass-

1
7 D D R2
USB
2.0
D

3
5

NO S P LIT T ER !!!
1 R J4 5
D
3 serv
8
USB

T uner
2.0

S ca rt2 /Y P b P r
Pb
Pr

L /R
Y

R
L

HD
CT RL
MI
OUT

1 .3
9187

3
0

1 2

S ca rt1 /Y P b P r SPO
VGA
HD

HD

HD
1.3

1.3

1.3
MI

MI

MI

18770_248_100203.eps
100219

Figure 7-5 SSB layout cells (top view) (non-DVBS with TCON)

2010-Feb-19 back to
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Circuit Descriptions Q552.1E LA 7. EN 51

7.2 Power Architecture

Refer to figure Figure 7-6 for the power architecture of this


platform.

18770_234_100127.eps
100127

Figure 7-6 Power Architecture TV550 platform

7.2.1 Power Supply Unit • Output to the display; in case of


- IPB: High voltage to the LCD panel
All power supplies are a black box for Service. When defective, - PSL and PSLS (LED-driver outputs)
a new board must be ordered and the defective one must be - PSDL (high frequent) AC-current.
returned, unless the main fuse of the board is broken. Always
replace a defective fuse with one with the correct 7.2.2 Diversity
specifications! This part is available in the regular market.
Consult the Service website for the order codes of the boards. The diversity in power supply units is mainly determined by the
diversity in displays. Table 7-1 Supply diversity lists the
Important delta’s with the TV543 platform are: different types of displays with its associated PSUs:
• New power architecture for LED backlight (PSL, PSLS,
PSDL) Table 7-1 Supply diversity
• “Boost”-signal is now a PWM-signal + continuous variable.
CTN Supplier PSU
The control signals are: 32PFL5405H/xx LGIT PLHC-P981A B
• Standby 32PFL5605H/xx Delta DPS-138BP A
• Lamp “on/off” 32PFL7605H/xx Delta DPS-199DP-1A
• DIM (PWM) (not for PSDL) 37PFL5405H/xx LGIT PLHD-P982A
• Boost (PWM except for IPB) 40PFL5605H/xx Delta DPS-206CP A
• Power-OK: indicates that the main converter is functioning 40PFL7605H/xx Delta DPS-199DP A
(feedback signal to the SSB). 42PFL5405H/xx LGIT PLHF-P983A

In this manual, no detailed information is available because of


The following displays can be distinguished:
design protection issues.
• CCFL/EEFL backlight: power board is conventional IPB
• LED backlight:
The output voltages to the chassis are: - side-view LED without scanning: PSL power board
• +3V3-STANDBY (standby-mode only) - side-view LED with scanning: PSLS power board
• +12V (on-mode) - direct-view LED without 2D-dimming: PSL power board
• +Vsnd (+24V) (audio power) (on-mode) - direct-view LED with 2D-dimming: PSDL power board.
• +24V (bolt-on power) (on-mode)

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EN 52 7. Q552.1E LA Circuit Descriptions

PSL stands for Power Supply with integrated LED-drivers. • a +24V under-voltage detection circuitry is built around
PSLS stands for a Power Supply with integrated LED-drivers item no. 7T04
with added Scanning functionality (added microcontroller). • the switching frequency of the 24 to 14...20V switched
PSDL stands for a Power Supply for Direct-view LED backlight mode converter is 350 kHz (item no. 7T03 and +V-LNB
with 2D-dimming. lines)
• the output signal on the +V-LNB line goes to the LNBH23Q
7.2.3 Connector overview (item no. 7T50)
• the LNBH23Q (item no. 7T50) sends a feedback signal via
Table 7-2 Connector overview the V0-CNTRL line
• the switching frequency of the +5V-DVBS to +1-DVBS
switched mode converter is 900 kHz (item no. 7T00)
Connector
• a delay line for the +2V5-DVBS and +1V-DVBS lines is
no. 1308 1311 1319 1316 1M95 1M99 1M09 1MP1
created with item no. 3T03 (R=10k) and 2T06 (C=100n)
Descr. mains mains disp. disp. to SSB to SSB Amb. T-con
• a 3.3V to 2.5V linear stabilizer is built around item no. 7T01
Pin CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8
• a 5V to 3.3V linear stabilizer is built around item no. 7T02.
1 N L’ 3V3std +12V 24Vb +12V
2 L L” Stndby +12V 24Vb +12V
3 - - - - GND1 GND1 GND1 n.c.
Diagram B08B contains the DVB-S2 LNB supply:
4 - - - - GND1 GND1 GND1 GND1
• the +V-LNB signal comes from item no. 7T03
5 - - - - GND1 BL_ON - GND1
• the V0-CTRL signal goes to item no. 7T03
_OFF • the LNB-RF1 goes to the LNB.
6 - - - - +12V DIM - -
7 - - - - +12V Boost - - Figures gives a graphical representation of the DC/DC
8 - - - - +12V n.c. - - converters with its current consumptions:
9 - - - - +Vsnd POK - -
10 - - - - GND_ - - -
SND
11 - - - - n.c. - - -
12 - - - - - - - -

7.3 DC/DC Converters

The on-board DC/DC converters deliver the following voltages


(depending on set execution):
• +3V3-STANDBY, permanent voltage for the standby
controller, LED/IR receiver and controls; connector 1M95
pin 1
• +12V, input from the power supply for TV550 common 18770_225_100127.eps
100219
(active mode); connector 1M95 pins 6, 7 and 8
• +24V, input from the power supply for DVB-S2 (in active Figure 7-7 DC/DC converters xxPFL5xxx series
mode); connector 1M09 pins 1 and 2
• +1V1, core voltage supply for PNX85500; has to be started
up first and switched off last (diagram B03B)
• +1V2, supply voltage for analogue blocks inside
PNX85500
• +1V8, supply voltage for DDR2 (diagram B03B)
• +2V5, supply voltage for analogue blocks inside
PNX85500 (see diagram B03E)
• +3V3, general supply voltage (diagram B03E)
• +5V, supply voltage for USB and CAM (diagram B03E)
• +5V-TUN, supply voltage for tuner (diagram B03E)
• +V-LNB, input voltage for LNB supply IC (item no. 7T50)
• +5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)
• +3V3-DVBS, clean voltage for silicon tuner and DVB-S2
channel decoder 18770_226_100127.eps
100219
• +2V5-DVBS, clean voltage for DVB-S2 channel decoder
• +1V-DVBS, core voltage for DVB-S2 channel decoder.
Figure 7-8 DC/DC converters xxPFL6xxx series

A +12 V under-voltage detector (see diagram B03C) enables


the 12V to 3.3V and 12V to 5V DC/DC converters via the
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter
via the ENABLE-1V8 line. DETECT2 is the signal going to the
standby microcontroller and ENABLE-3V3n is the signal
coming from the standby microcontroller.

Diagram B03D contains the following linear stabilizers:


• +2V5 stabilizer, built around item no. 7UCO
• +5V-TUN stabilizer, built around items no. 7UA6 and 7UA7
• +1V2 stabilizer, built around items no. 7UA3 and 7UA4. 18770_227_100127.eps
100219
Diagram B08A contains the DVB-S2-related DC/DC
converters and -stabilizers: Figure 7-9 DC/DC converters DVB-S2 devices

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Circuit Descriptions Q552.1E LA 7. EN 53

7.4 Front-End Analogue and DVB-T, DVB-C; • Channel decoder; I2C address 0xD0
ISDB-T reception • LNB switching regulator; I2C address 0x14
• Amplifier
• PNX85500 SoC TV processor with integrated DVB-T and
7.4.1 European/China region
DVB-C channel decoder and analogue demodulator.

The Front-End for the European/China region consist of the


Below find a block diagram of the front-end application for
following key components: DVB-S(2) reception.

• Hybrid Tuner
• Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
(8 MHz) (China)
• Bandpass filter
• Amplifier
• PNX85500 SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for this


region.

18770_237_100127.eps
100219

Figure 7-12 Front-End block diagram DVB-S(2) reception

This application supports the following protocols:


• polarization selection via supply voltage (18V = horizontal,
13V = vertical)
• band selection via “toneburst” (22 kHz): tone “on” = “high”
band, tone “off” = “low” band
• satellite (LNB) selection via DiSEqC 1.0 protocol
18770_235_100127.eps
100219 • reception of DVB-S (supporting QPSK encoded signals)
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and
Figure 7-10 Front-End block diagram European/China region 32APSK encoded signals), introducing LDPC low-density
parity check techniques.
7.4.2 Brazil region
7.6 HDMI
The Front-End for the Brazil region consist of the following key
components: In this platform, the Silicon Image Sil9x87 HDMI multiplexer is
implemented. Refer to figure 7-13 HDMI input configuration for
• Hybrid Tuner with integrated SAW filter and amplifier the application.
• External ISDB-T channel decoder covering the Brazilian
digital terrestrial TV standard
• Bandpass filter
• Amplifier
• PNX85500 SoC TV with integrated analogue demodulator.

Below find a block diagram of the front-end application for this


region.

18770_236_100127.eps
100219

Figure 7-11 Front-End block diagram Brazil region

18770_243_100203.eps
7.5 Front-End DVB-S(2) reception 100203

The Front-End for the DVB-S(2) application consist of the Figure 7-13 HDMI input configuration
following key components:
The following multiplexers can be used:
• Satellite Tuner; I2C address 0xC6 (bridged via channel • Sil9187A (does not support “Instaport” technology for fast
decoder) switching between input signals)

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EN 54 7. Q552.1E LA Circuit Descriptions

• Sil9287B (supports “Instaport” technology for fast • High definition ME/MC


switching between input signals). • 2D LED backlight dimming option
The hardware default I2C addresses are: • Embedded HDMI HDCP keys
• Sil9187A: 0xB0/0xB2 (random: software workaround) • Extended colour gamut and colour booster
• Sil9287B: 0xB2 (fixed). • Integrated USB2.0 host controller
• Improved MPEG artefact reduction compared with
The Sil9x87 has the following specifications: PNX8543
• +5V detection mechanism • Security for customers own code/settings (secure flash).
• Stable clock detection mechanism
• Integrated EDID The TV550 combines front-end video processing functions,
• RT control such as DVB-T channel decoding, MPEG-2/H.264 decode,
• HPD control analog video decode and HDMI reception, with advanced
• Sync detection back-end video picture improvements. It also includes next
• TMDS output control generation Motion Accurate Picture Processing (MAPP2). The
• CEC control MAPP2 technology provides state-of-the-art motion artifact
• EDID stored in Sil9x87, therefore there are no EDID pins reduction with movie judder cancellation, motion sharpness
on the SSB. and vivid colour management. High flat panel screen
resolutions and refresh rates are supported with formats
including 1366 × 768 @ 100Hz/120Hz and 1920 × 1080 @
7.7 Video and Audio Processing - PNX85500 100Hz/120Hz. The combination of Ethernet, CI+ and H.264
supports new TV experiences with IPTV and VOD. On top of
The PNX85500 is the main audio and video processor (or that, optional support is available for 2D dimming in
System-on-Chip) for this platform. It has the following features: combination with LED backlights for optimum contrast and
power savings up to 50%.
• Multi-standard digital video decoder (MPEG-2, H.264,
MPEG-4) For a functional diagram of the PNX85500, refer
• Integrated DVB-T/DVB-C channel decoder to Figure 7-14.
• Integrated CI+
• Integrated motion accurate picture processing (MAPP2)

PNX85500x
MEMORY
CONTROLLER

TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)

DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT

Low-IF DIGITAL IF MPEG/H.264


VIDEO Motion-accurate
DECODER pixel processing

SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION

AUDIO DACS analog audio


SPDIF AUDIO IN
AUDIO DSP
I 2S
AUDIO OUT
HDMI SPDIF
HDMI 450 MHz
RECEIVER AV-DSP

SYSTEM 560 MHz DRAWING


CONTROLLER MIPS32 ENGINE
(8051) 24KEf CPU

DMA BLOCK

I2C PWM GPIO IR ADC SPI UART I2C GPIO Flash USB 2.0 SD Ethernet
x8 Memory MAC
Card

18770_241_100201.eps
100219

Figure 7-14 PNX85500 functional diagram

2010-Feb-19 back to
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Circuit Descriptions Q552.1E LA 7. EN 55

7.8 Back-End

The following backlight types can be distinguished:


• CCFL/EEFL backlight; applicable to the xxPFL54xx sets
• LED backlight:
- side-view (edge) LED without scanning: PSL power
board; applicable to xxPFL76xx sets
- side-view (edge) LED with scanning: PSLS power board;
not applicable to this chassis
- direct-view LED with 0D-dimming: PSL power board;
applicable to xxPFL56xx sets
- direct-view LED with 2D-dimming: PSDL power board;
not applicable to this chassis.

Refer to section 7.2.2 Diversity for an in-depth explanation of


the different power boards that are used.

18770_242_100203.eps
100203

Figure 7-15 Backlight (xxPFL54xx, xxPFL56xx, xxPFL76xx sets)


application

7.9 Ambilight

In this chassis, only 2-sided Ambilight is implemented. Refer to


figure 7-16 Ambilight architecture.

1
MTK 1 1 1 1
Glue M
or M M M M
logic 5 AmbiLight AmbiLight
PNX85500 8 8 8 8
9
3 4 3 4

SSB
1M09

1M09

PSU

18770_209a_100202.eps
100202

Figure 7-16 Ambilight architecture

For an overview of the LED grouping per board, refer to figure


7-17 LED grouping per board.

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EN 56 7. Q552.1E LA Circuit Descriptions

+3V3

2B17

100n
7B20-1
74LVC2G17

5
6 PWM-CLOCK 2 3B01-2 7 1 6 1 3B30-1 8 PWM-CLOCK-BUF

× 100R 220R

2B00
6 5 3

2
33p

2B02

100p
L × ×
E 6 4 5 2
7B20-2
D L × L × 74LVC2G17
+3V3
E 6 3 E 6 4

5
D L × D L + SPI-CLOCK 1
3B01-1
8 3 4 4
3B30-4
5 SPI-CLOCK-BUF
100R 220R
E 6 E 5

2B01

2
33p
D D

2B10

100p
L L
E E
D D
18770_214_100126.eps
100126
36 30 24 18 15 12 9
Figure 7-20 Ambilight buffer

18770_210_100126.eps
100126 The temperature sensor is built around item no. 7B30 (diagram
AL1A) and indicates overtemperature of the board. Refer to
Figure 7-17 LED grouping per board figure 7-21 Temperature sensor.

The communication between PNX85500, Complex 3B34


Programmable Logic Device (CPLD) and the Ambilight module +3V3 +3V3
100K RES
uses the SPI protocol; refer to figure 7-18 Communication +3V3
7

6
protocol outside LED board. Between the CPLD and the LED
1K5 1%

1K5 1%
3B39-2

3B39-3
driver, as “extra” line is mentioned: 7B30
2

3
FB40
• Non-SPI signals that are required for the LED driver

5
1
4 TEMP-SENSOR
• Temperature sensor line. 3
LMV331IDCK
RES

2
2B08

3004
10K

10n
3B11

10K
-T

FB41
SPI S P I + e x tra
1M 59

C P LD
1K5 1%

PNX
3B39-1
2B09

10n
8

18770_211_100126.eps 18770_215_100126.eps
100126 100126

Figure 7-18 Communication protocol outside LED board Figure 7-21 Temperature sensor

Refer to figure for an overview of the communication inside the The EEPROM (item no. 7B07; diagram AL1A) contains
LED board. alignment information about the mounted LEDs and is
programmed during the alignment process in production. Refer
to figure 7-22 EEPROM.
E x tra

+3V3

SPI SPI SPI


LE D
2B20

100n

B uffer SPI-DATA-IN-BUF
D river
1M 84
1M 83

SPI-CLOCK-BUF
7B07
8

M95010-WDW6
+3V3 VCC

Tem p EEPRO M
7B06
5
D Φ Q
2

74LVC1G32GW 6 (64K)
5

sensor SPI-CS 1
C
4 1 3B02-2
S
Te m p SPI DATA-SWITCH 2
+3V3 HOLD
7 +3V3
1 3B02-1 8 3 7 10K 2
W
3

SPI 10K
GND
4

18770_213_100126.eps SPI-DATA-RETURN

100219
18770_216_100126.eps
100126
Figure 7-19 Communication protocol inside LED board
Figure 7-22 EEPROM
The buffer is built around item no. 7B20 (diagram AL1A) and
regenerates the clock signals. Refer to figure 7-20 Ambilight
The LED driver is built around item no. 7B26 (diagram AL1A)
buffer.
and controls the LEDs. Refer to figure 7-23 LED driver.

2010-Feb-19 back to
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Circuit Descriptions Q552.1E LA 7. EN 57

+3V3

2B11

100n

7B26-1

27
TLC5946RHB
3B00-1 VCC
BLANK 1 8 31 4 PWM-R1
BLANK 0
PWM-CLOCK-BUF 150R 24 5 PWM-G1
GSCLK 1
3B18 26 6 PWM-B1
IREF 2
1K8 FB35 3 7 PWM-G3
MODE 3
PROG 4 3B00-4 5 1 8 PWM-R3
SCLK 4
SPI-CLOCK-BUF 150R 2 9 PWM-R2
SIN 5
SPI-DATA-IN-BUF 23 10 PWM-G2
SOUT 6
SPI-DATA-IN 3 6 11 PWM-B2
7
SPI-DATA-OUT 3B00-3 150R 3B21 150R 22 OUT 14 PWM-B3
XERR 8
FB20 +3V3 3B22 25 15 PWM-G4
XHALF 9
LATCH 2 3B00-2 7 10K 32 16 PWM-R4
XLAT 10
150R 17 PWM-B4
11
12 18 PWM-B5
12
13 19 PWM-G5
13
7

6
28 NC 20 PWM-R5
2B04-2

2B04-1

2B04-4

2B04-3
14
100p

100p

100p

100p
29 21 DATA-SWITCH
15
3B31
GND GND_HS +3V3
2

30

33
2K0
7B26-2
TLC5946RHB
34 VIA 42
35 41
VIA VIA
36 40
VIA

37
38
39
18770_217_100126.eps
100126

Figure 7-23 LED driver

The Overvoltage Protection Circuit is built around item no.


7B50, 7B51, 7C20 and 7C22 (diagram AL1B). Refer to figure
7-24 Overvoltage Protection Circuit.

+24V
8 3B07-1 1

7B23-1
10K

BC847BS(COL)
6

2
2 3B07-2 7

1
10K

FB30
PWM-B1
3B35
+24V
+24V 7000 7001 7002 7003 7004 7005
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 270R
3B36
5 3B07-4 4

7B23-2 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R


10K

BC847BS(COL)
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 3B37

68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
3 3B07-3 6

4
10K

1 3B03-1 8
FB31 1K5
PWM-R1
3B03-2
2 7
+24V
1K5

3 3B03-3 6
3 3B13-3 6

1K5
7B25
10K

BC847BW 3 3B03-4
4 5
1K5
1
2B03

100n
5 3B13-4 4

2
10K

FB32
PWM-G1

18770_218_100126.eps
100126

Figure 7-24 Overvoltage Protection Circuit

7.10 TCON

This section describes the application with the TCON


integrated on the SSB.

For the basic application, refer to figure 7-25 TCON


architecture.

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EN 58 7. Q552.1E LA Circuit Descriptions

EEPROM

LVDS (10 bit)


Timing Mini - LVDS
Controller

Control
PNX8550

Signals
Gamma
Reference Source Drive IC
Voltage
+3.3 V
+1.8 V

+16 V

Gate Drive IC
+12 V Power TFT – LCD Panel
Block
VGH (+28 V)
VGL (-6 V)

M ain P latform TCO N

LC D P anel
SSB
18770_238_100127.eps
100127

Figure 7-25 TCON architecture

For the TCON block diagram, refer to figure 7-26 TCON block
diagram.

LVDS T im in g C o n tro lle r IC M in i-


Input S p re a d SDRAM LVDS
S p e c tru m Output
1 6 bit
Form atter/S erializer

R 1 A ~E D a ta M ini-LVDS
LV D S P a th Transmitter
R e c e iv er B lo c k
R 1C LK
(L in e
B u ffer)
OPC ODC DCA RLV P /N
M ini-LVDS
(Optimum

(Dynamic

Transmitter
Contrast
Control)

Control)
Circuit)
Power

(Over

Right h alf
Drive

data
R 2 A ~E

LV D S Gate D river
C trl S ign als
R 2C LK R e c e iv er
Ve rtic a l & H o rizo n ta l
Tim in g g e n e ra tio n Source D river
C trl S ign als

I2 C ROM H s y n c/ Control
I2 C
S lav e M aster Vsync Signal
S S C L K (S p re a d Spectrum C lo c k) Output
DE

EEPROM

18770_239_100127.eps
100127

Figure 7-26 TCON block diagram

2010-Feb-19 back to
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Circuit Descriptions Q552.1E LA 7. EN 59

Notes to figure 7-26 TCON block diagram: • Timing Control Function: generates control signals to
• LVDS receiver: converts the data stream back into RGB column drivers and row drivers (Source Enable - SOE,
data and SYNC signals (Vsync, Hsync, Data Enable - DE) Gate Enable - GOE, Gate Start Pulse - GSP).
• ODC: Over Drive Circuit - to improve LC response For an overview of the TCON DC/DC converters, refer to figure
• Data Path Block: the video RGB data input to data path 7-27 TCON DC/DC converters.
block is delayed to align the column driver start pulse with
the column driver data

LGD SHP W h ere U sed

To G a te D riv e rs (G a te
VGH +2 8 V +3 5 V
H ig h Vo lta g e )
D C /D C
+ 12V C o n tro lle r To G a te D riv e rs (G a te
VGL -6 V -6 V
L o w Vo lta g e )
Tim in g C o n tro lle r IC
Vcc +3 V 3 +3 V 3
S u p p ly Vo lta g e
Tim in g C o n tro lle r IC
Vcc +1 V 8 +1 V 2
S u p p ly Vo lta g e
G a m m a R e fe renc e
Vre f +1 6 V +1 5 V 2
Vo lta g e

S o u rc e D riv e r S u p p ly
Vdd +1 6 V +1 5 V 6
Vo lta g e

18770_240_100128.eps
100128

Figure 7-27 TCON DC/DC converters

7.10.1 TCON Programming

For LGD - TCONs, the EEPROM can be programmed via


ComPair (via I2C communication).
For Sharp - TCONs, the data can be flashed with a “SPI
Programmer” (via SPI communication). This device has to be
ordered separately.

7.10.2 TCON Alignment

The purpose of TCON alignment is to obtain equal voltages for


both positive and negative LC polarity. This is to avoid “flicker”
and “image sticking”.

The alignment value for the TCON is stored in the main


software and is automatically set to the correct value when you
enter the display code via the service menu. No manual
alignment is needed.

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EN 60 8. Q552.1E LA IC Data Sheets

8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of “memory” and “logic”
configurations of ICs that are drawn as “black boxes” in the ICs).

8.1 Diagram USB Hub B01C, USB2513B (IC 7F25)

Block diagram
To EEPROM or
To Upstream Upstream SMBus Master
24 MHz
VBUS USB Data SDA SCL
Crystal
3.3 V

Bus- Serial
Power Upstream Regulator PLL Interface
Detect/ PHY
Vbus Pulse
Serial
Repeater Interface Controller
Engine

3.3 V

Regulator
TT
#1
... TT
#x
Port
Controller

CRFILT

Routing & Port Re-Ordering Logic

PHY#1
Port #1
OC Sense
Switch Driver/
LED Drivers
... PHY#x
Port #x
OC Sense
Switch Driver/
LED Drivers

USB Data OC Port USB Data OC Port


Downstream Sense Power Downstream Sense Power
Switch/ Switch/
LED LED
Drivers Drivers

The ‘x’ indicates the number of available downstream ports: 2, 3, 4, or 7.


Note : The LED port indicators only apply to USB2513i.

Pinning information
SDA / SMBDATA / NON_REM[1]
SCL / SMBCLK / CFG_SEL[0]
HS_IND / CFG_SEL[1]
VBUS_DET

RESET_N

VDD33

NC

NC

NC
27
26
25
24
23
22
21
20
19

SUSP_IND / LOCAL_PWR / NON_REM[0] 28 18 NC

VDD33 29 17 OCS_N[2]

USBDM_UP 30 16 PRTPWR[2] / BC_EN[2]*

USBDP_UP 31
SMSC 15 VDD33
USB2512/12A/12B
XTALOUT 32 14 CRFILT
USB2512i/12Ai/12Bi
XTALIN / CLKIN 33 13 OCS_N[1]
(Top View QFN-36)
PLLFILT 34 12 PRTPWR[1] / BC_EN[1]*
Ground Pad
RBIAS 35 (must be connected to VSS) 11 TEST

VDD33 36 10 VDD33
1
2
3
4
5
6
7
8
9
USBDM_DN[1]

USBDM_DN[2]
USBDP_DN[1]

USBDP_DN[2]

VDD33

NC

NC

NC

NC

Indicates pins on the bottom of the device.

18770_301_100217.eps
100217

Figure 8-1 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 61

8.2 Diagram Temp Sensor + Headphone B01J, LM75BDP (IC 7FD1)

Block diagram
VCC

LM75B
BIAS POINTER CONFIGURATION
REFERENCE REGISTER REGISTER

TEMPERATURE
BAND GAP COUNTER
REGISTER
TEMP SENSOR 11-BIT
SIGMA-DELTA
A-to-D TOS
TIMER
CONVERTER REGISTER
OSCILLATOR
COMPARATOR/ THYST
INTERRUPT REGISTER
POWER-ON
RESET OS

LOGIC CONTROL AND INTERFACE

A2 A1 A0 SCL SDA GND

Pinning information

SDA 1 8 VCC
SCL 2 7 A0
LM75BDP
OS 3 6 A1
GND 4 5 A2

18770_300_100217.eps
100217

Figure 8-2 Pin configuration

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EN 62 8. Q552.1E LA IC Data Sheets

8.3 Diagram PNX NandFlash - Conditional Access B02A, PNX85500 (IC7S00)

Block diagram

PNX8550x
MEMORY
CONTROLLER

TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)

DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO analog CVBS
VIDEO ENCODER
OUTPUT analog Y/C
Low-IF
DIGITAL IF MULTI-
Direct-IF STANDARD Motion-accurate
VIDEO pixel processing
DECODER

SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION

AUDIO DACS analog audio


SPDIF AUDIO IN
AUDIO DSP
I2S
AUDIO OUT
HDMI SPDIF
HDMI 450 MHz
RECEIVER AV-DSP

SYSTEM 500 MHz DRAWING


CONTROLLER MIPS32 ENGINE
(8051) 24KEf CPU

Scatter/Gather
TS Demux

I2C PWM Px_x IR ADC SPI UART I2C GPIO Flash USB 2.0 SD Ethernet
x 10 Memory MAC
Card

Pinning information
ball A1 PNX8550xE
index area 2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF

Transparent top view


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100217

Figure 8-3 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 63

8.4 Diagram Audio B03A, TPA3120D2PWP (IC7D10)

Block Diagram

TPA3120D2
1 F
0.22 F
LIN BSR
22 H 470 F
RIN ROUT
1 F 0.68 F
PGNDR

PGNDL 0.68 F
1 F
BYPASS LOUT
22 H 470 F
AGND BSL
0.22 F

PVCCL
AVCC
PVCCR

VCLAMP
Shutdown
SD 1 F
Control

MUTE
GAIN0

GAIN1
} Control

Pin Configuration
PWP (TSSOP) PACKAGE
(TOP VIEW)

PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR
I_18020_142.eps
190908

Figure 8-4 Internal block diagram and pin configuration

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EN 64 8. Q552.1E LA IC Data Sheets

8.5 Diagram DC/DC B03B, TPS53126PW (IC7U03)

Block Diagram

Pin Configuration
VBST1 1 28 DRVH1
NC 2 27 LL1
EN1 3 26 DRVL1
VO1 4 25 PGND1
VFB1 5 24 TRIP1
NC
TPS53124

6 23 VIN
GND 7 22 VREG5
TEST1 8 21 V5FILT
NC 9 20 TEST2
VFB2 10 19 TRIP2
VO2 11 18 PGND2
EN2 12 17 DRVL2
NC 13 16 LL2
VBST2 14 15 DRVH2

18250_300_090319.eps
090319

Figure 8-5 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 65

8.6 Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

Block Diagram

Pin Configuration

DFN8 (4x4) PowerSO-8


I_18010_083.eps
130608

Figure 8-6 Internal block diagram and pin configuration

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EN 66 8. Q552.1E LA IC Data Sheets

8.7 Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

Block Diagram Pin Configuration


LD1117DT

DPAK

F_15710_166.eps
230905

Figure 8-7 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 67

8.8 Diagram Ethernet + Service B04C, LAN8710A-EZKH (IC 7E10)

Block diagram
MODE0 HP Auto-MDIX
MODE1 Auto- 10M Tx 10M
MODE Control
MODE2 Negotiation Logic Transmitter TXP / TXN
Reset Transmit Section
nRST Control RXP / RXN
Management 100M Tx 100M
RMIISEL SMI Logic Transmitter
Control
MDIX
Control
TXD[0:3] XTAL1/CLKIN
TXEN PLL
100M Rx DSP System: Analog-to-
TXER XTAL2
TXCLK Logic Clock Digital
Data Recovery
Interrupt
Equalizer nINT
Generator
RMII / MII Logic

RXD[0:3]
RXDV 100M PLL
RXER Receive Section
RXCLK LED1
LED Circuitry
LED2
10M Rx Squelch &
CRS Logic Filters
COL/CRS_DV
Central
RBIAS
MDC 10M PLL Bias
MDIO
PHY
Address PHYAD[0:2]
Latches

Pinning information
VDD1A
RBIAS

RXDV

TXD3
RXN
RXP

TXN
TXP
32

31

30

29

28

27

26

25

VDD2A 1 24 TXD2

LED2/nINTSEL 2 23 TXD1

LED1/REGOFF 3 22 TXD0
SMSC
XTAL2 4 LAN8710/LAN8710i 21 TXEN

XTAL1/CLKIN 5 32 PIN QFN 20 TXCLK

VDDCR 6
(Top View) 19 nRST

RXCLK/PHYAD1 7 18 nINT/TXER/TXD4
VSS
RXD3/PHYAD2 8 17 MDC
10

11

12

13

14

15

16
9
RXD2/RMIISEL

RXD1/MODE1

RXD0/MDE0

CRS

COL/CRS_DV/MODE2

MDIO
VDDIO

RXER/RXD4/PHYAD0

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100217

Figure 8-8 Internal block diagram and pin configuration

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EN 68 8. Q552.1E LA IC Data Sheets

8.9 Diagram HDMI B04D, SII9287B (IC 7EC1)

Block diagram

Pinning information

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Figure 8-9 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 69

8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

Block diagram

VDD 8

VDD/2
2 IN 1− VO1 1

+
3 BYPASS

6 IN 2−
− VO2 7
+

5 SHUTDOWN Bias 4
Control

Pinning information
D OR DGN PACKAGE
(TOP VIEW)

VO1 1 8 VDD
IN1− 2 7 VO2
BYPASS 3 6 IN2−
GND 4 5 SHUTDOWN

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100217

Figure 8-10 Internal block diagram and pin configuration

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EN 70 8. Q552.1E LA IC Data Sheets

8.11 Diagram Circuit Diagrams and PWB Layouts B07A, STV6110AT (IC 7R02)

Block diagram
RF_OUT

IP
RF_IN
IN
QP
AGC
QN

PLL, dividers DC offset compensation


SCL
XTAL_IN
XTAL_INN Amplifier I2C bus interface

XTAL_OUT SDA

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100217

Figure 8-11 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 71

8.12 Diagram Circuit Diagrams and PWB Layouts B08A, TPS54283PWP (IC 7T03)

Block diagram
2 BOOT1
BP
CLK1 Level
1 PVDD1
Shift
Current
f(IDRAIN1) + DC(ofst) Comparator
S Q
+
GND 4 R
R Q
+
f(IDRAIN1)
FB1 7 Overcurrent Comp
0.8 VREF + 3 SW1
RCOMP f(ISLOPE1) BP
f(IMAX1)

Soft Start Weak


SD1 CLK1 Pull-Down
1 CCOMP Anti-Cross
Conduction MOSFET

VDD2 f(ISLOPE1)
Ramp
Gen 1
TSD 1.2 MHz Divide CLK1
6 A 6 A Oscilator by 2/4 f(ISLOPE2)
EN1 5 SD1 Ramp
Gen 2
Internal
EN2 6 SD2 CLK2
Control
UVLO
150 k
SEQ 10 BP
FB1 Output
150 k Undervoltage 13 BOOT2
FB2 Detect
BP
CLK2 Level
14 PVDD2
Shift
Current
Comparator FET
f(IDRAIN2) + DC(ofst)
S Q Switch
+
GND 4 R
R Q
+
f(IDRAIN2)
FB2 8
Overcurrent Comp
0.8 VREF + 12 SW2
RCOMP f(ISLOPE2) BP
f(IMAX2)

Soft Start Weak


SD2 CLK2 Pull-Down
2 CCOMP Anti-Cross
Conduction MOSFET

5.25-V
BP 11 PVDD2
Regulator
150 k
BP
Level
ILIM2 9
Select

150 k 0.8 VREF


References
IMAX2 (Set to one of two limits)

UDG-07007

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100217

Figure 8-12 Internal block diagram and pin configuration

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EN 72 8. Q552.1E LA IC Data Sheets

8.13 Diagram Circuit Diagrams and PWB Layouts B08B, LNBH23Q (IC 7T50)

Block diagram
ISEL TTX ADDR SDA SCL Vcc Byp Vcc- L

LX
Preregulator
+U.V.lockout
+P.ON reset
Controller
PWM

Rsense EN

P-GND VSEL
VSEL
TTX EN

ITEST I2C interface


Vup
VOUT Control

TEN
Linear Post-reg
+Modulator
VoRX +Protections
+Diagnostics I2C Diagnostics

VoTX
22KHz
Oscill. 22KHz Tone
TTX DETIN
Amp. Diagn.
EXTM
22KHz Tone
Freq. Detector
DSQOUT
DSQIN

V CTRL LNBH23
A-GND

Pinning information
1 n.c .
2 n.c .
3 n.c .
4 LX
5 P -G N D
6 S DA Epad Connected with power grounds and to
7 n.c . the ground layer through vias
8 n.c .
to dissipate the heat.
9 S CL
10 A D DR
11 DS Q out
12 DS Q IN
13 E XTM
14 TTX
15 B Y P
16 n.c .
17 n.c .
18 V c c -L
19 V c c
20 A -G N D
21 V oRX
22 V oTX
23 n.c .
24 n.c .
25 n.c .
26 n.c .
27 V up
28 IS E L
29 D E TIN
30 V C TRL
31 n.c .
32 n.c .

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Figure 8-13 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 73

8.14 Diagram TCON Controller B11A, TL2429MC (IC 7J01)

Block diagram
RLV0~6P/M,
LLV0~6P/M
SOE,POL

LVDS
Input
Source Source Source Source
1RxA~E Driver 1 Driver 2 Driver 5 Driver 8
Internal
2RxA~E
SSIC
3RxA~E VST(GSP)
4RxA~E
ODC + OPC Gate Gate in
1RxCLK TCON Driver panel
2RxCLK 1 1
mini-LVDS
3RxCLK
GCLK1, … , GCLK3, … , GCLK6

4RxCLK Frame Memory


SDRAM Gate Gate in
Driver panel
2 2 TFT LCD ARRAY
SDA
SCL

EEPROM Gate Gate in


(LUT) Driver panel
16Kbit n n
or 32Kbit

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100217

Figure 8-14 Internal block diagram and pin configuration

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EN 74 8. Q552.1E LA IC Data Sheets

8.15 Diagram TCON Controller B11B, TPS62110RSA (IC 7JH1)

Block diagram
VI

Undervoltage +
Vina Lockout _
REF

Thermal
Shutdown
+
I AVG Comparator
_
REF

V V (COMP) 1-MHz
I Oscillator
P-Channel

Comparator S
+ Driver SW
R
_ Control Shoot-Through
Sawtooth
Logic Logic
Generator N-Channel

+
+
_
_ PG
SKIP Comparator +
_

+ _ LBO
Compensation R1
Gm
_ R2 +
+ +
_ _
EN REF

FB LBI P G ND GND
A. The internal feedback divider is disabled and the FB pin is directly connected
to the internal GM amplifier.

Pinning information
P G ND
SW
SW
PG

16 15 14 13
PGND 1 12 GND
Exposed
VIN 2 Thermal
11 GND
Pad
VIN 3 10 FB
EN 4 9 AGND
5 6 7 8
LBI
LBO

V IN A
S Y NC

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100217

Figure 8-15 Internal block diagram and pin configuration

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IC Data Sheets Q552.1E LA 8. EN 75

8.16 Diagram TCON Controller B11B, MAX17113ETL (IC 7JF1)

Block diagram
VIN (12V)

BST
IN2 VL

LX1

3.3V
2A LX2 STEP-UP
STEP-DOWN OSC
PGND

GND2 FB1
COMP
OUT

AGND
FSEL
VL
SWI

P
150mV SWO AVDD
FB2 16V
1.5A
VIN 3.3V
VIN

VL VL
VL PGOOD
PGOOD
RESET CRST

REF
REF REF
AGND DRN

STEP-DOWN, NEGATIVE EN1 THR


ON/OFF
EN2 MODE
STEP-UP, POSITIVE
CHARGE PUMP ON/OFF HV
DEL1 POWER-UP SWITCH
DEL2 SEQUENCE BLOCK CTL GON
CONTROL
DLP
GON VGON
35V
50% OSC SRC 50mA
VIN
VGOFF SWO
-6V DRVN DRVP
100mA NEGATIVE POSITIVE SRC
REG REG
CPGND CPGND

FBN FBP

AVDD

REF

Pinning information
PGND

DEL2

FSEL

OUT
EN2

EN1

IN2
IN2
VIN
VL

30 29 28 27 26 25 24 23 22 21
PGND 31 20 LX2
LX1 32 19 LX2
LX1 33 18 BST
TOP VIEW SWI 34 17 FB2
THIN QFN SWO 35 16 DEL1
FB1 36 MAX17113 15 REF
COMP 37 14 FBN
PGOOD 38 13 AGND
CRST 39 12 DRVN
AGND 40 11 CTL
1 2 3 4 5 6 7 8 9 10
MODE
GND2

CPGND
GON
DRN
DVRP
THR

DLP
FBP
SRC

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Figure 8-16 Internal block diagram and pin configuration

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EN 76 8. Q552.1E LA IC Data Sheets

8.17 Diagram TCON DC/DC B14B, ISL97653AIRZ (IC 7KFA)

Block diagram RSET HVS VREF PROT

HVS SAWTOOTH
CM1
LOGIC GENERATOR
GM AMPLIFIER
FBB - SLOPE LX1
+ COMPENSATION LX2
VREF BUFFER

CONTROL
Ε
UVLO COMPARATOR LOGIC
-
+
RSENSE
CURRENT PGND1
0.75 VREF AMPLIFIER PGND2

680kHz
FREQ
OSCILLATOR
VL

PVIN1,2 CURRENT LIMIT


REGULATOR
COMPARATOR
REFERENCE BIAS

CDEL AND
CURRENT LIMIT
EN SEQUENCE CONTROLLER THRESHOLD

VL
PVIN1,2 CB
SUPN

LXL1
LXL2
NOUT CONTROL
LOGIC
CURRENT
BUFFER CM2
LIMIT GM AMPLIFIER
COMPARATOR CURRENT AMPLIFIER
FBN - - FBL
+ - Ε +
+
0.2V VREF
CURRENT LIMIT SLOPE
THRESHOLD COMPENSATION
UVLO COMPARATOR
- SAWTOOTH
+ GENERATOR
0.4V

0.75 VREF LDO-CTL


LDO
- CONTROL
+ LOGIC2 LDO-FB

SUPP TEMP TEMP


FBP - SENSOR
+
VREF

POUT

SUPP

C1- C1+ POUT C2+ C2- DRN CTL COM

Pinning information
LDO-CTL

LDO-FB

PGND2

PGND1
AGND
PVIN1

TEMP
PROT

LX2

LX1

40 39 38 37 36 35 34 33 32 31

PVIN2 1 30 COMP

CB 2 29 FBB

LXL1 3 28 RSET

LXL2 4 27 HVS

PGND3 5 ISL97653A 26 EN
40 LD 6X6 QFN
PGND4 6 TOP VIEW 25 CDEL

CM2 7 24 CTL

FBL 8 23 DRN

VL 9 22 COM

VREF 10 21 POUT

11 12 13 14 15 16 17 18 19 20
PGND5

C1P

C2P

SUPP

FBP
FBN

SUPN

NOUT

C1N

C2N

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100217

Figure 8-17 Internal block diagram and pin configuration

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Block Diagrams Q552.1E LA 9. EN 77

9. Block Diagrams
9-1 Wiring diagram Rembrandt 32"
WIRING DIAGRAM 32" REMBRANDT

Board Level Repair

Component Level Repair


Only For Authorized Workshop

1M95 (B03C) 1M99 (B03C) 1735 (B03A) 1M20 (B09A) 1JA1 (B11C) 1JA2 (B11C)
1. +3V3-STANDBY 1. +12VD 1. LEFT-SPEAKER 1. LIGHT-SENSOR 1. GND 1. GND
2. STANDBY 2. +12VD 2. GND-AUDIO 2. GND | |
3. GND 3. GND 3. GND-AUDIO 3. RC 36. VCC 19. VDD
4. GND 4. GND 4. RIGHT-SPEAKER 4. LED-2 37. VCC 20. VDD
5. GND 5. LAMP-ON 5. +3V3-STANDBY | |
6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 41. VDD 24. VCC
7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 42. VDD 25. VCC
8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V | |
9. +24V-AUDIO-POWER 9. POWER-OK 60. GND 60. GND
10. GND-AUDIO
11. MAINS-OK

LOUDSPEAKER
(5213)
1316
1P3

1M99
9P
8M20
1M20 1JA2 1JA1
1M95
11P

8P

8JA1
60P 60P

8JA2
HIGH VOLTAGE

MAIN POWER SUPPLY SSB


1319
1P3

CONDITIONAL ACCESS
(1150)
IPB 32 PLHC-P981A B
(1005)

1M99
8M99

9P
1M95
KEYBOARD CONTROL

11P
8M95

1735
4P
2P3 2P3
1311 1308
N L

TUNER

USB
TO BACKLIGHT

TO BACKLIGHT

MAINS CORD
(1114)

8191

HDMI
HDMI

PHONE
HDMI HDMI VGA
3P
J1

SCART

8311

CN2 LCD DISPLAY CN1


(1004)
J2 J1 IR / LED BOARD MAINS
3P 8P (1112) SWITCH

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Block Diagrams Q552.1E LA 9. EN 78

9-2 Wiring diagram Rembrandt 37" - 42"


WIRING DIAGRAM 37"- 42" REMBRANDT

Board Level Repair

Component Level Repair


Only For Authorized Workshop

1M95 (B03C) 1M99 (B03C) 1735 (B03A) 1M20 (B09A) 1JA1 (B11C) 1JA2 (B11C)
1. +3V3-STANDBY 1. +12VD 1. LEFT-SPEAKER 1. LIGHT-SENSOR 1. GND 1. GND
2. STANDBY 2. +12VD 2. GND-AUDIO 2. GND | |
3. GND 3. GND 3. GND-AUDIO 3. RC 36. VCC 19. VDD
4. GND 4. GND 4. RIGHT-SPEAKER 4. LED-2 37. VCC 20. VDD
5. GND 5. LAMP-ON 5. +3V3-STANDBY | |
6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 41. VDD 24. VCC
7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 42. VDD 25. VCC
8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V | |
9. +24V-AUDIO-POWER 9. POWER-OK 60. GND 60. GND
10. GND-AUDIO
11. MAINS-OK
1316
1P3

1M99
9P
8M20
1M20 1JA2 1JA1

1M95
11P
8P

8JA1
60P 60P

8JA2
HIGH VOLTAGE

MAIN POWER SUPPLY SSB


1319
1P3

IPB 37 PLHD-P982A B B

CONDITIONAL ACCESS
(1150)

IPB 42 PLHF-P983A B

1M99
8M99

9P
(1005)

1M95
KEYBOARD CONTROL

11P
8M95

1735
4P
2P3 2P3
1311 1308
N L

USB
TUNER
TO BACKLIGHT

TO BACKLIGHT

MAINS CORD
(1114)

8191

HDMI
HDMI

PHONE
HDMI HDMI VGA
3P
J1

SCART

8311

CN2 LCD DISPLAY CN1


TWEETER (1004) TWEETER
(5215) (5215)
J2 J1 IR / LED BOARD MAINS
3P 8P (1112) SWITCH
LOUDSPEAKER
(5213)

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Block Diagrams Q552.1E LA 9. EN 79

9-3 Wiring diagram Van Gogh 32" - 40"


WIRING DIAGRAM 32"- 40" VAN GOGH

TO DISPLAY LCD DISPLAY TO DISPLAY


(1004)
Board Level Repair

Component Level Repair


Only For Authorized Workshop
8KA1

8KA2

1M95 (B03C) 1M99 (B03C) 1M20 (B09A) 1KA1 (B14E) 1KA2 (B14E)
1. +3V3-STANDBY 1. +12VD 1. LIGHT-SENSOR 1. GND 1. GND
2. STANDBY 2. +12VD 2. GND | |
3. GND 3. GND 3. RC 11. VLS_15V6 11. VLS_15V6
4. GND 4. GND 4. LED-2 12. VLS_15V6 12. VLS_15V6
5. GND 5. LAMP-ON LOUDSPEAKER 5. +3V3-STANDBY | |
6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 33. VCC_3V3 33. VCC_3V3
(5213)
7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 34. VCC_3V3 34. VCC_3V3
8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V | |
9. +24V-AUDIO-POWER 9. POWER-OK 78. VGH_25V 78. VGH_25V
10. GND-AUDIO 79. VGL_6V 79. VGL_6V
11. MAINS-OK 1735 (B03A) 80. GND 80. GND
1. LEFT-SPEAKER
KEYBOARD CONTROL

2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER

8M20

1M20 1KA2 1KA1


40"-10P
(1114)

32"-12P
1319
1316

8P 80P 80P

1M99
9P
SSB
40"-10P
32"-6P

B
1316
1319
3P
J1

CONDITIONAL ACCESS
(1150)

1M99
8M99

9P
1M95
11P

MAIN POWER SUPPLY

1M95
11P
8M95
TO BACKLIGHT

32"- FSP124-3MS01 B
40"- DPS-206CP A B

1735
4P
(1005)

USB
TUNER

HDMI
PHONE
SPDIF
HDMI HDMI VGA
SCART

2P3 2P3
1311 1308
N L

8311
MAINS CORD
8191

TWEETER TWEETER
(5216) (5216)
MAINS
SWITCH J2 J1 IR / LED BOARD
NOT FOR 32" TV-SETS NOT FOR 32" TV-SETS
3P 8P (1112)

18770_402_100217.eps
100219

2010-Feb-19 back to
div. table
Block Diagrams Q552.1E LA 9. EN 80

9-4 Wiring diagram Matisse 32"


WIRING DIAGRAM 32" MATISSE

8M83

8M09

TO BACKLIGHT
8JA1
8JA2
8M20
8M59
8M20
1M83
25P

1M84
25P
1M20 1JA1 1JA1 1M72 1M59
1319 1316 1M09 8P 60P 60P 4P 23P
12P 13P 4P

SSB
B

1M99

CONDITIONAL ACCESS
9P
(1150)

1M99
8M99

9P
1M95
11P

1M95
11P
8M95
AMBILIGHT MODULE 18 LED

AMBILIGHT MODULE 18 LED


MAIN POWER SUPPLY

1735
KEYBOARD CONTROL

SUB-WOOFER

4P

USB
(5214) ETHER
DPS-199DP-1 A B NET

1D38
3P
(1005)

TUNER
SCART

HDMI
(1114)

SPDIF
HDMI HDMI HDMI VGA
SCART
3P
J1
(1174)

(1174)
AL

AL
Board Level Repair

Component Level Repair


Only For Authorized Workshop
2P3 2P3

1M83
25P
1311 1308

MAINS CORD
8191
TO DISPLAY LCD DISPLAY TO DISPLAY
(1004)

8311
SPEAKER R SPEAKER L
MAINS
(5215) (5215)
SWITCH

J2 J1 IR / LED BOARD
3P 8P (1112)

1M38 (AL1A) 1M48 (AL2A) 1M95 (B03C) 1M99 (B03C) 1M20 (B09A) 1735 (B03A) 1KA1 (B14E) 1KA2 (B14E) 1M59 (B13)
1. +24V 14. +3V3 1. SPI-CLOCK-BUF 14. N.C. 1. +3V3-STANDBY 1. +12VD 1. LIGHT-SENSOR 1. LEFT-SPEAKER 1. GND 1. GND 1. AMBI-SPI-CLK-OU 15. AMBI-TEMP
2. +24V 15. BLANK 2. SPI-DATA-OUT 15. TEMP-SENSOR 2. STANDBY 2. +12VD 2. GND 2. GND-AUDIO | | 2. AMBI-SPI-SDO-OUT 16. GND
3. +24V 16. PROG 3. SPI-DATA-RETURN 16. GND 3. GND 3. GND 3. RC 3. GND-AUDIO 11. VLS_15V6 11. VLS_15V6 3. AMBI-SPI-SDI-OUT-GI 17. GND
4. +24V 17. GND 4. GND 17. GND 4. GND 4. GND 4. LED-2 4. RIGHT-SPEAKER 12. VLS_15V6 12. VLS_15V6 4. GND 18. GND
5. +24V 18. LATCH 5. PWM-CLOCK-BUF 18. GND 5. GND 5. LAMP-ON 5. +3V3-STANDBY | | 5. AMBI-PWM-CLK_B2 19. GND
6. GND 19. SPI-CS 6. +3V3 19. GND 6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 33. VCC_3V3 33. VCC_3V3 6. V-AMBI 20. GND
7. GND 20. +3V3 7. SPI-CS 20. GND 7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 1D38 (B03A) 34. VCC_3V3 34. VCC_3V3 7. AMBI-SPI-CS-OUTn_R2 21. +24V
8. GND 21. PWM-CLOCK 8. LATCH 21. +24V 8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V 1. LEFT-SPEAKER | | 8. AMBI-LATCH1_G2 22. +24V
9. GND 22. GND 9. GND 22. +24V 9. +24V-AUDIO-POWER 9. POWER-OK 2. GND-AUDIO 78. VGH_25V 78. VGH_25V 9. GND 23. +24V
10. GND 23. SPI-DATA-RETURN 10. PROG 23. +24V 10. GND-AUDIO 3. RIGHT-SPEAKER 79. VGL_6V 79. VGL_6V 10. AMBI-PROG_B1 24. +24V
11. TEMP-SENSOR 24. SPI-DATA-IN 11. BLANK 24. +24V 11. MAINS-OK 1M72 (B13) 80. GND 80. GND 11. AMBI-BLANK_R1 25. +24V
12. N.C. 25. SPI-CLOCK 12. +3V3 25. +24V 1. +24V 12. V-AMBI
13. N.C. 13. N.C. 2. +24V 13. AMBI-LATCH2_DIS
3. GND 14. AMBI-SPI-CS-EXTLAMPSn
4. GND
18770_403_100217.eps
100219

2010-Feb-19 back to
div. table
Block Diagrams Q552.1E LA 9. EN 81

9-5 Wiring Matisse 40"


WIRING DIAGRAM 40" MATISSE

8M83

Board Level Repair


8M09
Component Level Repair
TO BACKLIGHT
Only For Authorized Workshop 8K51
8G50

8M59
8M20
1M83
25P

1M84
25P
1M20 1M59 1G51 1G50
1319 1316 1M09 8P 1M09 23P 51P 41P
11P 12P 4P 4P

SSB
B

1M99

CONDITIONAL ACCESS
9P
(1150)

1M99
8M99

9P
1M95
11P

1M95
11P
8M95
AMBILIGHT MODULE 24 LED

AMBILIGHT MODULE 24 LED


MAIN POWER SUPPLY

1735
KEYBOARD CONTROL

4P

USB
ETHER
DPS-199DP A B NET
(1005)

TUNER
SCART

HDMI
(1114)

SPDIF
HDMI HDMI HDMI VGA
SCART
3P
J1
(1174)

(1174)
8735
AL

AL
1308
2P3

2P3
1311

TO DISPLAY TO DISPLAY

1M83
+ -

+ -

25P
LOADSPEAKER RIGHT LCD DISPLAY LOADSPEAKER LEFT
(5215) (1004) (5215)
MAINS CORD

TCON
8191

8311

MAINS
SWITCH

J2 J1 IR / LED BOARD
3P 8P (1112)

1M59 (B13) 1M38 (AL1A) 1M48 (AL2A) 1M95 (B03C) 1M99 (B03C) 1M20 (B09A) 1735 (B03A) 1KA1 (B14E) 1KA2 (B14E)
1. AMBI-SPI-CLK-OU 15. AMBI-TEMP 1. +24V 14. +3V3 1. SPI-CLOCK-BUF 14. N.C. 1. +3V3-STANDBY 1. +12VD 1. LIGHT-SENSOR 1. LEFT-SPEAKER 1. GND 1. GND
2. AMBI-SPI-SDO-OUT 16. GND 2. +24V 15. BLANK 2. SPI-DATA-OUT 15. TEMP-SENSOR 2. STANDBY 2. +12VD 2. GND 2. GND-AUDIO | |
3. AMBI-SPI-SDI-OUT-GI 17. GND 3. +24V 16. PROG 3. SPI-DATA-RETURN 16. GND 3. GND 3. GND 3. RC 3. GND-AUDIO 11. VLS_15V6 11. VLS_15V6
4. GND 18. GND 4. +24V 17. GND 4. GND 17. GND 4. GND 4. GND 4. LED-2 4. RIGHT-SPEAKER 12. VLS_15V6 12. VLS_15V6
5. AMBI-PWM-CLK_B2 19. GND 5. +24V 18. LATCH 5. PWM-CLOCK-BUF 18. GND 5. GND 5. LAMP-ON 5. +3V3-STANDBY | |
6. V-AMBI 20. GND 6. GND 19. SPI-CS 6. +3V3 19. GND 6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 33. VCC_3V3 33. VCC_3V3
7. AMBI-SPI-CS-OUTn_R2 21. +24V 7. GND 20. +3V3 7. SPI-CS 20. GND 7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 1M09 (B09) 34. VCC_3V3 34. VCC_3V3
8. AMBI-LATCH1_G2 22. +24V 8. GND 21. PWM-CLOCK 8. LATCH 21. +24V 8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V 1. +24V | |
9. GND 23. +24V 9. GND 22. GND 9. GND 22. +24V 9. +24V-AUDIO-POWER 9. POWER-OK 2. +24V 78. VGH_25V 78. VGH_25V
10. AMBI-PROG_B1 24. +24V 10. GND 23. SPI-DATA-RETURN 10. PROG 23. +24V 10. GND-AUDIO 3. GND 79. VGL_6V 79. VGL_6V
11. AMBI-BLANK_R1 25. +24V 11. TEMP-SENSOR 24. SPI-DATA-IN 11. BLANK 24. +24V 11. MAINS-OK 4. GND 80. GND 80. GND
12. V-AMBI 12. N.C. 25. SPI-CLOCK 12. +3V3 25. +24V
13. AMBI-LATCH2_DIS 13. N.C. 13. N.C. 18770_404_100217.eps
14. AMBI-SPI-CS-EXTLAMPSn 100219

2010-Feb-19 back to
div. table
Block Diagrams Q552.1E LA 9. EN 82

9-6 Block Diagram Video


VIDEO
B01A COMMON INTERFACE B02 PNX85500 B06B VIDEO OUT - LVDS B11A TCON CONTROLLER (LGD) B11C MINI LVDS
1JA1
1P00
60
17
+5VCA 1G50 7J01 7J02 58
18
1 TL2429MC M24C32
51 53
7F01 2
7600
52 74LVC245APW SDA-TCON 42
PNX85433EH/M2A
20
+3V3 3 SCL-TCON EEPROM 41
PCMCIA B02A VIDEO STREAM B02F LVDS +VDD

68P
PX1 PX1 37
36
+VCC
CONDITIONAL MDO(0-7) BUFFER CA-MDO(0-7) MD0 TO DISPLAY TO TCON SSB 34 TO DISPLAY
ACCESS (TCON ON DISPLAY) (TCON ON SSB)
LML
21
CA-MDI(0-7) MDI
PX2 3 PX2
13
B07A DVBS-FE 7R02 7R01 7JC1
GMA
2
STV6110AT STV0903BAC 41 MAX9668ETP
N.C. 1
4 DVB-S 21 IP 7 DVB-S 78 TS-DVBS-VALID TIMING
TNR_SER1_MIVAL
TUNER IM CHANNEL TS-DVBS-SOP CONTROL GAMMA
SAT IN 20 8
DECODER
75 TNR_SER1_SOP QUAD LVDS 1JA2
32 XTAL 122 74 TS-DVBS-CLOCK 1G51 1920x1080 REF 60
TNR_SER1_MICLK
30 18 QP 12 73 TS-DVBS-DATA SYST 59
TNR_SER1_DATA 51 100/120HZ
19 QM 11 50 GMA

1R10

16M
48
I2C 49
31 40
Only For DVBS RML
40 27
B01F HDMI & CI
7F75 PX3 PX3
25
UPC3221GV TO DISPLAY
1T01 1 B02I ANALOG VIDEO TO DISPLAY
B11B TCON DC/DC +VDD
24 (TCON ON SSB)
TH2603 VCC TO TCON SSB 20
(TCON ON DISPLAY) 7JD1
5F73 2F90 1F75 2F74 2 AGC AMPLIFIER 7 3F79-1 PNX-IF-P AE12
10 TUN-IF-P 1 4 TUNER_P MAX17119ET 19
IF-OUT1 +VCC
BANDPASS
5F70 PX4 PX4 13
2F78 40
11 TUN-IF-N 2 5 3 6 3F79-4 FILTER PNX-IF-N AF12 GCLK CLK
RF IN IF-OUT2 TUNER_N LEVEL 2
SAW 36MHZ17 4 IN OUT 4 SHIFTER
1
7F70 AGC CONTROL
3
MAIN HYBRID SELECT-SAW
B02E 2 SSB 3104 313 6402*
TUNER SSB 3104 313 6406*
CONTROL 1
PNX-IF-AGC AD12 +VDISP
IF_AGC
B14A TCON CONTROL (SHARP) B14E MINI LVDS (

OR
1KA1
81
7KAA B14C P GAMMA & 58
UPD809900F VOM & FLASH
B01H HDMI B04D HDMI B04A ANALOGUE EXTERNALS A 7KQB
53
M25P32 42
SPI

1E01
15 AV1-R AC13
PNX85500 PX1
SDO
SCS
SCK
FLASH
+VDD
41
37
36
AV1_R +VCC
1 11 AV1-G AE13 50 TO DISPLAY
AV1_G TO TCON SSB
AVI-B (TCON ON SSB)
7 AD13 L_LV
AV1_B 13
7 20 AV1-CVBS AB15
CVBS_Y1 PX2
EXT 1 7E05 13
7EC1 11

SII9187ACNU 19 GMA
15 7E09-1 7KQA 2
SII9287BCNU 16
16 AV1-BLK ISL24837IRZ 1
20
B02G
1P05 21
CONTROL TIMING
8 AV1-STATUS
1 90
SCART1 B02G 7E06 CONTROL REF 1KA2
DRX2+
CONTROL CVBS-MON-OUT1 AF11 VOLTAGE 81
3 DRX2- 89 CVBS1_OUT
1E02 GEN 59
1

4
2

DRX1+ 87
6 15 AV4-PR AC14 GMA
DRX1- 86 AI33 48
RXD 1 11 AV4-Y AE14
7 DRX0+ 84 AI13
7 AV4-PB AD14 AI23 50
9 DRX0- 83
18

7
19

10 20 AV2-CVBS AB14 R_LV


DRXC+ 81 AI42 13
12 DRXC- 80 EXT 2 11 7E04 PX3
HDMI SIDE 25
CONNECTOR 19 TO DISPLAY
16
15
7E09-2 B14D MPD +VDD
24 (TCON ON SSB)
16 AV2-BLK TO TCON SSB 20
HDMI 20
21
B02G
CONTROL
7KUE
MAX17079GTL 19
1P04 SCART2 8 AV2-STATUS +VCC
1 ARX2+ 23
SWITCH Only 7000 Serie
B02G
PX4 13
CONTROL CS(1-12) LEVEL CS(1U-12U)
3 ARX2- 22 2
1

SHIFTER
2

4 ARX1+ 20 B01I VGA 1


6 ARX1- 19 1E05
RXA
7 ARX0+ 17 1 R-VGA AF16 VGA_R SSB 3104 313 6364* SSB 3104 313 6400*
9 16 2 G-VGA
18

ARX0- AD16 B02E CONROL


B01C
10
19

USB HUB
15

VGA_G
5

10 ARXC+ 14 3 B-VGA AE16


VGA_B +5V-USB2
HDMI 3 12 ARXC- 13 13 H-SYNC-VGA AB18
HSYNC_IN 1P08
1

CONNECTOR
11

14 V-SYNC-VGA AC18 1
VSYNC_IN
Only 7000 Serie

1
R26 USB-DM 9F26 USB-DM2 2
SIDE USB

3 2
VGA USB_DN
R25 USB-DP 9F25 USB-DP2 3
CONNECTOR USB_DP CONNECTOR
9,27,64 4

4
+3V3-HDMI VCC33
B04B ANALOGUE EXTERNALS B B02A FLASH B01B FLASH
7F20 7000 Serie
1E04 NAND02GW3B2DN6F
AV3-PR AC15 +5V-USB1
2 NAND04GW3B2DN6F
PR PR_R_C1 1P07
1E08 1
AV3-Y NAND

1
1P03 EXT 3 2 AE15 9F21 2
Y Y_G1 USB-DM1
FLASH SIDE USB

3 2
1 BRX2+ 42 1E03 XIO_D XIO-D(00-07) 9F20 USB-DP1 3
AV3-PB CONNECTOR
3 BRX2- 41 2 AD15 4

4
PB PB_B1
256MB
1
2

4 BRX1+ 39
6 BRX1- 39 1ECB Y-SVHS AC12
ATV_CVBS_Y3
512MB
RXB 1 5000 Serie
7 BRX0+ 36 3
SVHS IN 5 C-SVHS AF13 12,37
9 BRX0- 35 CR VCC +3V3
18
19

4
10 BRXC+ 33 2
HDMI 2 12 BRXC- 32 5000 Serie 256MB
CONNECTOR 7000 Serie 512MB
B02C HDMI_DV B02B MEMORY
B05A DDR
1P02 62 HDMIA-RXC+ W25
TXC_P RXC_B_N
1 CRX2+ 72 63 HDMIA-RXC- W26 DQ DDR2-D(0-31)
TXC_N RXC_B_P
3 CRX2- 71 60 HDMIA-RX0+ V25 7B00 7B02
TX0_P RX0_B_N
EDE1116AGBG EDE1116AEBG 7B03 7B01

D(16-23)

D(24-31)
1

D(8-15)
4 CRX1+ 69 61 HDMIA-RX0- V26
2

D(0-7)
TX0_N RX0_B_P EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
6 CRX1- 68 58 HDMIA-RX1+ U25
RXC TX1_P RX1_B_N
7 CRX0+ 66 59 HDMIA-RX1- U26
TXA_N RX1_B_P SDRAM SDRAM SDRAM SDRAM
9 CRX0- 65 56 HDMIA-RX2+ T25
RX2_B_N 128MB 128MB 128MB 128MB
18

TX2_P
19

10 CRXC+ 63 57 HDMIA-RX2- T26


TX2_N RX2_B_P
12 CRXC- 62 3S0W W24
HDMI 1

VDDL
VREF

VDDL
VREF

VDDL
VREF

VDDL
VREF
+3V3 RREF
CONNECTOR

A1 E2 A1 E2 A1 E2 A1 E2

A DDR2-A(0-13)
+1V8
DDR2-VREF-DDR
5000 Serie 256MB 7000 Serie 512MB
A2
VREF_1 DDR2-VREF-CTRL2
V1
VREF_2 DDR2-VREF-CTRL3
18770_405_100217.eps
100219

2010-Feb-19 back to
div. table
Block Diagrams Q552.1E LA 9. EN 83

9-7 Block Diagram Audio


AUDIO
B01A COMMON INTERFACE B02 PNX85500 B02D CLASS-D B03A AUDIO
1P00
7H00
17
+5VCA PNX85439EH/M2
18
B02A VIDEO STREAM B02D AUDIO
51 7F01 7D10
52 74LVC245APW TPA3123D2PWP
20 1,3 5D07
PCMCIA +3V3 PVCC_L +24V-AUDIO-POWER
10,12 5D08

68P
7S05 PVCC_R
LM324P 1735
ADAC(1) 12 14 +AUDIO-L 5 22 LEFT-SPEAKER 1
CONDITIONAL MDO(0-7) BUFFER CA-MDO(0-7) MD0 AD7 OUT-L
ADAC_1 IN-L
ACCESS
CLASS D 2
CA-MDI(0-7) MDI POWER
SPEAKER L
AMPLIFIER
3
B07A DVBS-FE ADAC_2
AE7 ADAC(2) 10 8 -AUDIO-R 6
IN-R
7R02 7R01
STV6110AT STV0903BAC 7D15 15 RIGHT-SPEAKER 4
OUT-R
A-PLOP A-STBY 2
4 DVB-S 21 IP 7 DVB-S 78 TS-DVBS-VALID B03H STANDBY A-PLOP SD SPEAKER R
TNR_SER1_MIVAL B04E
TUNER IM CHANNEL TS-DVBS-SOP 1D38
SAT IN 20 8 75 TNR_SER1_SOP
30 XTAL
DECODER TS-DVBS-CLOCK AC19 AUDIO-MUTE-UP 4 1
32 122 74 TNR_SER1_MICLK PO_7 MUTE
18 QP 12 73 TS-DVBS-DATA 5D03

1R10
2

16M
TNR_SER1_DATA
19 QM 11 7D03 7D03
DETECT2 3
31 B02G MAIN SWITCH A-STBY STANDBY &
Only For DVBS MAINS-OK PROTECTION
B03C DETECT SUBWOOFER
(OPTIONAL)
B01F HDMI & CI
7F75
+5V-TUN-PIN
1T01
UPC3221GV
B02I ANALOG VIDEO
B04E HEADPHONE B01J TEMP SENSOR + HEADPHONE
1
TH2603 VCC
2F90 1F75 2F74 AGC AMPLIFIER 7 3F79-1 7EE0-1 7EE0-2
10 TUN-IF-P 5F73 1 4 2 PNX-IF-P AE12
IF-OUT1 TUNER_P AD1 RESET-AUDIO A-PLOP B03A
BANDPASS PO_6
5F70

B04A
11 TUN-IF-N 2 5 2F78 3 6 3F79-4 FILTER PNX-IF-N AF12
RF IN IF-OUT2 TUNER_N
SAW 36MHZ17 4 IN OUT
7F70 AGC CONTROL
MAIN HYBRID SELECT-SAW
7EE1
B02E TPA6111A2DGN
TUNER
CONTROL PNX-IF-AGC AD12
IF_AGC
HEADPHONE
AMPLIFIER
5
SHUTDOWN 1328
1 AMP1 2
VO_1
B01H HDMI B04D HDMI B04A ANALOGUE EXTERNALS A B02D PNX85500: AUDIO
ADAC3
AF7 ADAC(3) 2
IN-1 7 AMP2 3
1E01-1 VO_2
7EC1
3 AP-SCART-OUT-L 3EA7-1 7S05 1 HEADPHONE
SII9187ACNU AUDIO-OUT-L 1 3 ADAC(5) AE6
1 ADAC_5 AD6 ADAC(4) 6 8 OUT 3.5mm
SII9287BCNU ADAC4 IN-2 VDD +3V3
1 AP-SCART-OUT-R 3EA7-4 AUDIO-OUT-R ADAC(6)
7 5 AF6 ADAC_6
7
1P05
1
3
DRX2+
DRX2-
90
89
16
11

15
6 AUDIO-IN1-L AE10 AIN1_L
PNX85500 B01C USB HUB
1

4
2

DRX1+ 87 2 AUDIO-IN1-R AF10


6 AIN1_R B02E CONROL
DRX1- 86 20
21
RXD
7 DRX0+ 84 SCART1
9 DRX0- 83 1E02 +5V-USB2
18
19

10 81 1P08
DRXC+ 1 3 AP-SCART-OUT-L 7E01
A-PLOP 1
HDMI SIDE 12 DRXC- 80 A-PLOP B03C

1
R26 USB-DM 9F26 USB-DM2 2
CONNECTOR 1 SIDE USB

3 2
7 AP-SCART-OUT-R USB_DN
R25 USB-DP 9F25 USB-DP2 3
USB_DP CONNECTOR
4
HDMI 11

4
6 AUDIO-IN2-L AD10
1P04 15 AIN2_L
1 23
SWITCH 16
7000 Serie
ARX2+
20
2 AUDIO-IN2-R AC10
AIN2_R B02A FLASH B01B FLASH
3 ARX2- 22 21 +5V-USB1
1

SCART2 1P07
2

4 ARX1+ 20 7F20
Only 7000 Serie 1
6 ARX1- 19 NAND02GW3B2DN6F

1
RXA 9F21 USB-DM1 2
7 ARX0+ 17 NAND04GW3B2DN6F SIDE USB

3 2
9 16
B04B ANALOGUE EXTERNALS B 9F20 USB-DP1 3
CONNECTOR
18

ARX0- ADAC_5 NAND


19

4
10 14 1E08
ARXC+ ADAC_6 FLASH
HDMI 3 12 ARXC- 13 6 AUDIO-IN3-L AE9 XIO_D XIO-D(00-07)
AIN3_L
CONNECTOR
Only 7000 Serie
AUDIO IN
4
256MB 5000 Serie
L+R AUDIO-IN3-R AF9
AIN3_R 512MB
9,27,64
+3V3-HDMI VCC33 12,37
1E09 VCC +3V3
2 AUDIO-IN4-L AD9
AIN4_L
VGA (OR DVI)
5000 Serie 256MB
AUDIO 3 AUDIO-IN4-R AC9
AIN4_R 7000 Serie 512MB
1
+3V3
1P03 B02B MEMORY
1 BRX2+ 42
1E07 7S09 B05A DDR
2
DIGITAL 1 SPDIF-OUT 3 &
3 BRX2- 41 1 SPDIF-OUT-PNX AF5
AUDIO SPDIF_OUT
1
2

4 BRX1+ 39 OUT 4
6 BRX1- 39 B02G STANDBY
RXB DQ DDR2-D(0-31)
7 BRX0+ 36 7B00 7B02
8 5 SEL-HDMI-ARC AF18
35 P0_4 EDE1116AGBG EDE1116AEBG 7B03 7B01

D(16-23)

D(24-31)
9 BRX0-

D(8-15)
18

D(0-7)
19

10 33 EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG


BRXC+ B02c HDMI_DV
HDMI 2 12 BRXC- 32
CONNECTOR SDRAM SDRAM SDRAM SDRAM
62 HDMIA-RXC+ W25 128MB 128MB 128MB 128MB
RXC_B_N
1P02 63 HDMIA-RXC- W26
RXC_B_P

VDDL
VREF

VDDL
VREF

VDDL
VREF

VDDL
VREF
1 72 60 HDMIA-RX0+ V25
CRX2+ RX0_B_N
3 CRX2- 71 61 HDMIA-RX0- V26
RX0_B_P
58 HDMIA-RX1+ U25
1

4 CRX1+ 69 A1 E2 A1 E2 A1 E2 A1 E2
2

RX1_B_N
6 68 59 HDMIA-RX1- U26
CRX1- RX1_B_P A DDR2-A(0-13)
RXC 56 HDMIA-RX2+ T25
7 CRX0+ 66 RX2_B_N
HDMIA-RX2- T26 +1V8
9 CRX0- 65 57 RX2_B_P
18

DDR2-VREF-DDR
19

10 CRXC+ 63
12 62 3S0W W24 5000 Serie 256MB
HDMI 1 CRXC- 7000 Serie 512MB
+3V3 RREF
CONNECTOR A2
14 5EC2 VREF_1 DDR2-VREF-CTRL2
ARC-eHDMI+ eHDMI+ V1
VREF_2 DDR2-VREF-CTRL3
5000 Serie mux SIL9187 - non Instaport 18770_406_100217.eps
7000 Serie mux SIL9287 - Instaport 100219

2010-Feb-19 back to
div. table
Block Diagrams Q552.1E LA 9. EN 84

9-8 Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS
B01D SD-CARD B02A PNX85500 B06C AMBILIGHT
7GA0
XC9572XL
7S00
PNX85507EB PXCLK54 43 1M59
B02E
22 AMBI-SPI-CLK-OUT 1
1P09 PNX-SPI-CLK 41 27 AMBI-SPI-SDO-OUT 2
B02E ETHERNET
1 SDIO-DAT3 W2 PNX-SPI-SDI 40 CPLD 23 AMBI-SPI-SDI-OUT_G1 3
CC_DAT3
2 SDIO-CMD W6 PNX-SPI-SDO 39 29 AMBI-PWM-CLK_B2 5

Pin9
CMD

Pin1
5 SDIO-CLK W1 30 AMBI-SPI-CS-OUTn_R2 7

Pin2
CLK

Pin3
Pin4
7 SDIO-DAT0 W5 31 AMBI-LATCH1_G2 8 TO AMBILIGHT

Pin6 Pin5
DAT_0

Pin8 Pin7
8 SDIO-DAT1 W4 AMBI-PROG_B1 10 MODULE
9 SDIO-DAT2 W3
DAT_1
DAT_2
PNX85500 B02G
19
20 AMBI-BLANK_R1 11
SD-CARD 10 SDIO-CDn U6 13
B02E CONTROL V22 PNX-SPI-CS-BLn 3 28 AMBI-LATCH2_DIS
CONNECTOR SDCD
12 SDIO-WP V6 W23 PNX-SPI-CS-AMBIn 2 21 AMBI-SPI-CS-EXTLAMPSn 14
SDWP
32 AMBI-TEMP 15

VCCIO
B04C ETHERNET + SERVICE B02A
B02H POWER AF1 SENSE+1V1
26
7E10 VDD_1V1 B03B VIO
AA15 SENSE+1V2
LAN8710A-EZK VDDA_1V2 B03D
ETH-RXD SDCD
ETHERNET ETH-TXD SDWP
B02B MEMORY B05A DDR
7 ETH-RXCLK AA3
TXCLK DQ DDR2-D(0-31)
20 ETH-TXCLK AA2 7B00 7B02
RXCLK
7B03 7B01

D(16-23)

D(24-31)
EDE1116AGBG EDE1116AEBG

D(8-15)
ETHERNET

D(0-7)
CONNECTOR EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
RJ45
SDRAM SDRAM SDRAM SDRAM
B07A DVBS-FE B01K TUNER BRAZIL
128MB 128MB 128MB 128MB
B02A VIDEO STREAM
7R02 7R01
STV6110AT STV0903BAC
32 XTAL 122 73 TS-DVBS-DATA 9F27-1 TS-FE-DATA T21
QP 12 9F28 F8 E8 F8 E8 F8 E8 F8 E8
SATELLITE 18 MULTI STAND 74 TS-DVBS-CLOCK TS-FE-CLOCK T22
19 QM 11 DEMODULATOR 75 TS-DVBS-SOP 9F27-2 TS-FE-SOP R22 DDR2-A(0-13)
TUNER A
21 IP 7 FOR SAT DIG TV 78 TS-DVBS-VALID 9F27-4 TS-TS-VALID R23 DDR-CLK_N
CLK_N
20 IM 8 62 RESET-DVBS DDR-CLK_P
CLK_P
B02G
SENSE+1V0-DVBS 52 5000 Serie 7000 Serie
A80B

B01B FLASH B01A COMMON INTERFACE B02E CONTROL B02E PNX85500: MIPS B01C USB HUB

U23 SELECT-SAW
1P00 GPI0_11 B01F
MDO U23 BACKLIGHT-PWM
1 CA-MDI(0-7) GPI0_11 B13
AC5 PXCLK54
7F01 CLK_54_OUT B06C B13
AE4 RESET-SYSTEMn +5V-USB2
RESET_SYS B01K B02G
W23 PNX-SPI-CS-AMBIn 1P08
GPI0_6 B06E B06D B13
V22 PNX-SPI-CS-BLn 1
GPI0_7 B01K B02G B02G

1
MDO(0-7) CA-MDO(0-7) MDI R26 USB-DM 9F26 USB-DM2 2
COMMON INTERFACE

USB_DN SIDE USB

3 2
7F02 R25 USB-DP 9F25 USB-DP2 3
USB_DP CONNECTOR
7F03 B02A FLASH 4

4
PCMCIA
7F20
NAND02GW3B2DN6F
B04V ETHERNET + SERVICE
CA-A(00-14) XIO-A(0-14) XIO_A
NAND04GW3B2DN6F +5V-USB1
CONDITIONAL 1E06
7F04 Y23 RXD1-MIPS 1P07
NAND ACCESS GPI0_2 2
1
7F05 UART
FLASH

1
12,37 Y24 TXD1-MIPS 3 SERVICE 9F21 USB-DM1 2
GPI0_3 SIDE USB

3 2
VCC +3V3 CONNECTOR 9F20 3
1 USB-DP1 CONNECTOR
256MB CA-D(0-7) XIO-D(00-15) XIO_D 4

4
68
512MB

XIO-D(00-07) B02G PNX85500: STANDBY CONTROLLER B01E PNX85500-CONTROL

5000 Serie 256MB V23 BOOST-PWM 9CH0 BACKLIGHT-BOOST


7000 Serie 512MB V23 B01E
B06C
7F52
B09A DVBS CONNECTOR BOARD B03C DC / DC M25P05-AVMN6P
1M20 B02G STANDBY
B11D CONNECTORS
1 LIGHT-SENSOR AE26 AF24 PNX-SPI-CLK 6
P5_1
B14F CONNECTORS 2
SPI_CLK
AE22 PNX-SPI-WPn 3 FLASH
P6_5 8
3 RC AD19 AF23 PNX-SPI-CSBn 1 VCC +3V3-STANDBY
P1_0 SPI_CSB
4 LED-2 9U41 LED2 AC25 AE23 PNX-SPI-SDO 5 512K
PWM_1 SPI_SDO
TO IR / LED BOARD AND 5 7U43 AF25 PNX-SPI-SDI 2
+3V3-STANDBY SPI_SDI
KEYBOARD CONTROL 6 LED-1 LED1 AD26 1F51
PWM_0
AG1 RXD-UP 3
UA_RX_0
7 KEYBOARD AD23 P5_O AH5 TXD-UP 1 LEVEL SHIFTED
UA_TX_1
8 AB20 SDM FF04 2 FOR
+5V P1_7
AA26 RESET-STBYn 4 DEBUG USE
RESET_IN ONLY
AF22 SPI-PROG FF29 5
P6_4
B02G PNX85500: STANDBY CONTROLLER
+3V3-STANDBY
DETECT2 AA22 7S20
B03C P3_2
B02E
RESET-SYSTEM AB22 P3_3
NCP303LSN28G B03C DC / DC
AV1-BLK AD22 1 RESET-STBYn
B04A P3_5 OUTP
AV2-BLK AC22 2
B04A P3_4 INP
AV1-STATUS AE25 3
B04A CADC_2 GND

CONTROL
AV2-STATUS AE24 AE17
B04A CADC_3 XTAL_I
LCD-PWR-ONn AC20
B03H P2_0
1S02

54M

ENABLE -3V3-5V
+12V B03E
B04D HDMI AF17 +3V3-STANDBY ENABLE -1V8
XTAL_O B03B B03D
TO PIN: AD21 ENABLE-3V3n DETECT2
7EC0 P2_7 B02G B03A
1P02-13
EF
1P03-13 PCEC-HDMI CEC-HDMI AF19
P1_2
1P04-13 AF18 SEL-HDMI-ARC 1M99
P0_4 B02D
1
2

1P05-13 7EC1 AE20 LAMP-ON 5


SII9187ACNU P2_2
B02C HDMI_DV AA18 RESET-DVBS BACKLIGHT-OUT 6 TO
P0_1 B07A B07A POWER
ARX-HOTPLUG 31 AE18 RESET-ETHERNETn BACKLIGHT-BOOST 7
1P04-19 HDMI HDMIB-RC HDMI_RX P0_3 B04C B01E SUPPLY
18
19

BRX-HOTPLUG 35 AC21 POWER-OK 9


1P03-19 P2_6
CRX-HOTPLUG 41 SWITCH AB19 RESET-AUDIO
4x HDMI 1P02-19 3S0W P0_6 B04E
CONNECTOR DRX-HOTPLUG 45 W24 AE19 TACH0 1M95
1P05-19 +3V3 RREF P1_1 B03G TO
AF20 STANDBY 2 POWER
P2_3
SUPPLY
18770_407_100217.eps
100217

2010-Feb-19 back to
div. table
Block Diagrams Q552.1E LA 9. EN 85

9-9 Block Diagram I2C


I²C
B01E PNX85500: CONTROL B02E PNX85500: MIPS B01E PNX85500-CONTROL B04D HDMI B01K TUNER BRAZIL B01J TEMP SENSOR + B07A DVBS-FE B08B DVBS-SUPPLY
HEADPHONE
7S00 +3V3
PNX85500

3S6D

3S6E
B02E
B25 3S5Y SDA-SSB
3_SDA
A24 3S5Z SCL-SSB
3_SCL

3EC5

3EC3

3FD3

3FD4
3FE9

3FE8

3R00

3R01
+3V3 +3V3RF

3T61

3T51
AIN-5V
ERR
PNX85500 13
53 54 46 45 1 2 98 97 6 9

3EC1-1

3EC1-3
3S6A

3R15

3R14
3S69
CONTROL 1P04
C25 3S56 SDA-UP-MIPS 1F52 7EC1 7FE0 7FD1 7R01 W21 SDAT 7T50
29 ARX-DDC-SDA 16

1
2
1_SDA 3F63 3 SII9287B TC90517FG LM75BDP STV903BAC LNBH23QT
C26 3S57 SCL-UP-MIPS SII9187A W22 SCLT
DEBUG 30 ARX-DDC-SCL 15
1_SCL 3F62 1 TUNER TEMP CHANEL DEC LNB
7F52 ONLY

18
19
HDMI BIN-5V BRAZIL SENSOR DVBS CONTROLLER

3F63

3F59
M25P05-AVMN6P B02G B02G PNX85500: STANDBY MUX HDMI
CONTROLER
5 6 CONNECTOR 3 13 12

3ECA-1

3ECA-2
ERR ERR ERR ERR
FLASH 6 PNX-SPI-CLK AF24 +3V3-STANDBY ERR 1P03 ?? 42 28 31
8 SPI_CLK 23
3 PNX-SPI-WPn AE22 STANDBY 7F58 33 BRX-DDC-SDA 16 7R02

1
+3V3-STANDBY VCC

2
P6_5
M24C64 STV6110A

3S6W
512K 1 PNX-SPI-CSBn AF23

3S6V
SPI_CSB 34 BRX-DDC-SCL 15
5 PNX-SPI-SDO AE23 ERR ERR 3S2F

18
SPI_SDO

19
15 53 AC23 EEPROM CIN-5V SATELITE
2 PNX-SPI-SDI AF25 SPI_SDI MC_SDA (NVM) TUNER
3S2G HDMI RES RES
STANDBY AC24 CONNECTOR 2
MC_SCL B01H

3ECA-3

3ECA-4
SW ERR
HDMI ERR
RES 1P02
35 36
39 CRX-DDC-SDA 16

1
2
+3V3-STANDBY
MAIN NVM
40 CRX-DDC-SCL 15
SW
B01B

18
FLASH

19
DIN-5V

3S1G

3S1H
1F51 HDMI
AE21 RXD-UP 3F65 1 uP
7F20 CONNECTOR 1

3FBF-2

3FBF-1
P3_0 LEVEL SHIFTED +3V3 1P05
NAND02GW3B2DN6F 3F64
NAND04GW3B2DN6F AF21 TXD-UP 2 FOR DEBUG
P3_1 43 DRX-DDC-SDA 16

1
HDMI

2
USE ONLY

3ECU-2

3ECU-4
CONNECTOR
FLASH 44 DRX-DDC-SCL 15
B02A B02I SIDE

18
Y25 DDCA-SDA

19
(4Gx16) DDC_A_SDA
FLASH Only for sets with DVBS
Y26 DDCA-SCL
XIO-D(00-07) XIO_D DDC_A_SCL +3V3 B01I VGA
HDMI_DV B04C ETHERNET + SERVICE +5V-EDID +5V-VGA
MAIN

3S83

3S84
1E06

3ECP-3

3ECP-1
SW

3FC1

3FC2
Y23 RXD1-MIPS 3E53-4 3E53-3 1E05
3
5000 Serie 256MB GPIO_2 9FC1 12

10
47 VGA-SDA-EDID-HDMI

15
3E53-2 3E53-1 UART

5
7000 Serie 512MB Y24 TXD1-MIPS 2
GPIO_3 SERVICE EDID
48 VGA-SCL-EDID-HDMI 9FC3 15
1 CONNECTOR SW

1
B02I B02I

6
PNX85500: ANALOG VIDEO

11
AD25 3S5V-1 9FC2
B05A DDR
VGA_EDID_SDA
VGA-SDA-EDID VGA
3S5V-3 CONNECTOR
AD24 VGA-SCL-EDID 9FC4
VGA_EDID_SCL
7B00
EDE1116AEBG 7B01 RES
EDE1108AGBG EDE1108AGBG ANALOGUE
VIDEO B11C MINI LVDS (LGD) B11A TCON CONTROLLER (LGD) B14C P GAMMA & VCOM & FLASH (SHARP) B14A TCON CONTROL
(SHARP)
SDRAM SDRAM
9S15 1KQB
VGA-SDA-EDID-TCON
1
9S14
D(8-15)
D(0-7)

B02B VGA-SCL-EDID-TCON
2
VCC_3V3
MEMORY
RES
2 1

3KTU

3KTV
DDR2-A(0-13) A 7JB1 VCOM_SDA
DDR2-D(0-31) DQ 7 SDA-TCON
7JB3 VCOM_SCL 7KQH
7B02 +3V3
B01F HDMI & CI VCC
PCA9540B
EDE1116AEBG 7B03 8 SCL-TCON

9JB6

9JB7
EDE1108AGBG EDE1108AGBG 2 CHANNEL

3J36

3J35
3S6G
3S6F
D(16-23)

D(24-31)

1 20 MULTIPLEXER
9JBB SDA-TCON
SDRAM SDRAM B24 3S60 SDA-TUNER 3F75 TUN-P7 12 13 E19 E20

9JB6

9JB7
4_SDA VCC 7JC1 9JBA
3S61 3F76 RES SCL-TCON
A23 SCL-TUNER TUN-P6 MAX9668ETP
4_SCL 7KQA 7KAA
RES

3J38

3J37
ISL24837IRZ 7KQB UPD809900F1
10 BIT M25P32
ERR PROG GAMMA
18 175 176 5 6 8-CHANNEL CONTROL
7 6 REF SYST RES PROG I2C
5000 Serie 256MB 7J01 7J02 1J02 REF VOLT GEN FLASH
7000 Serie 512MB 1T01 TL2429MC M24C32-WDW6 +VDISP 2
TH2603 SCD
TCON EEPROM

3J04
1
B04C ETHERNET + SERVICE MAIN (4Kx8) SCL
TUNER 9JBB TCON
4

SDA-DISP

SCL-DISP
SDA-DISP

SCL-DISP
7
WP SW
ERR
7E10 34 TCON
LAN8710A-EZK SW

Only for LGD display with TCON on SSB Only for LGD display with TCON on SSB
11 ETH-RXD(0) Y5
ETH-RXD(1)
RXD_0 B06B VIDEO OUT - LVDS
10 Y6 +3V3
RXD_1
9 ETH-RXD(2) AB4
RXD_2
ETHERNET 8 ETH-RXD(3) AC1
3S6C
3S6B

RXD_3 1G51
7 ETH-RXCLK AA3
RXCLK B26 3S58 SDA-SET 9S12 SDA-DISP 3G2W 50
2_SDA LVDS
22 ETH-TXD(0) AA1 A25 3S5W SCL-SET 9S11 SCL-DISP 3G2Y 49 CONNECTOR
TXD_0 2_SCL
23 ETH-TXD(1) AA4
TXD_1 +3V3
24 ETH-TXD(2) AB1
ETHERNET TXD_2 ERR +3V3 ERR
25 ETH-TXD(3) AB2 14 64
CONNECTOR TXD_3 2 1
3S67

3S65

3S68

3S66

RJ45 20 ETH-TXCLK AA2 B09A DVBS CONNECTOR BOARD B11D CONNECTORS (LGD) B14F CONNECTORS (SHARP)
TXCLK Programmable via USB
3S81

3S80

4 SW
7S01 1F53 1F53 1F53
W21 RXD2-MIPS PCA9540B 3C84 2 3J84 2 3K84 2 SW Programmable via ComPair
GPIO_2 5
2D 2D 2D SW Pre-programmed device
W22 TXD2-MIPS 2 CHAN. 3C85 3 3J85 3 3K85 3
GPIO_3 DIMMING DIMMING DIMMING
MULTIPLEX.
7
ERR 1M71 1M71 1M71
24 8 3C83 3 3J83 3 3K83 1
TO TO TO
3C81 1 TEMPERATURE 3J81 1 TEMPERATURE 3K81 3 TEMPERATURE
RES SENSOR SENSOR SENSOR
RES RES RES
9S13 SDA-BL

9S10 SCL-BL
Only for LGD display with TCON on SSB Only for SHARP display with TCON on SSB
18770_408_100217.eps
100219

2010-Feb-19 back to
div. table
Block Diagrams Q552.1E LA 9. EN 86

9-10 Supply Lines Overview


SUPPLY LINES OVERVIEW
B03C DC / DC B01K TUNER BRAZIL B03D DC / DC B05A DDR B11C MINI LVDS

1M99 1M99 +1V2-BRA-VDDC +1V2-BRA-VDDC +1V8 +1V8 +1V8 +1V8 VCC VCC
+12VD B01g B03b B03b B11b
1 1 B03h, +1V2-BRA-DR1 +1V2 3B20
+1V2-BRA-DR1 7UA3 DDR2-VREF-DDR VDD VDD
B07a B01g B02h
2 2 B01,a,b,c,d,e,g,j,jk, B11b
+3V3 +3V3 3JC0
B03e B02a,c,d,e,h,B03c,f,g,h,
3 3
B04a,c,d,e,B05a, 3JC1
5FE7 +3V3-BRA +12V B06b,c,d,B08a,B09a, B06A DISPLAY INTERFACING-VDISP P_VDD

PSU-2 4 4
5FE4 +3V3-BRA-FLT B03e
+5V +5V B11d,B13,B14f
+VDISP-INT +VDISP-INT
5 5 LAMP-ON 3U16 B03h
B02G +3V3
6 6 BACKLIGHT-PWM_BL-VS +5V 5FE9 +5V 1G03 B11D CONNECTORS
B06C B03e 7UC0 +VDISP
7 7 BACKLIGHT-BOOST 3U15
B01E 7FE3 +2V5
8 8 BACKLIGHT-PWM-ANA-DISP IN OUT T 3.0A +3V3 +3V3

OR
B02G +2V5-BRA COM B02d,h B03e
IN OUT +2V5-LVDS 5G01
9 9 POWER-OK CUA0
B02G COM +3V3-STANDBY +3V3-STANDBY
B02h B03c
5G02 1G00
7 10 BL-SPI-SDO NOT FOR 5000 SERIES +5V +5V
B02h B03e
8 11 BL-SPI-CSn +5V5-TUN +5V5-TUN T 3.0A
B03e +12V +12V
B03c
9 12 BL-SPI-CLK B02A PNX85500: NANDFLASH 7UA6 +5V-TUN
CONDITIONAL ACCESS B01f
+3V3 +3V3
B03e B06B VIDEO OUT - LVDS
+12V ENABLE-1V8 +12V B13 AMBILIGHT CPLD
1M95 1M95 B03c +3V3 +3V3
B01e,B02e, 7UA0 B03e +3V3 +3V3
1 1 +3V3-STANDBY 3UA0
3V3_ST g,h,B03a,b, VOLT. +2V5-REF B03e
+VDISP +VDISP
STANDBY
2 2 STANDBY B04d,e,B09a, B02B PNX85500: SDRAM REG. B03a 5HA0 VINT
3 3 B11d,B14f
GND1
4 4 +1V8 +1V8 5HA1 VIO
B03e
GND1
5 5
GND1
3S20 DDR2-VREF-CTRL3 B06C . 1M72
1HA0 +24V
1
1U40 +12V 3S06 DDR2-VREF-CTRL2
B03E DC / DC
+3V3 +3V3
6 6 B03b,d,e,g, B03e 2 T 1.5A
+12V B08b,B09a, +1V1 +1V1
7 7 T 3.0A B03b
+12V B11d,B14f 5GA0 VINT
8 8 +12V +12V
+12V B03c 5GA1
+24V-AUDIO-POWER VIO
+VSND
9 9
B02d,B03a
7UD1 B14A TCON CONTROL (SHARP)
GND_SND
10 10 B02C PNX85500: DIGITAL VIDEO IN 5UD3
IN OUT
5UD2 +3V3
11 11 MAINS-OK +VDISP +VDISP
N.C. COM
+3V3 +3V3 7UD0 B14b 7KAC
B03e
5UD0 5UD1
B06D SPI-BUFFER
5KAG VCC_1V2
+5V5-TUN VIN SW
IN OUT
COM B03b +3V3 +3V3 GND B14b
B03e
6UD0 +5V B01,a,c,e,k, 5KAA VDD12
+3V3 +3V3 B03d,B04a,d,
B03e
B02D PNX85500: AUDIO
B09a,B11d, 5KAB LVDS_AVDD
+5V +5V B03d
+3V3 +3V3 7UD2 B14f B07A DVBS-FE
5KAC mini_AVDD
B03e +2V5
IN OUT
+3V3 +3V3 SEE B03D +1V-DVBS +1V-DVBS
B03e COM B08a 5KAD SSCG_AGND
3S11 +3V3-ARC
+2V5-DVBS +2V5-DVBS VCC_3V3 VCC_+3V3
B01A COMMON INTERFACE 7S08
7UD3 B08a
B14b
+2V5-AUDIO IN OUT
+3V3 5KAE
IN OUT B02h SEE B03D VDD33
+3V3 +3V3 COM +3V3-DVBS +3V3-DVBS
COM B08a
B03e 5KAF VDDQ
+24V-AUDIO-POWER +24V-AUDIO-POWER 5R00 +3V3-DEMOD
+5V +5V B03c ONLY FOR 5000 SERIES
B03e 3S0Z +24V-AUDIO-VDD 5R01 +3V3RF
3F01 +5VCA
+T B03F TEMPSENSOR + AMBILIGHT B14B TCON DC / DC (SHARP)

+3V3 +3V3 VCC_1V2 VCC_1V2


B02E PNX85500: MIPS
B03e
B08A DVBS-SUPPLY B14a
B01B FLASH
+3V3 +3V3 1UM0
B03e 5UM1 V-AMBI +1V1 +1V1 +VDISP-INT +VDISP-INT
B03b B03h
+3V3 +3V3
B03e +3V3-STANDBY +3V3 T 1.0A
+3V3 +3V3 1KFA +VDISP
B03c B03e
B14a,c,d
T 3.0A
+24V +24V VLS_15V6_B
B01C USB HUB B03G FAN - CONTROL
B09a
7KFE

+3V3 +3V3
B02G PNX85500: STANDBY CONTROLLER 7T03
9KFC
+3V3 +3V3 TPS54283PWP VLS_15V6
B03e +1V1 +1V1 B03e 5T03 +5V-DVBS B14c,d,e
B03b 7KFA
+5V +5V +12V +12V Dual 7T00 ISL97653AIRZ
B03e POL POL B03c
3F25 ? N-Synchr 5T00 5T01 +1V-DVBS VCC_3V3
+5V-USB1 IN OUT B07a IC
+3V3-STANDBY +3V3 Converter COM B14a,c,d
+T B03c LCD 9KFE VGH_35V
3F32 +5V-USB2 SUPPLY
7T02
+T
B03H VDISP - SWITCH
+3V3-DVBS 3KFP VGL_-6V
B14e
IN OUT B07a,B08b
+3V3 +3V3 COM B14e
B03e

5T02
B02H PNX85500: POWER +12VD +12VD
7T00
B03c +2V5-DVBS
B01D SD-CARD
+1V1 +1V1
IN OUT B07a B14C P GAMMA & VCOM & FLASH (SHARP)
B03b 7UU1 +VDISP-INT B06a,B11b, COM
+3V3 +3V3 B14b VCC_3V3 VCC_3V3
B03e +1V2 +1V2
B03d 5T04 +V-LNB B14b
3F40 +3V3-SD B08b
+1V8 +1V8 7UU2 +VDISP +VDISP
+T B03b
LCD-PWR-ONn B14b
+2V5 +2V5
B03d VLS_15V6 VLS_15V6
+2V5-AUDIO +2V5-AUDIO B14b
B02d B04A ANALOGUE EXTERNALS A B08B DVBS-SUPPLY 7KQA
B01E PNX85500: CONTROL
B03d
+2V5-LVDS +2V5-LVDS
+3V3-DVBS +3V3-DVBS
ISL248371RZ
VREF_15V2
+3V3 +3V3 IC
B08a B14d
+3V3 +3V3 +3V3 +3V3 B03e LCD
B03e +12V +12V
B03e +5V +5V SUPPLY
+3V3-STANDBY +3V3-STANDBY +3V3-STANDBY +3V3-STANDBY B03c
B03c B03c B03e +V-LNB +V-LNB
+5V +5V POL POL
? B08a
B03e
B04C ETHERNET + SERVICE B14D MPD

+3V3 +3V3
B09A DVBS CONNECTOR BOARD
VCC_3V3 VCC_3V3
B03e +3V3 +3V3 B14b
B01F HDMI & CI B03A AUDIO 5E08 +3V3-ET-ANA B03e
VREF_15V2 VREF_15V2
+3V3-STANDBY +3V3-STANDBY B14c
+5V-TUN +5V-TUN +3V3-STANDBY +3V3-STANDBY
B03c
B03d B03c +5V +5V
9F71 +5V-TUN-PIN B03e +VDISP +VDISP
+24V-AUDIO-POWER +24V-AUDIO-POWER 1M20
B03c B04D HDMI
5
B14b
VLS_15V6 VLS_15V6
3D09 +AVCC
+3V3 +3V3 B14b
8 TO
B03e
5EC0 +3V3-HDMI IR/LED
1M09
B01G TOSHIBA SUPPLY
1 +24V
PANEL
B14E MINI LVDS
+3V3-STANDBY +3V3-STANDBY B08a
+3V3 +3V3
B03B DC / DC B03c 2 1M59 VGL_-6V VGL_-6V
1C86 21
B03e 7FA3 +3V3-STANDBY +3V3-STANDBY +5V-VGA +5V-VGA B14b
B03c B01I
5FA3 +1V2-BRA-VDDC T 2.0A VGH_35V VGH_35V
IN OUT B01k +12V +12V
COM +12V +12V B14b
5FA4 +1V2-BRA-DR1 B03c +5V-EDID
B03c
5U02

B01k VCC_3V3 VCC_3V3


6EC1

B14b
7U03 +5V +5V
7U02-1 12V/1V8 VLS_15V6 VLS_15V6
TPS53126PW
COVERSION
B03e B11A TCON CONTROLLER (LGD)
B14b
1P04
12 HDMI 3 AIN-5V
Dual 18 VCC VCC
B01H HDMI
Synchronous
5U00 +1V8 B02h,B03d, CONNECTOR B07a
7U02-2 7J03
1P05
18 DIN-5V
Step-Down B05a
1P03 VCORE
B14F CONNECTORS
HDMI SIDE B04d Controller HDMI 2 BIN-5V IN OUT
14 18
CONNECTOR CONNECTOR COM
9J02 ML_VDD +3V3 +3V3
B03e
1P02
7U01 HDMI 1 CIN-5V +VDISP +VDISP +3V3-STANDBY +3V3-STANDBY
18 B07a B03c
CONNECTOR
B01I HDMI 1 +5V +5V
1E05 12V/1V1 DIN-5V DIN-5V B03e
B01h 1M20
18 +5V-VGA 7U04 COVERSION
VGA
CONNECTOR
B04d B11B TCON DC / DC (LGD) 5
23 TO
+VDISP-INT +VDISP-INT 8 IR/LED
24 5U01 +1V1 B02b,g,h, B04E HEADPHONE B03h PANEL
B03e,B08a 1JG1 +12V +12V
+VDISP
B01J TEMP SENSOR + HEADPHONE +3V3 +3V3 B03c
B03e T 3.0A 7JF1
+3V3 +3V3 +3V3-STANDBY +3V3-STANDBY MAX17113ETL
B03e B03c Multiple VDD
B11c
Output
Power VCC
B11c
Supply
18770_409_100217.eps
100218

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 87

10. Circuit Diagrams and PWB Layouts


10-1 AL1 820400089786 AmbiLight Common
LiteOn LED Common 1

LiteOn 15 LED Common


AL1A AL1A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
+3V3
1M83 C1
2B00 E8
2B11
2B01 F8
100n 2B02 E9
2B03 I14
A FH12-25S-0.5SH(55)
FB01 7B26-1 A 2B04-1 B7

27
+24V TLC5946RHB
1
2 3B00-1 VCC 2B04-2 B6
BLANK 1 8 31 4 PWM-R1
3
PWM-CLOCK-BUF 150R 24
BLANK 0
5 PWM-G1
2B04-3 B8
4 GSCLK 1
5
3B18 26
IREF 2
6 PWM-B1 2B04-4 B7
FB35 3 7 PWM-G3
6
FB03 PROG 4 3B00-4 5
1K8
1
MODE 3
8 PWM-R3
2B08 E12
7 SCLK 4
8 SPI-CLOCK-BUF 150R 2
SIN 5
9 PWM-R2 2B09 E12
SPI-DATA-IN-BUF 23 10 PWM-G2
9
SPI-DATA-IN 3 6
SOUT 6
11 PWM-B2 2B10 F9
10 FB04 7
11 TEMP-SENSOR SPI-DATA-OUT 3B00-3 150R 3B21 22
XERR
OUT
8
14 PWM-B3 2B11 A9
FB20 +3V3 150R 3B22 25 15 PWM-G4
12 XHALF 9 2B17 D8
LATCH 2 3B00-2 7 10K 32 16 PWM-R4
B 13
14
FB05
+3V3 FB06 150R
12
XLAT 10
11
17
18
PWM-B4 B 2B20 D4
15 BLANK 12 PWM-B5
16
FB07 PROG 13
13
19 PWM-G5 3004 E12

6
FB08 28 NC 20
FB10 PWM-R5 3B00-1 A6

2B04-2

2B04-1

2B04-4

2B04-3
17 14

100p

100p

100p

100p
LATCH 29 21 DATA-SWITCH
18 15
19
FB11 SPI-CS
3B31
3B00-2 B6
GND GND_HS
+3V3 FB12 +3V3 3B00-3 B6

3
20

30

33
21 PWM-CLOCK 2K0
22 7B26-2 3B00-4 B6
FB13 SPI-DATA-RETURN TLC5946RHB
23
FB15 SPI-DATA-IN 34 VIA 42 3B01-1 E7
24
25
FB16 SPI-CLOCK 35
VIA VIA
41 3B01-2 D7
27 26 36 40
VIA 3B02-1 E3
C 1M83 C 3B02-2 E5

37
38
39
3B03-1 H14
3B03-2 H14
3B03-3 H14
+3V3
3B03-4 H14
3B07-1 F3
+3V3 3B07-2 G3
3B34 3B07-3 H3
2B20

100n

SPI-DATA-IN-BUF +3V3 +3V3 3B07-4 G3


D 100K RES
D 3B11 E12

2B17

100n
SPI-CLOCK-BUF +3V3
3B13-3 H3

6
1K5 1%

1K5 1%
7B07

3B39-2

3B39-3
7B20-1
3B13-4 I3
8

M95010-WDW6 74LVC2G17
+3V3 VCC

5
7B30
3B18 A8
5
Φ 2

3
D Q FB40
2 3B01-2 7 1 3B30-1 8

5
7B06 (64K) PWM-CLOCK 1 6 PWM-CLOCK-BUF 1
4 TEMP-SENSOR
3B21 B7
74LVC1G32GW 6
5

C 100R 220R 3B22 B8


SPI-CS 1 3
LMV331IDCK

RES
2B00

2
4 1 3B30-1 D9

33p
3B02-2

2
S

2B02

2B08
100p

3004
10K
2 7

10n
DATA-SWITCH

3B11
HOLD +3V3
+3V3 1 3B02-1 8 3 7 10K 2 3B30-4 E9
W

10K
3

3B31 B10

-T
10K
GND
E FB41
E 3B34 D13
4

7B20-2
74LVC2G17 3B35 G14

1
1K5 1%
3B39-1
+3V3 3B36 G14

2B09

10n
5
3B37 G14

8
3B01-1 3B30-4
SPI-DATA-RETURN SPI-CLOCK 1 8 3 4 4 5 SPI-CLOCK-BUF 3B39-1 E13
100R 220R 3B39-2 D12
3B39-3 D13

2B01

2
33p

2B10

100p
+24V 7000 G5
7001 G7
F F 7002 G8
8 3B07-1 1

7B23-1
7003 G10
10K

BC847BS(COL)
6
7004 G11
2 7005 G13
7B06 D3
2 3B07-2 7

1
10K

7B07 D4
7B20-1 D8
PWM-B1
FB30 7B20-2 E8
3B35
+24V 7B23-1 F4
+24V 7000
G LTW-008RGB 7001
LTW-008RGB
7002
LTW-008RGB
7003
LTW-008RGB
7004
LTW-008RGB
7005
LTW-008RGB
270R
3B36
G 7B23-2 G4
7B25 H3
5 3B07-4 4

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6


7B23-2 270R 7B26-1 A8
10K

BC847BS(COL) 3B37
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 7B26-2 C9
68R 7B30 D13
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
FB01 A1
3 3B07-3 6

4
FB03 B1
10K

1 3B03-1 8
FB04 B1
FB31 1K5
FB05 B1
H PWM-R1
2
3B03-2
7 H FB06 B2
+24V
1K5
FB07 B1
3 3B03-3 6
FB08 B1
FB10 B2
3 3B13-3 6

1K5
7B25
10K

BC847BW 3 4
3B03-4
5
FB11 B1
1K5 FB12 B2
1
FB13 C1

2B03

100n
5 3B13-4 4

FB15 C1
2
10K

FB16 C1
FB20 B7
I FB32
I FB30 G3
PWM-G1
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13
1 2 3 4 5 6 7 8 9 10 11 12 13 14
B001 B002 B007 6 2009-12-04

5 2009-10-28
AL 2K10 LiteOn
8204 000 8978 4 2009-10-07
15 LED Common 3 2009-08-27

2 2009-07-03

18770_600_100212.eps
100218

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 88

LiteOn LED Common 2

LiteOn 15 LED Common 2


AL1B AL1B
1 2 3 4 5 6 7 8 9 10 11 12
2B50 C11
+24V
3B50 B7
3B51 B7

5 3B55-4 4
A 7B50-1
A

10K
BC847BS(COL) 6 3B52 B7
2
3B53-1 B7

3 3B55-3 6
3B53-2 C7

1
10K
FB70
3B53-3 C7
PWM-B2
3B50 3B53-4 C7
+24V 7105 7104 7103 7102 7101 7100
LTW-008RGB LTW-008RGB 270R
3B51
LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB 3B55-1 C3
B B 3B55-2 B3
7 3B55-2 2
5 BLUE 6 5 BLUE 6 270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6
7B50-2

10K
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 3B52 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
68R
3B55-3 A3
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
1
3B53-1
8 3B55-4 A3
1 3B55-1 8

+24V

4
1K5
3B57-2 D3
10K

2 3B53-2 7
1K5
3B57-3 C3

2B50

100n
FB71
PWM-G2 3 3B53-3 6
1K5 3C00-1 G3
C +24V
4 3B53-4 5 C
1K5
3C00-2 F3
3 3B57-3 6

7B51 3C00-3 F3
10K

BC847BW 3

1 3C00-4 E3
3C06-1 G3
7 3B57-2 2

2
10K

3C06-2 H3
D FB72 D 3C10 F4
PWM-R2
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
+24V
3C15-3 G4
3C15-4 G4
5 3C00-4 4

E 7C20-1 E
10K

BC847BS(COL) 6
7100 B11
2
7101 B10
3 3C00-3 6

7102 B9
1
10K

FC01
7103 B7
PWM-B3

+24V
1 3C10 2
7202
7104 B6
270R 7200 7201

F 1 3C11 2
LTW-008RGB LTW-008RGB LTW-008RGB
F 7105 B5
7 3C00-2 2

7C20-2
270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 Blue
7200 F8
10K

BC847BS(COL) 3 3C12 1 GREEN 2 1 GREEN 2 1 GREEN 2 Green

5
68R
3 RED 4 3 RED 4 3 RED 4
7201 F9
Red

1 3C15-1 8
7202 F10
1 3C00-1 8

7B50-1 A3
10K

1K5
3C15-2
2 7

PWM-G3
FC02 1K5 7B50-2 B3
3 3C15-3 6
G +24V
1K5
G 7B51 C3
4 3C15-4 5 7C20-1 E3
1 3C06-1 8

1K5
7C22 7C20-2 F3
10K

BC847BW 3

1 7C22 G3
FB70 B3
7 3C06-2 2

2
10K

FB71 C3
H FC03
H FB72 D3
PWM-R3
FC01 F3
FC02 G3
FC03 H3
1 2 3 4 5 6 7 8 9 10 11 12

6 2009-12-04

AL 2K10 LiteOn 5 2009-10-28

8204 000 8978 4 2009-10-07


15 LED Common 3 2009-08-27
2 2009-07-03

18770_601_100212.eps
100212

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 89

10-2 AL2 820400089773 3 LED LiteOn


3 LED LiteOn

3 LED LiteOn
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2C15 B6
7203 A3
7204 A4
7205 A5
A A

FH12-25S-0.5SH(55)
7203 7204 7205
LTW-008RGB LTW-008RGB LTW-008RGB
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B

2C15

100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22 C
23
24
+24V 25
26 27

1M84

D D

1 2 3 4 5 6 7 8 9 10

B003

3 2009-10-07

3 LED LiteOn 8204 000 8977 2

1
2009-08-27

2009-07-20
AL 2K10 3104 313 63895

18770_630_100212.eps
100218

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 90

10-3 AL1 820400089691 9 LED LiteOn


9 LED LiteOn

9 LED LiteOn
AL2A AL2A
1 2 3 4 5 6 7 8 9 10

1M84 A10
2D01 B6
7203 A3
A A 7204 A4
7205 A5
7203 7204 7205 1M84
LTW-008RGB LTW-008RGB LTW-008RGB
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B

2D01

100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
26 27

FH12-25S-0.5SH(55)

FD04

D D

1 2 3 4 5 6 7 8 9 10

B003 B004

1 2009-10-07

9 LED LiteOn 8204 000 8969


AL 2K10 3104 313 63812

18770_610_100212.eps
100218

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 91

9 LED LiteOn

9 LED LiteOn
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13

2D10 D13
+24V 3D02-1 A1
A A 3D02-2 B1

8 3D02-1 1
7D01-1
3D02-3 B1

10K
BC847BS(COL)
6

2 3D02-4 C1
3D05-3 C1
2 3D02-2 7
10K 1

3D05-4 D1
PWM-B4
FD01
1 3D10 2
3D10 B12
B +24V 7300 7301 7302 7303 7304 7305 270R
+24V
B 3D11 B12
LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB
3D11
1 2
3D12 B12
6 3D02-3 3

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R


7D01-2
10K

BC847BS(COL) 3D12
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
68R
3D13-1 C12
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
3D13-2 C12
4 3D02-4 5

4
3D13-3 C12
10K

1 3D13-1 8

C FD02 1K5
C 3D13-4 D12
PWM-R4

+24V
2 3D13-2 7
1K5
7300 B5
3 3D13-3 6 7301 B6
3 3D05-3 6

1K5
7D02 7302 B7
10K

BC847BW 3 4 3D13-4 5

1
1K5 7303 B8

2D10

100n
7304 B10
5 3D05-4 4

2
10K

D D 7305 B11
PWM-G4
FD03
7D01-1 A2
7D01-2 B2
7D02 C2
FD01 B1
FD02 C1
E E FD03 D1

1 2 3 4 5 6 7 8 9 10 11 12 13

1 2009-10-07

9 LED LiteOn 8204 000 8969


AL 2K10 3104 313 63812

18770_611_100212.eps
100212

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 92

10-4 AL1 820400089703 15 LED LiteOn


15 LED LiteOn

15 LED LiteOn
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5
A A
FD18 C7
FH12-25S-0.5SH(55)

7203 7204 7205 1M84


LTW-008RGB LTW-008RGB LTW-008RGB
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B

2D01

100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
26 27
FD18

D D

1 2 3 4 5 6 7 8 9 10

B003 B004 B005

3 2009-12-07

15 LED LiteOn 8204 000 8970


2

1
2009-10-07

2009-07-02
AL 2K10 3104 313 63823

18770_620_100212.eps
100218

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 93

15 LED LiteOn

15 LED LiteOn
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13 2D10 C13
2D11 H13
3D02-1 A1
+24V
3D02-2 A1
3D02-3 B1

8 3D02-1 1
7D01-1

10K
BC847BS(COL)
6
3D02-4 B1
A 2 3D02-2 7
2
A 3D03-3 H2
1
3D03-4 G2
10K

FD01
3D04-1 F2
PWM-B4

+24V 7300 7301 7302 7303 7304 7305


3D10
+24V 3D04-2 G2
270R
LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB
3D11 3D04-3 E2
6 3D02-3 3

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6


7D01-2 270R
3D04-4 F2
10K

BC847BS(COL) 3D12
B 3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
B
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
68R 3D05-3 C1
3D05-4 D1
4 3D02-4 5

4
10K

1 3D13-1 8
3D10 B12
PWM-R4
FD02 1K5
3D11 B12
2 3D13-2 7
+24V
1K5 3D12 B12
3 3D13-3 6
C C 3D13-1 B12
3 3D05-3 6

1K5
7D02
10K

BC847BW 3 4 3D13-4 5 3D13-2 C12


1K5
1
3D13-3 C12

2D10

100n
5 3D05-4 4

3D13-4 C12
2
10K

FD03
3D15 F12
PWM-G4
3D16 F12
D D 3D17 F12
3D18-1 G12
3D18-2 G12
3D18-3 G12
+24V
3D18-4 G12
7300 B5
E E
3

7301 B6
3D04-3

7D03-1
10K

BC847BS(COL)
6
7302 B7
6

7303 B8
5

1
3D04-4

10K

7304 B10
4

PWM-B5
FD04 7305 B11
3D15
+24V 7400 7401 7402 7403 7404 7405 270R
+24V
7400 F5
F LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB
3D16 F 7401 F6
1

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R


3D04-1

7D03-2
7402 F7
10K

BC847BS(COL) 3D17
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
8

5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4


68R
7403 F8
7

4
7404 F10
3D04-2

10K

1 3D18-1 8 7405 F11


2

FD05 1K5

G
PWM-R5
2 3D18-2 7
G 7D01-1 A2
+24V
1K5
7D01-2 B2
3 3D18-3 6
7D02 C2
5

1K5
3D03-4

7D04
10K

BC847BW 3 4 3D18-4 5
7D03-1 E2
4

1K5
1
7D03-2 F2

2D11

100n
3

2
3D03-3

7D04 G2
10K

FD01 A1
6

H PWM-G5
FD06 H
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1
1 2 3 4 5 6 7 8 9 10 11 12 13

3 2009-12-07

15 LED LiteOn 8204 000 8970 2 2009-10-07

1 2009-07-02
AL 2K10 3104 313 63823

18770_621_100212.eps
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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 94

10-5 AL1 3104313 - 63895, 63812


Layout AmbiLight LiteOn

AmbiLight LiteOn

18 LED

3B35
3B36
FB01 FC01
FB32

3B03
7B06

3B37

3C00
3B31

3B52
7B25 3B51

3B55
B001

B007

B002

B003
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205

3B18
FB04 FB12
FB11
2B09

3B50 2C15

3B30
2B03

3C12
3B53
7B26
1M83 1M84
FB07
3C15

3B01
3B34
3B07

3B13

7B50
7B07
2B01

7C20
FB70 3C11
FB40
3B21 3B22 2B50

7C22
2B17 2B11

7B51
FB05 FB06

2B00
FB41 FB35

3B00
7B30

3C06
3B02
2B04

2B10
2B02
2B20
3C10
7B20
2B08
3B11

7B23 3B57
3004

FB13 FB03
FB20
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71

3104 313 6389.5

24 LED
3B35
3B36

7B26
FB01 FC01 FD02
FB32
3B03

7B06
3B37

3C00
3B31

3B52
7B25 3B51

3B55
B001

B007

B002

B003

B004
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305

3B18
FB04 FB12
FB11
2B09

3B50
3B30

2B03

3C12
3B53

1M83 1M84
FB07
3C15
3B01

FD03
3B34

2D10
3B07

3B13

7D02
7B50
7B07
2B01

7C20
FB70 3C11
FB40
3B21 3B22 2B50 2D01

7C22
2B17 2B11 3D05

7B51
FB05 FB06
2B00

FB41 FB35

3D13
3D10
3B00

7B30 3D02

3D12
3C06
7D01
3B02

2B04
2B10
2B02
2B20

3C10
7B20
2B08
3B11

7B23 3B57
3004

FB13 FB03
FB20 FD04 3D11
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71 FD01

3104 313 6381.2

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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 95

10-6 AL1 820400090592 AmbiLight Common


Everlight LED Common 1

Everlight 15 LED Common


AL1A AL1A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1M83 C1
+3V3 2B00 E8
2B11
2B01 F8
2B02 E9
100n
2B03 I14
A FH12-25S-0.5SH(55)
FB01 7B26-1 A 2B04-1 B7

27
1 +24V TLC5946RHB 2B04-2 B6
3B00-1 VCC
2
BLANK 1 8 31 4 PWM-R1 2B04-3 B8
3 BLANK 0
4 PWM-CLOCK-BUF 150R 24
GSCLK 1
5 PWM-G1 2B04-4 B7
3B18 26 6 PWM-B1
5 IREF 2 2B08 E12
1K8 FB35 3 7 PWM-G3
6 MODE 3
4 3B00-4 5 1 8
7 FB03 PROG
150R 2
SCLK 4
9
PWM-R3 2B09 E12
8 SPI-CLOCK-BUF SIN 5 PWM-R2
9 SPI-DATA-IN-BUF 23
SOUT 6
10 PWM-G2 2B10 F9
SPI-DATA-IN 3 6 11 PWM-B2
10 FB04
3B00-3 150R 3B21 22 OUT
7
14
2B11 A9
11 TEMP-SENSOR SPI-DATA-OUT XERR 8 PWM-B3
12 FB20 +3V3 150R 3B22 25
XHALF 9
15 PWM-G4 2B17 D8
LATCH 2 3B00-2 7 10K 32 16 PWM-R4
B 13
14
FB05
+3V3 FB06 150R
XLAT 10
11
17 PWM-B4 B 2B20 D4
15 BLANK 12
12
18 PWM-B5 3004 E12
FB07 PROG 13 19 PWM-G5
16 13 3B00-1 A6

6
FB08 28 NC 20 PWM-R5
FB10

2B04-2

2B04-1

2B04-4

2B04-3
17 14
3B00-2 B6

100p

100p

100p

100p
LATCH 29 21 DATA-SWITCH
18 15
FB11 SPI-CS
19
+3V3 FB12 GND GND_HS
3B31
+3V3
3B00-3 B6

3
20
3B00-4 B6

30

33
21 PWM-CLOCK 2K0
7B26-2
22
FB13 SPI-DATA-RETURN TLC5946RHB 3B01-1 E7
23
FB15 SPI-DATA-IN 34 VIA 42 3B01-2 D7
24
FB16 SPI-CLOCK 35 41
25 VIA VIA 3B02-1 E3
27 26 36 40
VIA
C C 3B02-2 E5
1M83
3B03-1 H14

37
38
39
3B03-2 H14
3B03-3 H14
3B03-4 H14
+3V3 3B07-1 F3
3B07-2 G3
+3V3
3B07-3 H3
3B34
3B07-4 G3
2B20

100n
SPI-DATA-IN-BUF +3V3 +3V3 3B11 E12
D 100K RES
D

2B17

100n
SPI-CLOCK-BUF +3V3 3B13-3 H3

6
1K5 1%

1K5 1%
7B07 3B13-4 I3

3B39-2

3B39-3
7B20-1
8

M95010-WDW6 74LVC2G17
+3V3 VCC 3B18 A8

5
7B30
5
Φ 2
3B21 B7

3
D Q FB40
2 3B01-2 7 1 3B30-1 8

5
7B06 PWM-CLOCK 1 6 PWM-CLOCK-BUF 1
74LVC1G32GW 6 (64K) 4 TEMP-SENSOR 3B22 B8
5

C 100R 220R
SPI-CS 1 3
LMV331IDCK 3B30-1 D9

RES
2B00

2
4 1

33p
3B02-2

2
S
3B30-4 E9

2B02

2B08
100p

3004
10K
2 7

10n
DATA-SWITCH

3B11
+3V3 HOLD +3V3
1 3B02-1 8 3 7 2
W 10K 3B31 B10

10K
3

-T
10K
GND 3B34 D13
E FB41
E
4

7B20-2 3B35 G14


74LVC2G17

1
3B36 G14

1K5 1%
3B39-1
+3V3

2B09

10n
3B37 G14

5
3B39-1 E13

8
3B01-1 3B30-4
SPI-DATA-RETURN SPI-CLOCK 1 8 3 4 4 5 SPI-CLOCK-BUF
100R 220R
3B39-2 D12
3B39-3 D13

2B01

2
33p
7000 G5

2B10

100p
+24V
7001 G7
7002 G8
F F
8 3B07-1 1

7B23-1 7003 G10


10K

BC847BS(COL)
6 7004 G11
2 7005 G13
7B06 D3
2 3B07-2 7

1
7B07 D4
10K

7B20-1 D8
FB30
7B20-2 E8
PWM-B1
3B35 7B23-1 F4
+24V
+24V 7000 7B23-2 G4
G 99-235/RSBB7C-A24/2D 7001
99-235/RSBB7C-A24/2D
7002
99-235/RSBB7C-A24/2D
7003
99-235/RSBB7C-A24/2D
7004
99-235/RSBB7C-A24/2D
7005
99-235/RSBB7C-A24/2D
270R
3B36
G 7B25 H3
7B26-1 A8
5 3B07-4 4

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R


7B23-2
10K

BC847BS(COL)
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 3B37 7B26-2 C9
68R 7B30 D13
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
FB01 A1
3 3B07-3 6

4 FB03 B1
10K

FB04 B1
1 3B03-1 8 FB05 B1
FB31 1K5 FB06 B2
PWM-R1
H +24V
2
3B03-2
7 H FB07 B1
1K5
FB08 B1
3 3B03-3 6 FB10 B2
3 3B13-3 6

1K5
7B25 FB11 B1
10K

BC847BW 3 3B03-4
4 5
FB12 B2
1K5
1 FB13 C1

2B03

100n
FB15 C1
5 3B13-4 4

FB16 C1
10K

FB20 B7
I FB32
I FB30 G3
PWM-G1
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13
1 2 3 4 5 6 7 8 9 10 11 12 13 14
B001 B002 B007

2 2009-11-27

1 2009-11-03
AL 2K10 Everlight
8204 000 9059
15 LED Common

18770_670_100212.eps
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 96

Everlight LED Common 2

Everlight 15 LED Common 2


AL1B AL1B
1 2 3 4 5 6 7 8 9 10 11 12
2B50 C11
+24V
3B50 B7
3B51 B7

5 3B55-4 4
A 7B50-1
A 3B52 B7

10K
BC847BS(COL) 6

2 3B53-1 B7
3B53-2 C7

3 3B55-3 6

1
10K
3B53-3 C7
PWM-B2
FB70
3B50
3B53-4 C7
+24V 7105
99-235/RSBB7C-A24/2D
7104
99-235/RSBB7C-A24/2D 270R 7103
99-235/RSBB7C-A24/2D
7102
99-235/RSBB7C-A24/2D
7101
99-235/RSBB7C-A24/2D
7100
99-235/RSBB7C-A24/2D 3B55-1 C3
3B51
B B 3B55-2 B3
7 3B55-2 2
5 BLUE 6 5 BLUE 6 270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6
7B50-2

10K 3B55-3 A3
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 3B52 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
1
3B53-1
8 3B55-4 A3
1 3B55-1 8

+24V

4
1K5
3B57-2 D3
10K

2 3B53-2 7
1K5 3B57-3 C3

2B50

100n
FB71
PWM-G2 3 3B53-3 6
1K5 3C00-1 G3
C +24V
4 3B53-4 5 C 3C00-2 F3
1K5
3 3B57-3 6

7B51 3C00-3 F3
10K

BC847BW 3

1
3C00-4 E3
3C06-1 G3
7 3B57-2 2

2
10K

3C06-2 H3
D FB72 D 3C10 F4
PWM-R2
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
+24V
3C15-3 G4
3C15-4 G4
5 3C00-4 4

E 7C20-1 E
10K

BC847BS(COL) 6
7100 B11
2
7101 B10
3 3C00-3 6

7102 B9
10K

PWM-B3
FC01 7103 B7
1 3C10 2
+24V
270R 7200 7201 7202
99-235/RSBB7C-A24/2D
7104 B6
99-235/RSBB7C-A24/2D
F 1 3C11 2
99-235/RSBB7C-A24/2D
F 7105 B5
7 3C00-2 2

270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 Blue


7C20-2
7200 F8
10K

BC847BS(COL) 3 3C12 1 GREEN 2 1 GREEN 2 1 GREEN 2 Green

5
68R
3 RED 4 3 RED 4 3 RED 4 Red 7201 F9
1 3C15-1 8
7202 F10
1 3C00-1 8

4
10K

1K5

2
3C15-2
7 7B50-1 A3
FC02 1K5
PWM-G3
3 3C15-3 6
7B50-2 B3
G +24V G
1K5
7B51 C3
4 3C15-4 5
7C20-1 E3
1 3C06-1 8

1K5
7C22
10K

BC847BW 3
7C20-2 F3
1
7C22 G3
7 3C06-2 2

FB70 B3
10K

H H FB71 C3
FC03
PWM-R3
FB72 D3
FC01 F3
FC02 G3
1 2 3 4 5 6 7 8 9 10 11 12 FC03 H3

2 2009-11-27

AL 2K10 Everlight 1 2009-11-03

8204 000 9059


15 LED Common

18770_671_100212.eps
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 97

10-7 AL1 820400090611 3 LED Everlight


3 LED Everlight

3 LED Everlight
AL2A AL2A
1 2 3 4 5 6 7 8 9 10

1M84 A10
2C15 B6
7203 A3
A A 7204 A4
7205 A5
FH12-25S-0.5SH(55)
7203 7204 7205
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B

2C15

100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22 C
23
24
+24V 25
26 27
1M84

D D

1 2 3 4 5 6 7 8 9 10

B003

1 2009-11-27

3 LED Everlight 8204 000 9061


AL 2K10 3104 313 64201

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 98

10-8 AL1 820400090601 9 LED Everlight


9 LED Everlight

9 LED Everlight
AL2A AL2A
1 2 3 4 5 6 7 8 9 10

1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5
A A

7203 7204 7205 1M84


99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B

2D01

100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
26 27

FH12-25S-0.5SH(55)

D D

1 2 3 4 5 6 7 8 9 10

B003 B004

1 2009-11-03

9 LED Everlight 8204 000 9060


AL 2K10 3104 313 64191

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 99

9 LED Everlight

9 LED Everlight
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13
2D10 C13
+24V 3D02-1 A1
3D02-2 A1

8 3D02-1 1
7D01-1
3D02-3 B1

10K
BC847BS(COL)
6

2 3D02-4 B1
A A
2 3D02-2 7
1
3D05-3 C1
10K

FD01
3D05-4 C1
PWM-B4

+24V
1 3D10 2 +24V 3D10 A12
7300 7301 7302 7303 7304 7305 270R
99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D
1
3D11
2 3D11 B12
6 3D02-3 3

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6


7D01-2 270R
3D12 B12
10K

BC847BS(COL) 3D12
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2

B 5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4


68R
B 3D13-1 B12
3D13-2 C12
4 3D02-4 5

4
10K

1 3D13-1 8 3D13-3 C12


FD02 1K5
PWM-R4
2 3D13-2 7
3D13-4 C12
+24V
1K5
3 3D13-3 6
7300 B5
7301 B6
3 3D05-3 6

1K5
7D02
C
10K

BC847BW 3 4 3D13-4 5 C
1
1K5 7302 B7
7303 B8

2D10

100n
5 3D05-4 4

2
10K

7304 B10
PWM-G4
FD03
7305 B11
7D01-1 A2
D FD04
D 7D01-2 B2
7D02 C2
FD01 A1
FD02 C1
FD03 D1
FD04 D1
1 2 3 4 5 6 7 8 9 10 11 12 13

1 2009-11-03

9 LED Everlight 8204 000 9060


AL 2K10 3104 313 64191

18770_641_100212.eps
100212

2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 100

10-9 AL1 820400090621 15 LED Everlight


15 LED Everlight

15 LED Everlight
AL2A AL2A
1 2 3 4 5 6 7 8 9 10

1M84 A10
2D01 B6
7203 A3
A A 7204 A4
7205 A5
7203
99-235/RSBB7C-A24/2D
7204
99-235/RSBB7C-A24/2D
7205
99-235/RSBB7C-A24/2D
SPI-CLOCK-BUF
1M84

1
FD18 C7
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B

2D01

100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
FD18 26 27

D D

1 2 3 4 5 6 7 8 9 10

B003 B004 B005

1 2009-11-27

15 LED Everlight 8204 000 9062


AL 2K10 3104 313 64211

18770_660_100212.eps
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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 101

15 LED Everlight

15 LED Everlight
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13

2D10 C13
+24V 2D11 H13
3D02-1 A1

8 3D02-1 1
7D01-1
3D02-2 A1

10K
BC847BS(COL)
6

A 2
A 3D02-3 B1
2 3D02-2 7
10K
1 3D02-4 B1
3D03-3 H2
PWM-B4
FD01
3D10
3D03-4 G2
+24V 7300
99-235/RSBB7C-A24/2D
7301
99-235/RSBB7C-A24/2D
7302
99-235/RSBB7C-A24/2D
7303
99-235/RSBB7C-A24/2D
7304
99-235/RSBB7C-A24/2D
7305
99-235/RSBB7C-A24/2D
68R
+24V
3D04-1 F2
3D11 RES
3D04-2 G2
6 3D02-3 3

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 68R


7D01-2
10K

B BC847BS(COL)
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 3D12
B 3D04-3 E2
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3D04-4 F2
4 3D02-4 5

4
3D05-3 C1
10K

1 3D13-1 8 3D05-4 D1
FD02 1K5
PWM-R4
2 3D13-2 7
3D10 B12
+24V
1K5
3D11 B12
3 3D13-3 6
C C 3D12 B12
3 3D05-3 6

1K5
7D02
10K

4 3D13-4 5
BC847BW 3
1K5
3D13-1 B12
1
3D13-2 C12

2D10

100n
5 3D05-4 4

3D13-3 C12
10K

FD03
3D13-4 C12
PWM-G4
3D15 F12
D D 3D16 F12
3D17 F12
3D18-1 G12
3D18-2 G12
+24V
3D18-3 G12
3D18-4 G12
E E
3

7300 B5
3D04-3

7D03-1
10K

BC847BS(COL)
6
7301 B6
6

2
7302 B7
5

1
3D04-4

10K

7303 B8
4

PWM-B5
FD04 7304 B10
3D15
+24V 7400 7401 7402 7403 7404 7405 68R
+24V 7305 B11
F 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D
3D16 RES F 7400 F5
1

5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 68R


3D04-1

7D03-2
7401 F6
10K

BC847BS(COL) 3D17
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2

7402 F7
8

68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4

7403 F8
7

4
3D04-2

10K

1 3D18-1 8
7404 F10
2

PWM-R5
FD05 1K5
7405 F11
2 3D18-2 7
G +24V
1K5
G 7D01-1 A2
3 3D18-3 6
7D01-2 B2
5

1K5
3D03-4

7D04
10K

BC847BW 3 4 3D18-4 5 7D02 C2


4

1K5
1
7D03-1 E2

2D11

100n
3

7D03-2 F2
2
3D03-3

10K

7D04 G2
6

H FD06 H
PWM-G5
FD01 A1
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1
1 2 3 4 5 6 7 8 9 10 11 12 13

1 2009-11-27

15 LED Everlight 8204 000 9062


AL 2K10 3104 313 64211

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 102

10-10 AL1 3104313 - 64201, 64191


Layout AmbiLight Everlight

AmbiLight Everlight

18 LED

3B35
3B36
FB01 FC01
FB32

3B03
7B06

3B37

3C00
3B31

3B52
7B25 3B51

3B55
B001

B007

B002

B003
FB12

7203 7204 7205

3B18
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202
FB04
FB11
2B09

3B50 2C15

3B30
2B03

FB07

3C12
3B53
7B26
1M83 1M84
3C15

3B01
3B34
3B07

3B13

3B22
7B50
7B07
2B01

7C20
FB70

2B04
FB40
2B17

7C22
2B11

7B51
FB41 FB05 FB06 FB35
3B21 2B50

3B00
3C11
7B30

3B02
2B10
2B02
2B20
2B08
3B11

2B00
7B23 7B20 3B57
3004

FB13 FB03
FB20 3C10 3C06
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71

3104 313 6420.1

24 LED
3B35
3B36

7B26
FB01 FC01
FB32
3B03

7B06
3B37

3C00
3B31

3B52
7B25 3B51

3B55
B001

B007

B002

B003

B004
FD03
FB12

3B18
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305
FB04
FB11
2B09

3B50
3B30

2B03

3C12
3B53

1M83 1M84
FB07
3C15
3B01

3B34

2D10
3B07

3B13

7D02
3B22

7B50
7B07
2B01

7C20
FB70
2B04

FB40
2B17

7C22
2B11 3D05

7B51
FB41 FB05 FB06 FB35
3B21 2B50

3D13
3D10
3B00

3C11
7B30 3D02

3D12
7D01
3B02
2B10
2B02
2B20

2D01 FD01 FD02


2B08
3B11

2B00

7B23 7B20 3B57


3004

FB13 FB03
FB20 3C10 3C06 FD04 3D11
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71

3104 313 6419.1

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10-11 B01 820400089943 Tuner, HDMI & CI


Common Interface

Common Interface
B01A B01A
1 2 3 4 5 6 7 8 9 10 11 1P00-A D10
1P00-B G10
2F00 A6
+3V3
3F06
2F01 A2
3F01 CA-RST 100K
2F00
+5V +5VCA TRANSPORT STREAM FROM CAM
7F00
RES
CA-CD1n 4 3F07-4 5
2F02 B6
+T 0R4 100n

20
22u 16V
74LVC245A 10K
2 3F07-2 7
2F03 D6
2F01

1 CA-CD2n
3EN1
3EN2 3F07-3
10K
2F04 E6
RES

19 CA-DATAENn 3 6
A IF01
G3
10K
+3V3
A
CA-MOCLK
3F02
2
1
18 MOCLK CA-DATADIR 1
3F07-1
8 2F05 G6
100R IF02 2 10K
3F03-1
CA-MOVAL
CA-MOSTRT 3F03-2 2 7
1 8
100R
3
4
17
16
MOVAL
MOSTRT CA-ADDENn 1 3F08-1 8
2F06 H6
100R IF03 5
6
15
14 MOCLK
10K
2 3F08-2 7 3F01 A2
7 13 10K
8 12 MOVAL 3 3F08-3 6 3F02 A4
9 11 10K
MOSTRT 4 3F08-4 5 3F03-1 A4

10
10K

MDO0 1 3F09-1 8
3F03-2 A4
B +3V3 10K
2 3F09-2 7
B 3F04-1 C4
2F02 MDO1
RES 10K
7F01 100n MDO2 3 3F09-3 6 3F04-2 C4

20
74LVC245A 10K
1
3EN1 MDO3 4 3F09-4 5
10K
IF04
3F04-3 C4
3EN2

IF05
19
G3
MDO4 1
3F10-1
8
3F04-4 C4
3F04-1 1 8 100R 2 18
CA-MDO0
IF06 2
1 MDO0
MDO5 2
10K
3F10-2
7 3F05-1 C4
CA-MDO1 3F04-2 2 7 100R 3 17 MDO1 10K
CA-MDO2 3F04-3 3 6 100R
3F04-4 4 5 100R
4
5
16
15
MDO2 MDO6 3 3F10-3 6 3F05-2 C4
CA-MDO3 MDO3 10K
C CA-MDO4 3F05-1 1 8 100R
3F05-2 2 7 100R
6
7
14
13
MDO4 MDO7 4 3F10-4 5
10K
C 3F05-3 C4
CA-MDO5 MDO5
CA-MDO6
CA-MDO7
3F05-3 3 6 100R
3F05-4 4 5 100R
8
9
12
11
MDO6
MDO7
3F12
3F05-4 C4
CA-RDY
IF07 +3V3
3F06 A9

10
10K
CA-WAITn 2 3F11-2 7

+3V3 CA-INPACKn 3 3F11-3


10K
6 IF08
3F07-1 A9
+5VCA

15-BIT ADDRESS
2F03
RES CA-WP
10K
4 3F11-4 5
3F07-2 A9
7F02 100n 3F11-1
10K
3F07-3 A9

20
74LVC245A CA-VS1n 8 1 +3V3 ROW_A
1 10K 1P00-A
D 3EN1
3EN2
GND1
1 D 3F07-4 A9
19 CA-ADDENn CA-D03 D3
G3 2

XIO-A00 18 2 CA-A00
CA-D04
CA-D05
D4
D5
3 3F08-1 A9
1 4

XIO-A01 17
2
3 CA-A01
CA-D06
CA-D07
D6
D7
5
6
3F08-2 A9
16 4 CE1
XIO-A02
XIO-A03 15 5
CA-A02
CA-A03
CA-CE1n
CA-A10 A10
7
8
3F08-3 B9
XIO-A04 14 6 CA-A04 CA-OEn OE
XIO-A05 13
12
7
8
CA-A05 CA-A11 A11
A9
9
10 3F08-4 B9
XIO-A06 CA-A06 CA-A09 11
XIO-A07 11 9 CA-A07 CA-A08
CA-A13
A8
A13
12 3F09-1 B9
13
3F09-2 B9
10

CA-A14 A14
E CA-WEn WE|P
RDY|BSY
14
15 E
CA-RDY
+3V3 +5VCA VCC1
16
17
3F09-3 B9
VPP1

7F03
2F04
RES CA-MIVAL A16
A15
18
19 3F09-4 B9
100n CA-MICLK 20
3F10-1 C9
20

74LVC245A CA-A12 A12


21
1 CA-A07 A7
3EN1 22
3EN2
G3
19 CA-ADDENn
CA-A06
CA-A05
A6
A5
23
24
3F10-2 C9
CA-A04 A4
XIO-A08 18
1
2 CA-A08 CA-A03 A3
25
26
3F10-3 C9
CA-A02 A2
2 27

F XIO-A09
XIO-A10
17
16
3
4
CA-A09
CA-A10
CA-A01
CA-A00
A1
A0
28
F 3F10-4 C9
29
XIO-A11
XIO-A12
15
14
5
6
CA-A11
CA-A12
CA-D00
CA-D01
D0
D1
30 3F11-1 D9
31
13 7 D2
XIO-A13
XIO-A14 12 8
CA-A13
CA-A14
CA-D02
CA-WP WP|IOIS16
32
33
3F11-2 C9
11 9 GND2
70 69
34
3F11-3 D9
10

10074595-050MLF 3F11-4 D9
+3V3
2F05
ROW_B
1P00-B 3F12 C9
8-BIT DATA RES GND3
7F04 CA-CD1n CD1
35 7F00 A5
G 100n 36
G
20

74LVC245A MDO3 D11


3EN1
1 CA-DATADIR MDO4 D12
D13
37
38 7F01 B5
3EN2 MDO5 39
G3
19 CA-DATAENn MDO6
MDO7
D14
D15
40 7F02 D5
41
XIO-D00 18
1
2
2 CA-D00 CA-CE2n
CA-VS1n
CE2
VS1
42
43
7F03 E5
XIO-D01 17 3 CA-D01 CA-IORDn IORD
XIO-D02 16 4 CA-D02 CA-IOWRn IOWR
44
45
7F04 G5
XIO-D03 15 5 CA-D03 CA-MISTRT A17
XIO-D04
XIO-D05
14
13
6
7
CA-D04
CA-D05
CA-MDI0
CA-MDI1
A18
A19
46
47 7F05 I5
48
XIO-D06
XIO-D07
12
11
8
9
CA-D06
CA-D07
CA-MDI2
CA-MDI3
A20
A21
49 IF01 A4
H +5VCA VCC2
50
51 H IF02 A5
10

VPP2
52
CA-MDI4 A22

+3V3
CA-MDI5 A23
A24
53
54
IF03 A4
CA-MDI6 55

CONTROL
2F06
RES
CA-MDI7
MOCLK
A25
VS2
56 IF04 B9
57
7F05 100n CA-RST RESET
58 IF05 C4 1X04 1X01
20

74LVC245A CA-WAITn WAIT


59 REF EMC HOLE REF EMC HOLE
1 INPACK
3EN1
3EN2
CA-INPACKn
CA-REGn REG
60
61
IF06 C5
19 CA-ADDENn MOVAL BVD2|SPKR

18
G3
2
MOSTRT BVD1|STSCHG
D8
62
63 IF07 C5
XIO-D11 CA-REGn MDO0
I 17
1
2
3
MDO1 D9
D10
64
65 I IF08 D9
XIO-D09 CA-CE1n MDO2 66
XIO-D08 16 4 CA-CE2n CA-CD2n CD2
67
XIO-OEn 15 5 CA-OEn GND4
68
XIO-WEn 14 6 CA-WEn 72 71
XIO-D14 13 7 CA-IORDn
XIO-D15 12 8 CA-IOWRn 10074595-050MLF
CA-WAITn 11 9 XIO-D10
10

3 2009-10-22

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Flash

Flash
B01B B01B
1 2 3 4
2F20 A3 3F20-1 B1 3F20-4 C2 3F21-3 C1 3F22-2 C1 3F23 C2 IF21 C3
2F21 A3 3F20-2 B2 3F21-1 C1 3F21-4 C2 3F22-3 C2 3F24 D2 IF22 D3
3F19 D2 3F20-3 B1 3F21-2 C2 3F22-1 C2 3F22-4 C2 7F20 B3 IF23 D3

+3V3
A A

2F20

2F21
100n

100n
7F20

12

37
NAND04GW3B2DN6F

B Φ VCC
1
2 B
[FLASH] 3
4Gx16 4
5
XIO-D00 3F20-1 1 8 100R 29 6
0
XIO-D01 3F20-2 2 7 100R 30 10
1
XIO-D02 3F20-3 3 6 100R 31 11
2
XIO-D03 3F20-4 4 5 100R 32 14
3
XIO-D04 3F21-1 1 8 100R 41 IO 15
4
XIO-D05 3F21-2 2 7 100R 42 20
5
XIO-D06 3F21-3 3 6 100R 43 21
6
XIO-D07 3F21-4 4 5 100R 44 22
7
NC 23
24
C NAND-CE1n
IF21
25
26
C
NAND-CLE 3F22-2 2 7 100R 16 27
CLE
NAND-ALE 3F22-3 3 6 100R 17 28
ALE
+3V3 3F23 10K 9 33
CE
XIO-OEn 3F22-1 1 8 100R 8 34
RE
XIO-WEn 3F22-4 4 5 100R 18 35
WE
NAND-WPn IF22 19 38
WP
+3V3 3F24 7 39
R
40
2K2 B
NAND-RDY1n 45
IF23 46
47
3F19

48
10K

D VSS
D
13

36
+3V3

1 2 3 4
3 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 105

USB Hub

USB Hub
B01C B01C
1F24 E9
1 2 3 4 5 6 7 8 9 1F25 B1
1P07 B9
1P08 D9
2F25 A2
2F26 A2
2F27 A2
2F28 A4
IF44 +5V
2F29 A4
+3V3 2F30 A4

+T 0R4
2F31 A5

3F25
2F25

100n
2F32 A5
FF40 2F33 A5
+5V-USB1
3F26-1 2F34 B1
A 1
100K
A 2F35 B2
IF43 3F26-2 3F25 A8
USB-OC1n 2 7
3F26-1 A8
100K 3F26-2 A8
3F26-3 3F26-3 A8
2F26

2F27

2F28

2F29

2F30

2F31

2F32

2F33
100n

100n

100n

100n

100n

100n
3 6

1u0

1u0
100K 3F26-4 B8
3F26-4 3F28 B2
4 5
3F30 C2
100K 3F31-2 C2
3F28

1M0

+3V3 7F25 3F31-3 C2

14

34

36
23
15

10
29
USB2513B-AEZG 3F31-4 D2

5
1F25
B 1 3 CR PLL
FILT
VDD_3V3 USB-DP 9F25 USB-DP2
B 3F32 C8
24M Φ USB-DM 9F26 USB-DM2
3F34-1 C8
4
2

USB HUB 3F34-2 C8


3F35

2F34

2F35
10K

10p

10p

IF33 IF35
33 13 USB-OC1n SIDE USB BOTTOM 3F34-3 D8
XTALIN|CLKIN OSC1

9F20

9F21
USBDP_DN1|PRT_DIS_P1
2 USB-DP1 3F34-4 D8
IF34
32 1 USB-DM1 1P07 3F35 B1
XTALOUT USBDM_DN1|PRT_DIS_M1
12 +5V-USB1
IF30 BC_EN1|PWRTPWR1 1 3F36 D6
RESET-USBn 26 IF36 USB-DM1 FF34
RESET 2 7F25 B2
17 USB-OC2n USB-DP1 FF35
OSC2 3 9F20 B7
11 4 USB-DP2
TEST USBDP_DN2|PRT_DIS_P2 +5V 4
IF42 USBDM_DN2|PRT_DIS_M2
3 USB-DM2 5 6 9F21 B7
3F31-2
2 7 28 16 9F25 B8
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2
IF37 292303-4
10K 9F26 B8
C USB-DP IF31
IF32
31
DP OSC3
19 USB-OC3n
C FF30 E8

+T 0R4
USB-DM 30 USBUP 7 USB-DP3

3F32
DM USBDP_DN3|PRT_DIS_P3 FF31 E9
+3V3 27 6 USB-DM3
VBUS_DET USBDM_DN3|PRT_DIS_M3
BC_EN3|PWRTPWR3
18 FF32 E9
3F30 IF41 3F34-1 FF33
35 1 +5V-USB2 FF33 C9
RBIAS
12K IF40 8
3F31-3 100K FF34 C7
3 6 22 9
SDA|SMBDATA|NON_REM1 3F34-2 FF35 C7
10K 24 NC 20 USB-OC2n 2 7
3F31-4 IF39 SCL|SMBCLK|CFG_SEL0 FF36 D7
4 5 25 21 100K
HS_IND|CFG_SEL1
10K FF37 D7
3F34-3
3 6 FF38 E9
VIA
GND_HS
3F36 100K FF39 E8
37

38
39
40
41

+3V3 USB-OC3n
4
3F34-4
5 FF40 A8
10K
IF30 C2
D 100K SIDE USB TOP D IF31 C1
1P08 IF32 C1
+5V-USB2 1 IF33 B2
USB-DM2 FF36
2 IF34 B2
USB-DP2 FF37
3 IF35 B5
4 IF45
FF32 5 6 IF36 C5
IF37 C5
292303-4
IF39 D2
IF40 C2
IF41 C2
IF42 C2
E FF39 +5V
FF38
1F24
1
E IF43 A3
IF44 A3
USB-DM3 2
USB-DP3
IF45 D9
3
FF30 4
FF31 5
7 6

502382-0570

1 2 3 4 5 6 7 8 9

3 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 106

SD Card

SD Card
B01D B01D
1 2 3 4
1P09-1 C4
1P09-2 D4
2F40 A2
3F40 A2
3F41-1 C1
A A 3F41-2 C1
3F40 FF45
3F41-3 C1
+3V3 +3V3-SD
+T
3F41-4 C1
0R4

22u 16V
3F42-1 C1

2F40
3F42-2 D1
3F42-3 D1
3F43-1 C3
3F43-2 C3
3F43-3 C3
B B 3F44-1 C3
+3V3 3F44-2 C3
3F44-3 C3
3F41-2 IF47 3F44-2
3F45 C1
2 7 SDIO-DAT3 SDIO-DAT3 2 7 FF47
1P09-1
FF41 C3
47K 3F41-3 100R 3F43-2
3 6 SDIO-CMD SDIO-CMD 2 7 FF48
1 FF42 C3
47K 100R 2
+3V3-SD 3 FF43 C3
3F45 RES
SDIO-CLK SDIO-CLK 1 3F44-1 8
4 FF44 D3
C 10K 100R
FF49
5
6 C FF45 A2
3F41-1 3F43-3 7
1 8 SDIO-DAT0 SDIO-DAT0 3 6 FF41
8 FF46 C4
47K 3F41-4 100R 3F43-1 9 FF46
4 5 SDIO-DAT1 SDIO-DAT1 1 8 FF42 1314 FF47 C3
1
3F42-1
8
47K
SDIO-DAT2 SDIO-DAT2 3
3F44-3
6
100R
FF43 1939115-1 FF48 C3
47K 100R FF49 C3
FF50 D3
IF46 D1
1P09-2
2
3F42-2
7 SDIO-CDn SDIO-CDn FF44
IF47 B1
D 47K
10
11 D
3F42-3 IF46 12
3 6 SDIO-WP SDIO-WP FF50
1939115-1
47K

1 2 3 4 TUNER, HDMI & CI


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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 107

PNX85500 Control

PNX85500 Control
B01E B01E
1 2 3 4 5 6 7 8 9
1F51 F8
1F52 D8
2F52 B1
2F53 D6
2F58 D2
A A 3F51 B1
+3V3-STANDBY +3V3-STANDBY
3F52 B3
3F53 C6
+3V3-STANDBY
+3V3 +3V3
3F54 D7
+3V3
3F51

100n
2F52

RES
10K

3F58 E1
3F59 E3
3F60 E3

RES
3F66

10K
3F52

10K
3F62 D5
8
7F52
B B

3F67
M25P05-AVMN6
3F63 E5

RES
10K
BACKLIGHT-BOOST
VCC IF50
PNX-SPI-SDI IF51 2
Q Φ D
5 PNX-SPI-SDO 7F53 RES
PDTA114EU +5V
3F64 F5
512K IF52
3F65 F5
6 PNX-SPI-CLK
FLASH C
IF53 3F66 B7

RES
1 PNX-SPI-CSBn
S
IF54
IF55
3F67 B6
3

3F68

47K
W PNX-SPI-WPn BOOST-PWM
7F54-1 RES 3F68 C7
7 BC847BPN(COL) 6
HOLD +3V3-STANDBY
FF29 IF61 7F54-2 RES
3F69 D7
IF56
VSS SPI-PROG BC847BPN(COL)
4 2
7F52 B2
C IF57
1 C 7F53 B7
4

IF62 5
FF04
SDM 7F54-1 C7
3
7F54-2 C7
3F53
9CH0 FF58
7F58 D1
10K RES 9CH0 C7

RES
RES
FF04 C4

2F53

3F69

3F54

RES
1K0
FF29 C4

1u0

10K
+3V3 MAIN NVM FF55 E3
D D FF56 E3
DEBUG ONLY
FF57 E2
IF58 2F58 RES FF61 3F62 100R
1F52 FF58 C7
SCL-SSB 1 SCL
100n
FF62
2
FF61 D4
SDA-SSB SDA
7F58
3F63
3 FF62 D7
8

FF63 100R 4 5
Φ FF63 E4
3F58

10K

(8K×8) 7 FF64 F7
WC
EEPROM 3F59 FF55
FF65 F4
IF59 1 6 SCL-UP-MIPS
0 SCL
2
1 ADR 100R FF56 FF66 F4
E 3
2 SDA
5
3F60
SDA-UP-MIPS E IF50 B3
100R
4

IF51 B1
FF57 IF52 B3
DEBUG / RS232 INTERFACE LEVEL IF53 B3
IF54 C3
SHIFTED
1F51 IF55 C6
FF65 3F64
TXD-UP
FF64
1
FOR IF56 C7
FF66 100R 3F65 2
RXD-UP UP IF57 C7
3
F RESET-STBYn
SPI-PROG
100R
4 DEBUG F IF58 D2
5
7 6
USE ONLY IF59 E1
IF61 C4
IF62 C4

1 2 3 4 5 6 7 8 9

3 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 108

HDMI & CI

HDMI & CI
B01F B01F
1F75 B5 2F62 B10 2F70 B10 2F75 B8 2F80 B9 2F86 D1 2F93 C2 3F76 C2 3F80 C9 5F71 B9 6F72 C7 9F02 A8 9F71 E4 FF00 B2 FF76 B1 IF12 C9 IF72 C5 IF77 B6 IF82 C4 IF90 D7
1T01 A1 2F63 C9 2F71 A7 2F76 B9 2F81 B1 2F88 E5 2F94 D7 3F77 C4 3F81 C9 5F72 E4 7F70 D8 9F03 A8 AF70 B3 FF01 C4 FF81 C1 IF13 C9 IF73 B6 IF78 B8 IF86 C5
2F59 B1 2F64 C9 2F72 A9 2F77 B9 2F82 B9 2F90 C6 3F71 C7 3F78 C7 3F82 B10 5F73 C5 7F75 A6 9F04 B3 AF71 B3 FF71 A1 FF82 C2 IF14 C9 IF74 B8 IF79 C5 IF87 C2
2F60 B1 2F65 B10 2F73 A9 2F78 B6 2F84 C1 2F91 D6 3F72 C7 3F79-1 B8 5F66 C10 5F74 B10 9F00 A6 9F05 C4 AF72 B9 FF74 B1 IF10 A5 IF15 C9 IF75 B6 IF80 B8 IF88 D2
2F61 B1 2F66 C10 2F74 B6 2F79 B8 2F85 C4 2F92 C7 3F75 D2 3F79-4 B8 5F70 D6 5F76 B10 9F01 A6 9F06 C4 AF73 B9 FF75 B2 IF11 A5 IF16 B10 IF76 B8 IF81 B6 IF89 D5

1 2 3 4 5 6 7 8 9 10

IF10

IF11

A 1T01
TX31XX PNX-IF-P
A
2F71

9F00

9F01

9F02

9F03
FF71 +5V-TUN-PIN
15
TUNER 14
4MHZ_REF 10n

2F72

2F73
15p

1p0
I2C_ADR

I2C_SDA

IF_OUT1

IF_OUT2
RF_AGC

I2C_SCL

7F75
B+_TUN
B+_LNA

1
16 13
RF_IO

UPC3221GV-E1
TUN

NC
AF72

2F65
VCC

15p
IF75 2F74 IF73 2F75 IF76 3F79-1
1F75 2 INPUT1 OUTPUT1 7 IF74 1
10

11

12

2p2 RES
1 4
1

I O1 10n 10n 220R IF16

5F71

2F76

2F77

5F74

2F62

2F70
680n

820n
2 5

22p

10p

1p0
IGND O2 2F78 IF77
3 INPUT2 OUTPUT2 6 IF78
2F79 IF80 3F79-4
AF71 TUN-IF-N 3 4
GND IF81 10n

820R
5F76

3F82
330n
AF70 TUN-IF-P

GND1

GND2
FF74 FF76 220R
B TUN-P1 FF00
9F04 IF-AGC
X7251X
36M17
4 VAGC AGC CONTROL
10n AF73
B
RES
RES

2F80

2F82
15p

1p0
2F81

2F59

2F60

100n

4u7

5
2F61 FF75
4n7

4u7

PNX-IF-N
2F93

100n

IF82 3F77
TUN-P6 FF81 PNX-IF-AGC IF12 IF13
3F80 2F63
TUN-P7 FF82 4K7 IF79 IF-
FF01 220R 10n

5F66

680n

22p
IF-AGC IF72
+5V-TUN-PIN 2F66
+5V-TUN-PIN

3F81 IF14 2F64 IF15

9F05

9F06
IF+
C C

BA591
2F85

3F71

6F72

2F92
4K7

1K0
47n

10n
3F72 220R 10n

IF86 2F90
2F84 3F76 IF87 SCL-TUNER 10n

3F78

3K3
15p 47R 3 5F73 2
TUN-P6 TUN-IF-N

5F70

470n
2F86 3F75 IF88 4 1
SDA-TUNER TUN-IF-P
15p 47R ATB2012 2F91
TUN-P7
10n RES

D IF89
SELECT-SAW
IF90
7F70
D
PDTC114EU

2F94
RES

10n
9F71

E 5F72
+5V-TUN-PIN
E
+5V-TUN
30R RES
2F88

22u

1 2 3 4 5 6 7 8 9 10
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 109

Toshiba Supply

Toshiba Supply
B01G B01G
1 2 3

2FA2 C1
2FA3 C2
2FA4 C3
A A 5FA3 B2
5FA4 B3
7FA3 B2
FFA2 C2
FFAF B2

+3V3 +1V2-BRA-DR1

+1V2-BRA-VDDC

B B

5FA3

5FA4
30R

30R
7FA3
LD1117DT12
FFAF
3 2
IN OUT
COM
2FA2

2FA3

2FA4
100n

100n

10u
1

FFA2

C C

D D

Not yet implemented


1 2 3 TUNER, HDMI & CI
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HDMI

HDMI
B01H B01H
1P05 B1 3FBF-1 C4 3FBF-2 C4 FFB1 C2 FFB2 C2 FFB3 C2 FFB4 C2 FFB5 C1 FFB6 C2

1 2 3 4

A A

HDMI CONNECTOR SIDE


1P05
1 DRX2+ DIN-5V
2
3 DRX2-

B 4
5
DRX1+
B
6 DRX1-
7 DRX0+
8
9 DRX0-

1 3FBF-1 8
10 DRXC+

47K
11
12 DRXC-
13 PCEC-HDMI
14
FFB1 DRX-DDC-SCL DRX-DDC-SCL
15 3FBF-2
FFB2 DRX-DDC-SDA DRX-DDC-SDA 2 7 DIN-5V
16
17 47K
FFB3
C 18
19 FFB4
DIN-5V
DRX-HOTPLUG C
FFB5 21 20
23 22 FFB6

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 111

VGA

VGA
B01I B01I
1 2 3 4 5 6 7 8 9 1E05 B2
1FC1 B4
1FC2 B4
1FC3 C4
1FC4 C4
A A 1FC5 D4
FFC1 3FC5
1FC6 F4
R-VGA
2FC1 B4

CDS4C12GTA
18R
2FC2 B4

2FC1

1FC1

RES 6FC1
100p

12V
2FC3 C4
2FC4 C4
FFC2 3FC6
G-VGA 2FC5 D4
B B

CDS4C12GTA
18R
2FC6 E4

RES 6FC2
2FC2

1FC2
100p

12V
2FC7 E4
1E05 2FC8 F4
1
2 3FC7
3FC1 D3
B-VGA
3
3FC2 E3

CDS4C12GTA
4 FFC3 18R
5
3FC3 C6

RES 6FC3
2FC3

1FC3
100p

12V
6
VGA 7
3FC4 D6
8
CONNECTOR
C 9
10
FFC4 C 3FC5 A6
11
12
FFC5
9FC5 H-SYNC-VGA 3FC6 B6
13
3FC7 C6

RES 6FC4

CDS4C12GTA
14

2FC4

1FC4

3FC3
12V
47p

4K7
15 16 6FC1 B5
17

1216-00D-15S-1EF
FFC6 6FC2 B5
FFC7
6FC3 C5
9FC6 V-SYNC-VGA
6FC4 C5

CDS4C12GTA
D D

RES 6FC5
6FC5 D5
2FC5

1FC5

3FC4
12V
47p

4K7
6FC6 E5
RES
9FC1 VGA-SDA-EDID-HDMI 6FC7 E5
3FC1 FFC8
9FC2 VGA-SDA-EDID 6FC8 F5
RES

CDS4C12GTA
10K
9FC1 D6

6FC6
2FC6

12V
47p

9FC2 E6
9FC3 E6
E RES
3FC2 FFC9
9FC3 VGA-SCL-EDID-HDMI
E 9FC4 E6
9FC4 VGA-SCL-EDID
9FC5 C6

CDS4C12GTA
10K RES

9FC6 D6
2FC7

6FC7

12V
47p

FFC1 A4
FFC2 B4
+5V-VGA FFC3 C4
CDS4C12GTA

FFC4 C3
F
2FC8

1FC6

6FC8

F
12V
47p

FFC5 C4
FFC6 D2
FFC7 D4
FFC8 D4
FFC9 E4
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 112

Temp Sensor + Headphone

Temp Sensor + Headphone


B01J B01J
1 2 3 4 5 6 7 8 9
1328 D6
1329 C6
1FD2 D4
1FD3 D5
2FD1 A4
2FDC D5
2FDD D5
A A
+3V3
3FD1 A3
3FD2 B5

3FD1

3FD2 RES
1K0
RES 3FD3 B3

2FD1

9FD1

9FD2
100n

1K0
3FD4 B2

LTST-C190KGKT
3FD6 C4

8
RES 7FD1
LM75BDP 3FD7 C4
6FD1

+VS
B 3
OS A0
7 IFD1
B 3FDG-1 D4
IFD2
SDA-SSB
3FD3
1
SDA A1
6 IFD3 3FDG-2 D4
100R IFD4
SCL-SSB
3FD4
2
SCL A2
5 IFD5 6FD1 B3

GND
100R
6FD2 D4

3FD6 RES

3FD7 RES

9FD5
1K0

1K0
6FD3 D5
4 7FD1 B3
9FD1 A4
C C 9FD2 A4
9FD5 C5
1329
FFDA D5
1
2
FFDB D5
5 4
3 FFDC D6
502382-0370 IFD1 B4
IFD2 B3
D FFDA 1328
D IFD3 B4
AMP1 2
AMP2 3 IFD4 B3
1
CDS4C12GTA

CDS4C12GTA FFDB
IFD5 B4
8

FFDC
3FDG-1

3FDG-2

2FDC

2FDD
1FD2

6FD2

1FD3

6FD3
1K0

1K0

12V

12V

1n0

1n0
MSJ-035-29D PPO (PHT)
1

E E

1 2 3 4 5 6 7 8 9

3 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 113

Tuner Brazil

Tuner Brazil
B01K B01K
1 2 3 4 5 6 7 8 9 10 11 12 13
1FE0 C2
2FE0 A3
2FE3 A6
2FE4 A6
2FE5 A6
2FE6 B3
2FE8 C3
2FF0 A6
A A 2FF1 A7
5FE0 IF63 IF64 2FF2 B6
+2V5-BRA +1V2-BRA-VDDC 2FF3 B6
30R
2FF4 B6

2FE0

2FE3

2FE4

2FE5

2FF0

2FF1
100n

100n

100n

100n
1u0

1u0
2FF5 B6

+3V3-BRA-FLT
2FF6 B7
2FF7 C6
AGND 2FF8 C6
5FE3 IF65 IF66 5FE4
+3V3-BRA-FLT
+3V3-BRA 2FF9 C7
30R 30R 2FG0 C6
B B 2FG1 C7

2FE6

2FF2

2FF3

2FF4

2FF5

2FF6
100n

100n

100n

100n
1u0

1u0
2FG2 C1
2FG3 C2
AGND
2FG4 D3
5FE5 IF67 IF68 2FG6 D3
+1V2-BRA-DR1
5FE7 IF48 2FG7 E3
30R
+3V3 +3V3-BRA 2FG8 E3
2FE8

2FF7

2FF8

2FF9
100n

100n
1u0

1u0
30R 2FG9 E3
2FH2 D11
2FH3 D12
C IF69 5FE8
+2V5-BRA C 2FH4 D12
30R 7FE3 2FH5 D6
1FE0 LD3985M25
2FH6 E3

2FG0

2FG1
100n
1 3

1u0
5FE9 FF03
25M4 +5V
1
IN OUT
5 +2V5-BRA 2FH7 E3
30R 2FH8 E7
2FG2

4 2
2FG3

3 4
18p

18p

INH BP
3FE5 E7
COM 3FE6 F3
7FE0
3FE7 F3
32

22

20

16
36
56
63

13
35
49
64

34
DR1VDD 48

43

2FH2

2FH3

2FH4
TC90517FG

1u0

10n

1u0
2
AGND AGND AGND
3FE8 F3
AD_DVDD

AD_AVDD

PLLVDD

DR2VDD
19
VDDC Φ VDDS
21
2FH5
I FIL
AGND 3FE9 F3
D 18
O
X
PBVAL
58
1n5
3FG6-4 4 5 33R TS-FE-VALID D 3FG2-1 F6
3 53
DFE6
4 9F27-4 5
3FG2-2 F7
0 RERR TS-DVBS-VALID
2 XSEL 3FG4-1 F7
1 DFE7
RLOCK
54 3FG4-2 F6
IF+ 2FG4 10n IF17 30
IF- 2FG6 10n IF18 29
P
ADI_AI 55
DFE8
2 9F27-2 7 TS-DVBS-SOP
3FG6-2 E7
N RSEORF
3FG6-3 E7
2FG7 100n BFE1 28 59 3FG6-3 3 6 33R
P SBYTE TS-FE-SOP 3FG6-4 D7
2FG8 100n BFE2 27 ADQ_AI
N DFE9
52 9F28 TS-DVBS-CLOCK 5FG0
3FG7 E7
AGND BFE3 SLOCK
2FG9 100n 24 5FE0 A3
BFE4 P
2FH6 100n 25 AD_VREF 61 3FG7 33R TS-FE-CLOCK
N SRCK 30R 5FE3 B3
E AGND
2FH7 100n BFE5 26
AD_VREF SRDT
60 3FG6-2 2 7 33R TS-FE-DATA 5FG2 E 5FE4 B7
39 38
DFF1
1 9F27-1 8
5FE5 B3
AGND DTCLK STSFLG1 TS-DVBS-DATA 30R
IF27 IF28 5FE7 C11
3FE5 AGND
40 9 IF-AGC 5FE8 C7
+3V3-BRA-FLT DTMB AGCCNTI
18K 5FE9 C11

2FH8
8 10

10n
S_INFO AGCCNTR
DFF2 5FG0 E11
3FE6 10K 1 51
41
0
TSMD
STSFLG0 5FG2 E11
1
SYRSTN
42 7FE0 D4
3FE7 10K IF29 7 7FE3 C11
AGCI 3FG2-1
6 RESET-SYSTEMn
11 SLADRS
0
5 10K 3FG2-2 9F27-1 E8
F CKI 1
3FG4-2
10K F 9F27-2 D8
AD_DVSS
AD_AVSS

SCL-SSB 3FE8 100R IF49 45 12


SCL SCL 9F27-4 D8
PLLVSS

SDA-SSB 3FE9 100R 46 TN 14 4K7 3FG4-1


SDA SDA +3V3-BRA-FLT
4K7 9F28 E8
VSS
BFE1 E4
23

31

17

4
15
33
37
44
47
50
57
62

BFE2 E4
BFE3 E4
BFE4 E4
AGND AGND
BFE5 E4
DFE6 D6
DFE7 D6
G G DFE8 D6
DFE9 E6
DFF1 E6
DFF2 F6
FF03 C12
IF17 D4
IF18 D4
IF27 E7
IF28 E7
IF29 F4
H H IF48 C12
IF49 F4
IF63 A4
IF64 A5
IF65 B4

Not yet implemented IF66 B5


IF67 B4
IF68 B5
IF69 C6
1 2 3 4 5 6 7 8 9 10 11 12 13

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 114

10-12 B02 820400089506 PNX85500


PNX NandFlash - Conditional Access

PNX NandFlash - Conditional Access


B02A B02A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3S01-1 E2
3S01-2 E3
3S01-3 E2
3S01-4 E3
3S02-1 E3
3S02-2 E2
3S02-3 E2
A A 3S02-4 E3
7S00-5
PNX85500 3S03 F3
FLASH D25 XIO-D00 3S04-1 F3
00
D26 XIO-D01
01
02
C24 XIO-D02 3S04-2 F3
D23 XIO-D03
NAND-ALE D22
03
C23 XIO-D04
3S15 B6
ALE 04
NAND-CLE C21
CLE
NAND
05
B23
A22
XIO-D05
XIO-D06
3S1R F7
06
XIO-A00 J25
J26
00
XIO_D
07
E22
F24
XIO-D07 3S1S G7
XIO-A01 01 08 XIO-D08
XIO-A02 H21
02 09
F25 XIO-D09 3S1T G7
H22 F26
B XIO-A03
XIO-A04 H23
03
04
10
11
E23
XIO-D10
XIO-D11 B 3S1U G7
XIO-A05 H24 E24
XIO-A06 H25
05 12
E25 INPACK INPACK IS26 3S15 3S23 G7
06 13
H26 E26
XIO-A07
XIO-A08 G21
07
XIO_A
14
D24
XIO-D14
XIO-D15
10K 3S24 G7
08 15
XIO-A09 G22
G23
09
B22
3S28 G7
XIO-A10 10 OE_ XIO-OEn
XIO-A11 G24
11
XIO
WE_
C22 XIO-WEn 3S29 H7
XIO-A12 G25
XIO-A13 G26
12
13 CLK_BURST
B21 7S00-11 E3
XIO-A14 F22
XIO-A15 IS25 F23
14
15 CE1_
E21 NAND-CE1n
7S00-5 A4
D21
CE2_
A20
9S00 F5
C NAND RDY2
RDY1
F21 NAND-RDY1n C 9S08 C5
A21 9S08 NAND-WPn
WP_
IS00
IS00 C5
IS25 C3
IS26 B6

D D

7S00-11
PNX85500

CA-MDI0 3S01-1 8 1 P21 VIDEO_STREAM N26 CA-MDO0


0 0
33R 7 3S01-2 2 P22 M21
E CA-MDI1
CA-MDI2 3S01-3 6 3 33R P23
1
2
1
2
M22
CA-MDO1
CA-MDO2 E
CA-MDI3 33R 5 3S02-4 4 P24 M23 CA-MDO3
3S02-2 3 3
CA-MDI4 7 2 33R P25 MDI MDO M24 CA-MDO4
4 4
CA-MDI5 33R 8 3S02-1 1 P26 M25 CA-MDO5
5 5
CA-MDI6 6 3 33R N21 M26 CA-MDO6
6 6
CA-MDI7 3S02-3 33R 5 3S01-4 4 N22 L21 CA-MDO7
7 7
33R
CA-ADDENn J22
ADD_EN

CA-DATADIR K25 K23 CA-VS1n


DATA_DIR 1
VS K24 9S00 * CA-MOCLK
2
CA-DATAENn K26 RES
DATA_EN
K21 CA-CD1n
3S03 1
N23 CD K22
F CA-MICLK
10R
I
MCLK
2 CA-CD2n
F
CA-MOCLK L25
O CA
3S04-2 +3V3
CA-MISTRT 7 2 N24
MISTRT
3S04-1 33R
CA-MIVAL 8 1 N25 TS-FE-DATA 3S1R
MIVAL
33R 560R
CA-MOSTRT L22 TS-FE-CLOCK 3S1S
MOSTRT
560R
CA-MOVAL L23 TS-FE-VALID 3S1T
MOVAL
560R
J21 TS-FE-SOP 3S1U
OOB_EN
560R
L24
G CA-RDY RDY
TS-FE-DATA
G 1X06
EMC HOLE
CA-RST L26 T21 TS-FE-DATA 3S23
RST DATA
T23 TS-FE-ERR RES 470R
ERR
J23 T22 TS-FE-CLOCK TS-FE-CLOCK 3S24
VCCEN TNR_SER1 MICLK
R23 TS-FE-VALID RES 470R
MIVAL
J24 R22 TS-FE-SOP TS-FE-VALID 3S28
VPPEN SOP
470R
TS-FE-SOP 3S29
470R

H H

1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07

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PNX SDRAM

PNX SDRAM
B02B B02B
1 2 3 4 5 6 7 8 9 10 11
2S12 D4
2S17 E7
2S20 E7
2S24 E7
2S25 E7
A A 3S06 D3
3S07 D3
3S0V F8
3S20 D2
3S22 D2
B B 3S30 C7
7S00-8

DDR2-BA0
PNX85500
H1 MEMORY J1 DDR2-A0
3S33 C8
0 0
DDR2-BA1
DDR2-BA2
H2
G1
1 BA
2
1
2
J3
K1
G4
DDR2-A1
DDR2-A2 3S6P E10
3 DDR2-A3
DDR2-DQM0
DDR2-DQM1
D1
D5
0
1
M0 4
5
L3
G3
DDR2-A4
DDR2-A5
3S6Q E10
DDR2-DQM2 R3 DM L2 DDR2-A6
DDR2-DQM3 T5
2
3
6
7
H5
L1
DDR2-A7
DDR2-A8
7S00-8 B6
A 8

C FS01 D3
DDR2-D0 F3 J5 DDR2-A9
0 9
C +1V8
DDR2-D1
DDR2-D3
C2
F2
1
2
10
11
J2
M3
DDR2-A10
DDR2-A11
DDR2-D2
DDR2-D6
C3
B4
3
4
12
13
J4
M2
DDR2-A12
DDR2-A13
FS02 D2
DDR2-D5 F1 K5 DDR2-A14
DDR2-D4
DDR2-D7
C1
E1
5
6
7
14

N
N5 3S30 DDR2-CLK_N
IS42 E8
100u 2.0V

F4 CLK N4 3S33 DDR2-CLK_P


180R 1%

180R 1%

DDR2-D8 8 P 10R
3S20

3S06

2S12

DDR2-D9 B2 10R
9
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
DDR2-D11 C5 DQS0 E3 DDR2-DQS0_P
FS02 11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
B3 DQS1 D4 DDR2-DQS1_P
180R 1%

DDR2-D14 14 P
3S22

D DDR2-D15 F5
U3
15
DQ R1 D
180R 1%

DDR2-D16 16 N DDR2-DQS2_N
3S07

DDR2-D17 P2 DQS2 R2 DDR2-DQS2_P


17 P
DDR2-D19 U2
18
DDR2-D18 P3 T3 DDR2-DQS3_N
19 N
DDR2-D22 N1 DQS3 T4 DDR2-DQS3_P
20 P
DDR2-D23 U1
21
DDR2-D20 P1 K3 DDR2-CAS
22 CASB 3S6Q
DDR2-D21 T1 K4 DDR2-CKE DDR2-CKE
23 CKE
DDR2-D24 V4 L5 DDR2-CS 10K
24 CSB
DDR2-D30 R5 M4 DDR2-ODT
25 ODT
DDR2-D26 U5 M1
26 PCAL 3S6P
DDR2-D25 P5 M5 DDR2-RAS DDR2-ODT
27 RASB
DDR2-D28 N3 H3 DDR2-WE 10K
28 WEB
E DDR2-D31
DDR2-D27
V3
R4
29
30 1
A2 DDR2-VREF-CTRL2
E
DDR2-D29 V5 VREF V1 DDR2-VREF-CTRL3
31 2

IS42

2S20

2S17

1%
2S24

2S25
100p

100n

100n

100p

3S0V

261R
F F

1 2 3 4 5 6 7 8 9 10 11

6 2009-12-07

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 116

PNX Digital Video In

PNX Digital Video In


B02C B02C
1 2 3 4 5 6 7 8 9 10 11 12 13 14

2S2E F5
3S0W E5
A A 7S00-6 D6
IS01 E6
IS10 E7

B B

C C

D D
7S00-6
PNX85500

HDMIA-RX2+ T25 HDMI_DV


P
HDMIA-RX2- T26 RX0_A
N

HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A
E HDMIA-RXC+ W25
P
E
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W W24
RREF
12K
2S2E

10u

RES

F F

G G

H H

I I

1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 117

PNX Audio

PNX Audio
B02D B02D
2S2G C12 IS1G G7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2S2H D12 IS1K H9
2S2J G12 IS1L F5
2S2K F12 IS1N C7
2S2L D4 IS1S D7
2S2R B7 IS44 H9
2S2S B9
2S2T B8
2S2V B3
A A 2S2W B3
2S2Y C3
2S2Z B3
3S0Z 2S30 C3
3S53-1 +2V5-AUDIO +24V-AUDIO-POWER 2S31 C3
4R7 +24V-AUDIO-VDD
100R
2S32 D3
+3V3
3S53-2
2S33 C3

2S3J

220n
7S08 2S34 B9
100R LD3985M25
1 3S16-1 8 2S36 C6
1 2S2W FS03
3S12-1 8 10K 3S53-3 FS08 5 1 2S38 E9
AUDIO-IN1-L OUT IN
22K 100R IS12 4 2S39 E9
1u0 IS13 3S14

RES
4 3 ADAC(1) 12 7S05-4 2S3A E8
2 BP INH
B 3S53-4 +2V5 LM324 14 3S38
B

2S2R

2S2S
3S16-2 7

10u
2 3S12-2 2S2V 22K +AUDIO-L 2S3B E8
AUDIO-IN1-R 7 10K COM IS02 13

10u
100R 100R 2S3C E8

2S2T

100n
22K 1u0 11 2S3D E8

2S34

100n
2
3S16-3 3 6
3S12-3 6 2S3E E3
3 2S2Z
AUDIO-IN2-L 10K 2S3F E2
22K 1u0 10K 2S3G E3
2 3S36-2 7
3S16-4 5 8 3S36-1 1
2S3H E3
IS0V 4 2S2Y 10K
4 3S12-4

100u 4V
2S3J B11

3S51

2S42

2S41
10K

4R7
5

1u0
AUDIO-IN2-R 2S2G
22K
2S3K G6
1u0
47p 2S3L H8
3S13-4 IS0R 4 3S17-4 5 7S00-2 2S3M H9
2S31
AUDIO-IN3-L 10K PNX85500 +24V-AUDIO-VDD
2S3Q G5
C 4
22K
5
3
1u0
AE10 AUDIO AC7
2S36
1
3S3G-1
8 ADAC(1)
C 2S41 C6
L P
3S13-3 3S17-3 6 AF10 AIN1 ADACL AB7 IS1N 33R 3S3G-3 4
2S42 C6
2S30 R N 1u0 IS03
AUDIO-IN3-R 3 6 10K 3 6 ADAC(2) ADAC(2) 10 7S05-3 3S0Z A11
AD10 AC6 LM324 8 3S39
22K 1u0 L P 33R -AUDIO-R 3S10 D4
AC10 AIN2 ADACR AB6 9
3S17-1 R N 100R 3S11 F5
1 8
3S13-1 2S33 11 3S12-1 B2
AUDIO-IN4-L 10K AE9 AD7
L 1 3S3G-2
1 22K 8 AF9 AIN3 AE7 2 7 ADAC(3) 3S12-2 B2
1u0 R 2
AF7 3S12-3 B2
2 3 33R
3S17-2 7 AD9 ADAC AD6 4 3S3G-4 5 ADAC(4) 3S12-4 C2
2S32 L 4
AUDIO-IN4-R 2 3S13-2 10K AC9 AIN4 AE6 IS1S 33R
7 R 5
AF6
3S13-1 C2
22K 1u0 6 3S13-2 D2
AF8
L
D 3S10
AE8
R
AIN5
OSCLK
AD4
AD1
3 3S36-3 6
10K
5 3S36-4 4
D 3S13-3 C2
3S13-4 C2
I2S_OUT SCK 3S3H 10K
2S2L 100R AB9 AD2 ADAC(5) 3S14 B9
POS WS 2S2H
IS1B AB8 VR_AADC 33R
1u0 NEG
AE1
3S16-1 B3
IS19 1 3S3U 47p
AD8 AF2 ADAC(6)
3S16-2 B3
VREF_AADC 2
AE3 +24V-AUDIO-VDD 3S16-3 B3
IS1A I2S_OUT_SD 3 33R
AC8 AF3 3S16-4 C3
VCOM_AADC 4
3S3F 3S17-1 C3
AF5
SPDIF_OUT 3S17-2 D3

2S3D

2S3C

2S3B

2S3A

2S39

2S38
1n0

1n0

1n0

1n0

1n0

1n0
56R DBS8 3S17-3 C3
AE5 IS07 4
SPDIF_IN1
2S3G
2S3H
2S3E

3S17-4 C3
2S3F

100n

100n

3 7S05-1
10u

10u

ADAC(5)
LM324 1
9S06

AUDIO-OUT-L 3S18-1 G7
E 2 E 3S18-2 G8
11 3S18-3 G8
3S19 H5
3S25 H9
3S32 G12
3S34 G11
3S36-1 C12
3S37 3S6L 3S36-2 B11
10K 22K
3S36-3 D11
2S2K 3S36-4 D12
3S37 F11
+3V3 47p 3S38 B13
F +3V3-ARC F 3S39 C13
+24V-AUDIO-VDD 3S3F E4
3S11
3S3G-1 C7
IS1L 3S3G-2 D8
1R0 3S3G-3 C8
3S3G-4 D7
4
2S3Q

3S3H D7
100n

ADAC(6) 5 7S05-2
LM324 7
IS06 AUDIO-OUT-R 3S3U D8
6 3S51 C6
11 3S53-1 A6
7S09-1
3S53-2 B6
14

74LVC00APW
IS1D
G SPDIF-OUT-PNX SPDIF-OUT-PNX 1 &
3
2S3K
IS1G 1 3S18-1 8 SPDIF-OUT
G 3S53-3 B6
3S53-4 B6
2 220R 3S6L F12
100n 3S34 3S32

2 3S18-2 7

3 3S18-3 6
+3V3 3S6M H8

220R

220R
7

+3V3 10K 22K 7S00-2 C5


2S2J
7S05-1 E12
47p 7S05-2 G12
+3V3-ARC
7S05-3 C12
3S19

+3V3-ARC
10K

7S09-2 7S05-4 B12


14

74LVC00APW 7S09-3
7S08 B8
14

4 & 74LVC00APW
6 9 & IS1K IS44 7S09-1 G6
IS1E 2S3L 180R 2S3M
SEL-HDMI-ARC 5 8 eHDMI+ 7S09-2 H6
H +3V3
10
100n 3S6M 100n H 7S09-3 H7
7

7S09-4 I7
7

9S06 E4

3S25

68R
DBS8 E4
FS03 B12
FS08 B7
+3V3-ARC IS02 B11
IS03 C11
7S09-4 IS06 G11
14

74LVC00APW IS07 E11


12 & IS0R C2
11
IS0V C2
I +3V3
13 I IS12 B8
IS13 B9
7

IS19 D3
IS1A D3
IS1B D4
IS1D G5
IS1E H5

1 2 3 4 5 6 7 8 9 10 11 12 13 14

6 2009-12-07

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 118

PNX Mips

PNX Mips
B02E B02E
1F10 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2S89 D8
3S00 B5
3S21 B1
3S26 C5
3S27 C6
3S40 A1
3S45 A1
3S55 C3
3S56 A5
3S57 A6
+3V3 3S58 A5
A 7S00-3
PNX85500 A 3S5W B6
3S5Y B5
CONTROL C25 1 3S56 2 3S69 1F10 3S5Z B6
IS05 SDA SDA-UP-MIPS SDA-UP-MIPS
3S45 1 C26 100R 1 2 3S57 3S6A 4K7 4K7 FS44
+3V3 BOOTMODE SCL SCL-UP-MIPS SCL-UP-MIPS EJTAG-TRSTn-PNX85500 1 3S60 B5
100R EJTAG-TMS-PNX85500 FS49
10K 2 3S61 B6
BOOTMODE Y21 B26 1 3S58 2 SDA-SET SDA-SET 3S6B 4K7 EJTAG-TDO-PNX85500 FS50
3S40
GPIO1 GPIO1 Y22
GPIO_0
2
SDA
A25 100R 1 2 3S5W SCL-SET SCL-SET 3S6C 4K7 EJTAG-TCK-PNX85500 FS51
3 FOR FACTORY 3S62 B1
+3V3 GPIO_1 SCL 4
RXD1-MIPS Y23 100R EJTAG-TDI-PNX85500 FS52 USE ONLY 3S64 C1
10K GPIO_2 5
DS52 TXD1-MIPS Y24 B25 1 3S5Y 2 SDA-SSB SDA-SSB 3S6D 2K2 3S65 E11
3S82 RES GPIO_3 SDA 3S5Z 6
BOOST-PWM RXD2-MIPS W21 3 A24 100R 1 2 SCL-SSB SCL-SSB 3S6E 2K2 EJTAG-DETECTn FS53 3S66 E11
+3V3 GPIO_4 SCL 7
TXD2-MIPS W22 100R
10K GPIO_5 8 3S67 E11
3S80 FS10 TXD2-MIPS PNX-SPI-CS-AMBIn W23 B24 1 3S60 2 SDA-TUNER SDA-TUNER 3S6F 4K7 10 9
+3V3 GPIO_6 SDA 3S68 E11
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 4K7
+3V3 GPIO_7 SCL 3S69 A9
B +3V3
3S21
10K
PNX-SPI-CS-AMBIn
BOOST-PWM
SELECT-SAW
V23
U23
GPIO_10
GPIO_11 TRSTN
AA25
100R
EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K B 3S6A A8
IS04 AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K +3V3 3S6B A9
10K TMS +3V3-STANDBY FS57 BM08B-SRSS-TBT
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
3S62 PNX-SPI-CS-BLn DN TCK 3S6C B8
+3V3 USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2
IS4Z R24 DP USB TDO
AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4 3S6D B9
10K RREF TDI
10K 3S6E B8
3S00
3S55
RESET_SYS
AE4 RESET-SYSTEMn 3S6F B9
5K6
3S64 FS64 33R 3S6G B8
SELECT-SAW AD5 BACKLIGHT-PWM
+3V3 BL_PWM 3S6H-1 B8
10K 3S6H-2 B9
AC5
CLK_54_OUT 3S6H-3 B9

3S26

3S27
3S6J

10K

10K

10K
3S6H-4 B9
C +3V3
3S83
RXD1-MIPS
C 3S6J C5
3S6K B9
10K 3S72 C6
3S84 +3V3 +3V3
TXD1-MIPS IS40 3S80 B1
+3V3 3S72
10K PXCLK54 3S81 B1
47R 3S82 B1
3S83 C1
3S84 C1
7S00-3 A4
7S00-4 G12
RES
7S01 E8
9S10 F8
D D 9S11 F8
+3V3 9S12 F8
9S13 F8
2S89 DS52 B2
FS10 B2
100n +3V3 FS11 B2
FS2W F9

3
7S01
PCA9540B 3S65 FS2Y F9
VDD SC0 5 SCL-DISP SCL-DISP 2 1 FS31 F8
3S66 4K7 FS44 A12
SC1 8 SCL-BL SCL-BL 2 1
FS49 A12
3S67 4K7
FS50 A12
E SCL-SET 1 SCL
INP
I 2 C
-BUS
SD0 4 SDA-DISP SDA-DISP 2
3S68
1
4K7 E FS51 B12
2 SDA FIL SD1 7 2 1
SDA-SET CTRL SDA-BL SDA-BL FS52 B12
4K7
FS53 B12
VSS
FS57 B12
FS64 C2

6
FS31 IS04 B2
IS05 A2
IS08 F8
IS09 F8
9S10 SCL-BL IS40 C6
IS08 IS4Z B4
F SCL-SET 9S11 FS2W SCL-DISP
F IS50 G12
9S12 FS2Y SDA-DISP
IS09
SDA-SET 9S13 SDA-BL

7S00-4
PNX85500

ETH-RXCLK AA3
RXCLK ETHERNET

G ETH-RXD(0)
ETH-RXD(1)
Y5
Y6
0
1 TXCLK
AA2 ETH-TXCLK
G
ETH-RXD(2) IS50 AB4 RXD ETH
2
ETH-RXD(3) AC1 AA1 ETH-TXD(0)
3 0
AA4 ETH-TXD(1)
1
ETH-RXDV AC2 TXD AB1 ETH-TXD(2)
RXDV 2
ETH-RXER Y4 AB2 ETH-TXD(3)
RXER 3
ETH AA5 ETH-TXEN
TXEN
SDIO-DAT3 W2 AB3 ETH-TXER
CC_DAT3 TXER
SDIO-CLK W1 AC3 ETH-COL
CLK COL
SDIO-CMD W6 Y2 ETH-CRS
CMD CRS
SDIO-DAT0 W5 Y3 ETH-MDC
0 MDC
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
1 DAT MDIO
SDIO-DAT2 W3
2
H SDIO-CDn
SDIO-WP
U6
V6
SDCD
SDWP
H

1 2 3 4 5 6 7 8 9 10 11 12 13 14

6 2009-12-07

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 119

PNX Video Out - LVDS

PNX Video Out - LVDS


B02F B02F
1 2 3 4 5 6 7 8 9 10 11 12 13 14
7S00-7 C8

A A

B B

C 7S00-7
PNX85500 C
PX1A- A7 LVDS D7 PX3A-
N N
PX1A+ B7 A A E7 PX3A+
P P

PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P

PX1CLK- C10 E10 PX3CLK-


N N
PX1CLK+ B10 CLK CLK D10 PX3CLK+
P P

PX1C- A9 LOUT1 LOUT3 D9 PX3C-


N N
PX1C+ B9 C C E9 PX3C+
P P
D PX1D- A11
N N
D11 PX3D- D
PX1D+ B11 D D E11 PX3D+
P P

PX1E- C12 E12 PX3E-


N N
PX1E+ B12 E E D12 PX3E+
P P

PX2A- A14 D14 PX4A-


N N
PX2A+ B14 A A E14 PX4A+
P P

PX2B- C15 E15 PX4B-


N N
PX2B+ B15 B B D15 PX4B+
P P

PX2CLK- C17 E17 PX4CLK-


N N
B17 CLK CLK D17
E PX2CLK+ P
LOUT2 LOUT4
P PX4CLK+
E
PX2C- A16 D16 PX4C-
N
PX2C+ B16 N C E16 PX4C+
C P
P
PX2D- A18 D18 PX4D-
N
PX2D+ B18 N D E18 PX4D+
D P
P
PX2E- C19 E19 PX4E-
N
PX2E+ B19 N E D19 PX4E+
E P
P

F F

G G

1 2 3 4 5 6 7 8 9 10 11 12 13 14

6 2009-12-07

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 120

PNX Stand-by Controller

PNX Stand-by Controller


B02G B02G
1 2 3 4 5 6 7 8 9 10 11 12 13
1S02 B8
2S10 B6
2S11 B5
2S13 B6
2S37 B5
2S4D C3
2S4E E2
2S4F B9
2S4G B9
A A 2S4K G10

+1V1

POL
3S1B C2
3S1C C1
3S1D C2
IS3B
3S1E C1
3S1F C2

5S04
RES

30R
3S1G D2

2S10

100n
1u0
2S13 3S1H D1
2S37 3S1J D2
3S1K D1
1u0 3S1L E2

9S24
RES
3S1P D11
B 2S11 B 3S2A D2
100n 3S2F D7
IS20 DS50 2S4G 3S2G D7

3
3S2H D7
1 10p

AC17
3S2K D7

AA17

AF26

1S02

54M
7S00-9
PNX85500 2S4F 3S2L D10

VDDA_1V1_DCS

VDDA_ADC2V5

VDD_XTAL
3S2M E10
AE17

1
+3V3-STANDBY 2S4D XTAL_IN 10p +3V3-STANDBY 3S2S E10
3S1B 1n0 AD19
RC RC
3S1C RES 10K AE19
0
AF17
3S2V F11
TACHO TACHO 1 XTAL_OUT
10K 3S1D CEC-HDMI CEC-HDMI AF19 3S3L C2
2 P1
3S1E RES 27K BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP AA20 AA26 RESET-STBYn 3S3M C1
3 RESET_IN
C +3V3-STANDBY
10K 3S1F
10K
SDM SDM AB20
7
STANDBY EA
AB24 EA EA
IS3F 3S44 C 3S3N C2
3S3P C1
3S3L RES LCD-PWR-ONn LCD-PWR-ONn AC20
0 ALE IS3E 10K 3S43 3S3Q C2
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
3S3N RES 1 ALE 3S3R D2
10K LAMP-ON LAMP-ON AE20 IS3D 10K
2 10K 3S42
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN 3S3S D1
3 PSEN
10K 3S3Q RES FAN-CTRL1 FAN-CTRL1 AA21 P2 3S3T D1
RES 3S3S 4 3S2F 100R RES 3S6V
10K FAN-CTRL2 FAN-CTRL2 AB21 AC23 SDA-UP-MIPS SDA-UP-MIPS 3S3W E9
5 SDA
10K 3S3R POWER-OK POWER-OK AC21 MC AC24 3S2G 100R SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
3S3T 10K RES AD21
6 SCL 3S3Y D9
ENABLE-3V3n ENABLE-3V3n 7 4K7 RES
10K AD26 3S2H 100R LED1
LED1 RES 3S1P 3S41 D12
+3V3-STANDBY 3S1G 0
RXD-UP RXD-UP AE21 PWM AC25 3S2K 100R LED2 LED2 10K 3S41 3S42 C11
0 1
3S1H 10K TXD-UP TXD-UP AF21 3S43 C11
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO 3S44 C11
3S2A RES 2 SDO
D 10K
DETECT2 AB22
AC22
3
4
P3
SPI
SDI
CLK
AF25
AF24
PNX-SPI-SDI
PNX-SPI-CLK
D 3S46 D10
AD22 AF23 PNX-SPI-CSBn
3S47 E10
5 CSB
3S49 E10
3S1K RES RES 3S2L
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 IS2V CTRL-DISP CTRL-DISP 3S6V C11
0 0 RES 3S46
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS 10K 3S6W D12
10K 1 1
AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K
3S1J KEYBOARD AE24
2 2
AE18 10K 3S47 +3V3-STANDBY 5S04 B6
KEYBOARD 3 3 RESET-ETHERNETn RESET-ETHERNETn RES
LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC 3S2S 10K 7S00-9 B6
100K 2S4E 4
AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP 10K RES 3S2M 7S20 G10
4 5

VSS_XTAL
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 3S3W 10K RES 9S0D G9
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 4K7 3S49 9S0E G9
7

AD17
3S1L
SPI-PROG SPI-PROG 4K7
9S24 B6
10K PNX-SPI-WPn
DS50 B8
E E FS0Z G11
FS45 G9
IS20 B6
IS2U G10
IS2V D7
IS2Z D7
IS3B A6
IS3D C10
IS3E C10
IS3F C10

F F
+3V3-STANDBY +3V3-STANDBY

1 3S2V 2
10K
9S0E
FS0Z
7S20 RESET-STBYn
NCP303LSN28
FS45 2
INP
1 IS2U 1
OUTP
5
CD
NC GND
G G

3
9S0D

2S4K

100n
RES
H H

1 2 3 4 5 6 7 8 9 10 11 12 13

6 2009-12-07

PNX85500
8204 000 8950

18770_517_100118.eps
100118

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 121

PNX Power

PNX Power
B02H B02H
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2S21 F6 2S5K-4 C5
IS3Q 5S80 2S23 B6 2S5M G11
+1V1
30R 2S26 A6 2S5P F5

RES 10u
2S6A

2S5A
100n
2S27 B3 2S60 A6
2S28 B3 2S61 A6

1
5S81 2S29 C6 2S62 A7
A +2V5
A 2S43 B2 2S63 A7

2
30R

RES 10u
2S45 F11 2S64 A7

2S6B

2S5B
100n
2S46 F11 2S65 A7
2S4M B12 2S66 A7

1
+1V8
IS3S 5S82

2S26

2S60

2S61

2S62

2S63

2S64

2S65

2S66

2S67

2S68
100n

100n

100n

100n

100n

100n

100n

100n

100n
2S4N C11 2S67 A8

47u
+3V3
30R

2
2S4P C11

RES 10u
2S68 A8

2S5C

2S5D
100n
2S4Q B3 2S6A A11
2S4R B4 2S6B A11
SENSE+1V1 c001
7S00-10
5S93
2S4S F5 2S6C C11

G6

G7
R6
R7
U7

C6
D6
A5
A6
B5
B6

E6
F6

F7
L6
L7
+2V5
B PNX85500 30R
B 2S4T H11 2S6D B11

2S6E 2

220u 6.3V
VDD_1V8

2S4M
2S6D

100n

100n
AF1 V20
+1V1 2S4U D11 2S6E B11

7
AE2 HDMI_VDDA_1V1 V21

5
AD3
2S4V D11 2S6F C11

1
2S5G-1

2S5G-2

2S5G-3

2S5G-4

2S5H-1

2S5H-2

2S5H-3

2S5H-4
2S4Q

2S4R
2S43

2S28

2S27

2S23
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
AC4 VDD U20

22u

22u

47u

1
AB5
H20
HDMI_VDDA_2V5 U21 2S4W D11 2S6G C11

4
F11 U22 +2V5-LVDS 2S4Y D11 2S6H H11

2
HDMI_VDDA_3V3_TERM
G11
F13 N6 2S4Z E11 2S6K H11

2S4N

2S4P
100n
G13 VDD_2V5 N7

10u
F15 2S50 E11 2S6L I11

2S5J-3 6

2S5J-1 8
8

5
G15 C7
2S51 E9 2S6M I11

2S5K-1

2S5K-2

2S5K-3

2S5K-4

2S5J-2

2S5J-4
C C

100n

100n

100n

100n

100n

100n

100n

100n

100u 2.0V
F17 C9
G17 C11
2S29 F19 VDD_2V5_LVDS C14
5S85 2S52 E9 2S6N C11
1

4
+3V3

2
1 2S6G 2
G19 C16
2S53 H11 2S6P C12

1
30R

2S6N

2S6C

2S6P
2S6F

100n

100n

100n

100n
J9 C18

10u
J11 2S55 G11 2SHW I11
AA16
AA8
Y11
Y14

J13 W20
Y16
Y9

7S00-12

1
PNX85500 J15 P20 2S56 G11 5S80 A12
VSSA J17 M20
A1 M7 L9 VDD_3V3 K20
+3V3-STANDBY
2S57 G11 5S81 A12
A10 N2 L11 V7
2S58 H11 5S82 A12

2S4U
2S4V

100n
A12 N20 L13 Y8

10u
A15 P10 L15
A17 P12 L17
VDD_1V1
Y19 2S59 I11 5S83 D12
D A19
A26 VSS
P14
P16
N9
N11
VDD_3V3_SBY Y18
IS3K 5S83
D 2S5A A11 5S84 E12
A3
A8
P18
P4
N13
N15
VDDA_1V1_LVDS_PLL
B13
+1V1 2S5B A11 5S85 C12
IS3L 30R

2S4W
2S4Y
2S5C B11

100n
B1 P6 N17 AA15
5S87 F12

RES 1u0
B20 P7 R9 Y15
VDDA_1V2
C20 T10 R11 AA13 2S5D B11 5S88 G12
C4 T12 R13 5S95 +2V5
D2
VSS
VSS T14 R15
VDDA_2V5
Y12
5S84 2S5G-1 B4 5S89 H12
D20 T16 R17
30R 2S5G-2 B4 5S90 H12

6.3V
E13 T18 U9 AA9 +1V2
VDDA_2V5_AADC 30R

2S4Z
2S51

2S52

2S50
100n

100n
E20 T2 U11

10u
E4 T6 U13 AA7 c000 SENSE+1V2 2S5G-3 B4 5S92 I12

10u
VDDA_2V5_ADAC
F10 T7 U15
2S5G-4 B5 5S93 B12
E F12
F14
U4
V10
U17
J6
VDDA_2V5_DCS
Y17
E 2S5H-1 B5 5S94 F5
F16 V12 AA6 D13
VDDA_2V5_LVDS_BG
F18
F20
V14
V16
Y7
W7 T20 POL 2S5H-2 B5 5S95 E10

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG
VDDA_2V5_USB
F8 V18 F9 2S5H-3 B5 7S00-10 B6
G10 V2 G9 Y13 +2V5-AUDIO
VDDA_2V5_VADC
G12 Y20 2S5H-4 B5 7S00-12 C1

V24 HDMI_AGND
5S94

2S46

100n
J7 Y10

VSSA_USB
VSS +1V1
30R
VDD_1V1_DDR VDDA_2V5_VDAC
2S5J-1 C5 IS3K D10
2
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

R21
VDDA_3V3_USB 2S5J-2 C5 IS3L D10
2S4S

2S5P

2S21
100n
10u

1u0

RES
2S5J-3 C5 IS3Q A10

U24

A13

C13

R20
1

F +2V5-AUDIO F 2S5J-4 C5 IS3S A10


2S5K-1 C4

2S45

100n
IS58 I10
2S5K-2 C4 c000 E13
5S87 2S5K-3 C4 c001 B5
+2V5
30R

2S55

2S56
100n

1u0
G 5S88
+2V5-LVDS
G
30R

2S5M

2S57
100n

10u
5S89
+2V5

2
30R

2S6H

2S6K
100n

100n
2S58

10u
1

1
H 5S90
+2V5
H
30R

2S4T

2S53
100n

10u
2SHW

100n
I I
IS58 5S92
+3V3

2
30R

2S6M

2S6L

2S59
100n

100n

1u0
1

1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07

PNX85500
8204 000 8950

18770_518_100118.eps
100118

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 122

PNX Analog Video

PNX Analog Video


B02I B02I
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2S14 D12
2S15 D12
2S16 D12
2S87
AV1-CVBS
2S18 D12
22n 2S8A 9S17 Y-SVHS 2S19 D12

3S59
47R
Connectivity 22n
2S22 A11

3S5B
47R
A A 2S40 B11
AV1-R 2S7J 2S75 F11
22n 2S22 C-SVHS
2S76 F11

3S4J
2S77 F12

56R
22n

3S05

56R
2S78 G12
2S7E G6
EU: SCART1 CVBS-MON-OUT1 2S7H B6
AV1-B 2S7K
AP: - 2S7J A6

3S5E

560R
22n

2S7K B6

3S4L
56R
B B 2S7L C6
IS4V
2S7M C6
2S7N D6

560R
2S40

3S08
47p
2S7H
AV1-G 2S7P D6
22n 2S7Q E6

3S4K
56R
IS4W
2S7R F6
2S7U F6

3S09

8K2
C C 2S84 G6
2S7M
YPBPR1-SYNCIN1 2S85 H6
10n
2S7L
2S86 H6
AV3-Y
2S87 A6
22n

3S4P
2S8A A11

56R
2S8G E6
2S7N
AV3-PR 3S05 A11
EU: YPBPR1 22n
3S08 B11

3S4R
56R
D AP: YPBPR1
7S00-1
PNX85500 D 3S09 C11
2S7P ANALOG_VIDEO 3S4G G6
AV3-PB
22n
AB15
CVBS_Y1 ATV_CVBS_Y3 AC12 3S4J A6

2S19

2S18

2S16

2S15

2S14
3S4T
AC13 IS5C

56R
AF13

22n

22n

22n

22n

22n
R C3
AD13
AE13
B AV1
AD11
3S4K C6
G CVBS_Y7
C7
AC11 3S4L B6
AV2-CVBS 2S8G AF15
AE15
SYNCIN1
Y_G1 CVBS1_OUT
AF11
BS13
3S4P D6
22n AC15 AE11
PR_R_C1 CVBS2_OUT 3S4R D6

3S5L
AD15

47R
PB_B1
AB14
RESREF AB10
AA11 IS5E 3S5S
3S4T D6
E 2S7Q
AF14
CVBS_Y2
SYNCIN2
CURREF
10K E 3S4U F6
YPBPR2-SYNCIN2 AE14 AC16 IS5D
Y_G2 1
10n
AC14
PR_R_C2 2 AB16 IS5F
IS5G
3S4W F6
AD14 AB13
PB_B2 3
REF 4 AB12 IS5H 3S50 H6
AF16 AA12 IS5J
AD16
R
G VGA
5
6
AA10 3S75
PNX-IF-AGC 3S52 H6
AE16
B 47K 3S54 I6

2S75
2S7R AB18 BS15

10n
AV4-Y HSYNC_IN IF_AGC AD12
AC18 BS17
EU: 22n AF4
IN
VSYNC
RF_AGC AB11
3S59 A6
SCART2 OUT
3S4U

AD24 BS09 3S5B A11


56R

SCL VGA_EDID P AE12


AP: YPBPR2 AD25
SDA TUNER N AF12 BS10
3S76 IS11
3S5E B11
F +CVBS 47K
PNX-RF-AGC
F
3S5L E6

2S76
AGND

10n
AA14
AV4-PR 2S7U
3S5S E9
22n
3S5T-1 I5
3S4W
56R

2S77
PNX-IF-P 3S5T-2 I11
10n
3S5T-3 I5
2S7E
3S5T-4 I11
AV4-PB
22n 2S78
3S5V-1 I5
3S4G
56R

G 10n
PNX-IF-N
G 3S5V-2 I12
3S5V-3 I5
R-VGA
2S84 3S5V-4 I12
22n 3S75 E12
3S50
56R

3S76 F12
7S00-1 D8
G-VGA
2S85 9S14 I3
22n 9S15 I3
3S52
56R

H H 9S17 A13
BS09 F9
2S86
B-VGA BS10 F10
22n BS13 E9
3S54
56R

EU: VGA
BS15 F9

4 3S5T-4 5

2 3S5T-2 7

4 3S5V-4 5

2 3S5V-2 7
AP: VGA

100R

100R

100R

100R
H-SYNC-VGA 1 3S5T-1 8
BS17 F10
100R IS11 F13
V-SYNC-VGA 3 3S5T-3 6 IS4V B10
100R
IS4W C10
I VGA-SCL-EDID 3 3S5V-3 6
I IS5C D9
100R IS5D E9
VGA-SDA-EDID 1 3S5V-1 8 IS5E E9
100R
VGA-SCL-EDID-TCON 9S14
* IS5F E9
VGA-SDA-EDID-TCON 9S15
* *
= TCON ONLY IS5G E9
IS5H E9
IS5J E9
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07

PNX85500
8204 000 8950

18770_519_100118.eps
100118

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 123

10-13 B03 820400089514 CLASS D


Audio

Audio
B03A B03A
1 2 3 4 5 6 7 8 9 1735 E8 FD06 E8
1D38 E9 FD07 F4
1D50 E8 FD14 A5
1D52 F8 ID05 C8
2D01 F7 ID06 C8

+AVCC
2D02 F4 ID07 C8
7D03-1 +24V-AUDIO-POWER 2D03 E3 ID08 C8
3D09 BC847BS(COL) FD14 2D05 A5 ID09 C7

1
+24V-AUDIO-POWER
2D06 A5 ID10 C7
4R7
A A 2D07 B5 ID11 A4

2D06

220n
2D08 B6 ID12 A5
2D09 C7 ID13 E3

2
3D16 ID12
ID11 2D10 C7 ID14 B3

5D07

220R
5D08

220R
22K
2D11 C8 ID15 B3

10u 35V
GND-AUDIO

2D05
2D12 C8 ID18 C5
2D13 F8 ID19 C5
ID27 ID28
FD01 2D28 ID14 2D24 2D14 E8 ID27 B6
-AUDIO-R
2D16 C4 ID28 B6

220u 35V

220u 35V
1u0 47n 2D17 C4 ID29 C5

8
2D20

2D07

2D19

2D08
220n

220n
6

3D02-1

3D14-4

3D14-3

3D14-2

3D14-1

2D22

2D26
220n

220n
2D19 B6 ID30 C5

4K7

22K

22K

22K

22K
3D02-3
A-PLOP 6 3 2 7D15-1 2D20 B5 ID31 C6
B BC847BS(COL)
B 2D21 D8 ID32 C6

1
4K7
1
2D22 B8 ID33 F4
2D23 B4 ID34 D3
GND-AUDIO GND-AUDIO 2D24 B4 ID35 D3
2D26 B8 ID36 E2
7D10-1
FD03 2D29 ID15 2D23 TPA3120D2PWP 2D27 D8 ID37 D4

19
20

10
12
+AUDIO-L

1
3
2D28 B2 ID38 D5
1u0 47n AVCC L R
2D29 B2 ID39 E2

5
3

3D02-4
PVCC ID32 2D10
Φ 16 3D01-1 D3

4K7
3D02-2 ID19 BSR ID10 5D02 5D05 2D12 RIGHT-SPEAKER
7 2 5 7D15-2 6 3D01-2 D3
BC847BS(COL) ID18
R CLASS-D 15
220n
ID06 ID08 3D01-4 E2

4
4K7 IN R 22u 220R 25V 220u
4 5 AUDIO AMP
L OUT 3D02 B3
C 18
0
L
22
ID31 2D09
ID09 5D01 5D04 ID07 2D11 LEFT-SPEAKER C 3D02 C3
17
1
GAIN
BSL
21 22u ID05 220R 25V 220u
3D02 B4
GND-AUDIO 2D16 ID29 220n 3D02 C4
11
VCLAMP 3D04 E2
2D17 1u0 7
BYPASS 3D06-1 F4
1u0 ID30 4
MUTE 3D06-2 F4
2
AUDIO-MUTE-UP ID37 SD
3D06-3 F3
PGND
AGND L R 3D06-4 F3
A-STBY ID38 GND_HS
3D09 A3

8
9

23
24

13
14

25
3D10-1 D8

5
3D15-4
+3V3-STANDBY 3D10-2 D8
8

8
4K7
3D01-1

3D10-4

3D10-3

3D10-2

3D10-1
D D

2D21

2D27
220n

220n
6 3D10-3 D7
47K

22K

22K

22K

22K
CD10
MAINS SWITCH DETECT 3D10-4 D7
4
7D11-1 2
3D14-1 B8
1

1
BC847BS(COL)
ID34 GND-AUDIO 3D14-2 B8
1 3 +3V3-STANDBY
+3V3-STANDBY ID35 3D14-3 B7
3D01-2
7D11-2 5 2 7 DETECT2 3D14-4 B7
5

BC847BS(COL) 3D15-1 E2
47K
3D01-4

6 4
47K

GND-AUDIO GND-AUDIO 3D15-2 E3

40
39
38
2D03
100p

GND-AUDIO 7D10-2
7D13-1 2 TPA3120D2PWP 3D15-4 D5
4

BC847BS(COL) LEFT-SPEAKER 3D16 A5


ID36 VIA
1 3
GND-AUDIO GND-AUDIO 26 37 5D01 C7
ID39 +AVCC 27 36
VIA 5D02 C7

V_NOM
3D15-1 3D15-2 ID13 6D01
E E

1D50

2D14
7D13-2 5 1 8 7 2 28 VIA VIA 35

10n
BC847BS(COL)
5D03 E7
4K7 4K7 29 34
BZX384-C GND-AUDIO GND-AUDIO 5D04 C8
4
VIA 5D05 C8
3D04
2K2

MAINS-OK
1735 1D38 5D07 A6
30
31
32
33

FD05 5D08 A6
GND-AUDIO GND-AUDIO 5D03 1 1
FD06
2 2 6D01 E3
GND-AUDIO 220R 3 3 7D03-1 A5

2D01
GND-AUDIO FD02

10n
GND-AUDIO 4 7D03-2 F5

2D13
3 7D03-2 1735446-3

10n
BC847BS(COL) 1735446-4 7D10-1 B6
3D06-4 FD07 3D06-2
LEFT-SPEAKER 5 7D10-2 E5
4 100K 5 7 2
100K 7D11-1 D2
4
7D11-2 D3
F 8
3D06-1
1
ID33
RIGHT-SPEAKER
F 7D13-1 E1
7D13-2 E2

V_NOM
100K

1D52
GND-AUDIO 7D15 B3
7D15 C3
2D02
RIGHT-SPEAKER 3
3D06-3
6 CD10 D5
FD01 B1
100K 10u
GND-AUDIO
FD02 F8
FD03 B1
FD05 E8
1 2 3 4 5 6 7 8 9
4 2009-10-22

CLASS D
8204 000 8951

18770_520_100118.eps
100218

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 124

DC/DC

DC/DC
B03B B03B
2U00 D2 2U04 F4 2U08 G9 2U12 F11 2U16 C10 2U20 B14 2U24 B5 3U01 F1 3U05 E4 3U11 B6 3U19 G9 3U23-1 C9 3U24-1 F9 3U27 D5 5U02 B13 7U01 D8 7U04 E8 FU02 B9 FU06 E8 IU04 G3 IU08 D4 IU12 D7 IU16 E5 IU20 G9 IU24 E3
2U01 E3 2U05 F4 2U09 F9 2U13 F12 2U17 C9 2U21 C6 2U25 B12 3U02 F2 3U08 G2 3U14 D7 3U20 F11 3U23-2 C9 3U24-2 F9 3U28 D5 5U03 A13 7U02-1 B6 CU00 H7 FU03 C14 IU01 F3 IU05 D3 IU09 C6 IU13 D7 IU17 F9 IU21 H9 IU25 F4
2U02 D4 2U06 F1 2U10 F10 2U14 E14 2U18 D9 2U22 D8 2U29 G14 3U03 F3 3U09 H3 3U17 G10 3U21 G13 3U23-3 C9 3U24-3 F9 5U00 C10 6U00 E8 7U02-2 C6 FU00 G13 FU04 F4 IU02 F3 IU06 D3 IU10 B 6 IU14 E8 IU18 F9 IU22 B13
2U03 E2 2U07 H3 2U11 F9 2U15 C10 2U19 B12 2U23 B5 3U00 F1 3U04 D3 3U10 H3 3U18 G10 3U22 G2 3U23-4 C8 3U24-4 F8 5U01 E10 7U00 F1 7U03 E3 FU01 E14 FU05 B9 IU03 F1 IU07 D4 IU11 C6 IU15 C9 IU19 G10 IU23 C9

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A A

5U03 RES

30R
FU05 5U02 IU22
+12V
30R
7U02-1

2U24

2U23

2U25

2U19

2U20
10u

10u

10u

10u

1u0
SI4952DY
B IU10
7 8 B
2
12V/1V8 CONVERSION

1
3U11

3R3
2U21 FU02 5U00 FU03
+1V8
IU11 220p 3u6

3 3U23-3 6

2 3U23-2 7

1 3U23-1 8

22u
3U23-4

2U15

2U16
47R

47R

47R

47R

47u
7U02-2
SI4952DY

4
5 6
C IU09
4 IU23 C

2U17

1n0
IU15
7U01
SI4778DY

2U18

1n0
3U27 5 6 7 8
IU08 IU12
4
10R 1 2 3

D D
2U00

3U14
10u

3R3
3U04

3R3

2U22
IU06 2U02 IU07
IU05 IU13 220p
3U28

10R

100n
2U01

3U05
100n

3R3

7U04
7U03 SI4778DY
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
12V/1V1 CONVERSION
E ENABLE-1V8
3
10
1
2
EN DRVH
1
2
1
12 E
1n0 RES

FU06 5U01 FU01


2U03

+1V1 4 24 +1V1
1 1

STPS2L30A
+1V8 9 VO SW 13

RES 100u 2.0V


2 2 2u0

6U00

2U14
5 22

3U24-4

3U24-3

3U24-2

3U24-1
1 1

3U20

2U12

2U13
8 VFB PGND 15

22u
47R

47R

47R

47R

10R
RES

47u
RES GND-SIG 2 2
7U00 3U02 IU01
BC847BW 21 7
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 22K IU02 GND-SIG
GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5
F F

2U11

1n0
+3V3-STANDBY 3U00 2U06
+1V1 GND
2U04

2U05
6

10u

1u0

10K 100n
IU18
10K
3U01

GND-SIG

2U09

2U10
1n0

1u0
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%

3U17

1% 330R

2U29

100n
RES
G IU20 G

100p RES

3U19
2U08

3U18
5K6

1% 1K0
3U08 3U22
IU04
+1V8
330R 1% 1K0 1% IU21
RES 100p
1K0 1%
3U09

3U10

2U07
22K

GND-SIG GND-SIG GND-SIG


CU00

H GND-SIG GND-SIG GND-SIG


GND-SIG
H

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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DC/DC

DC/DC
B03C B03C
1 2 3 4 5 6 7 8 9 1M95 E1 3U84 D2
1M99 C1 6U40 E3
1U40 E2 7U40-1 F4
2U41 B1 7U40-2 E4
2U42 C2 7U41-1 F4
2U43 D2 7U41-2 F5
2U44 D3 7U42 B5
2U45 D3 7U43 B3
2U46 D3 7U48-1 C6
A +3V3 +3V3-STANDBY A 2U47 E1 7U48-2 E6
2U48 F1 9U41 B5
LED-2
2U49 F1 9U42 B4

RES 10K

RES 10K
3U74

3U75
+5V +3V3-STANDBY
2U50 F1 FU07 C3
IU43
2U51 D1 FU48 C1
9U41
2U52 D1 FU49 C1

RES 10K
2U53 D2 FU50 C1

3U68

3U69
10K
LED-1
IU44 2U54 F2 FU51 C1
3U41 LED2 LED2 3U59
IU45 2U55 F3 FU52 C3
B ∗ optionally 1M99 is a 9 pin connector 9U42
RES
10K RES 10K RES
B 2U68 E1 FU53 C2
7U42 RES +3V3 2U71 D5 FU54 C2
BC847BW 2U72 D1
IU47
FU55 C1
2U41 RES

3U70 3U53
7U43 LED1 LED1 3U41 B5 FU56 D1
BC847BW
100p 10K 10K 3U42 C3 FU57 D1
+12VD
3U43 C3 FU58 E1
3U44 C3 FU59 E1
1M99
FU48 2U42 3U45 C3 FU60 E1
1 3U81 IU56
2
FU49
1u0 +3V3 3U53 B6 FU61 E1
FU50
3 10K 3U56 D3 FU62 E1
4
C 5
FU51
FU52
3U45
LAMP-ON
IU64
C 3U59 B6
3U60-1 F5
FU63 E1
FU64 F1
6 100R 3U82
FU53 3U42 BACKLIGHT-PWM_BL-VS
7 3U60-2 F4 FU65 F1
8 100R 1K0 RES
9
FU55 3U64 3U43 BACKLIGHT-BOOST
7U48-1
3U60-3 E5 FU66 F1
10 1K0 FU54 100R
3U44
FU07
BACKLIGHT-PWM-ANA-DISP 4
3U83-4
5
BC857BS(COL)
ENABLE-3V3-5V
3U60-4 F5 FU67 F1

6
11 3U61 E5 FU68 F1
RES 1K0
RES 100p

RES 100p

12 100R 100K
100p
2U51

2U52

2U53

3U65

1n0

10n
10n

3U62-1 F4
1n0

3U56 IU41 FU72 F4


100p

1
1-1735446-2
3U62-2 E3

3U83-1
FU73 E5
2U72

100K
+3V3

2
10K
2U44

2U45

2U46
2U43

2U71
3U62-3 E4

100n
FU74 D1
RES

IU55 3U62-4 E3

8
POWER-OK
IU40 E5
D 3U66
BL-SPI-SDO
D 3U63 F5
3U64 C2
IU41 D5
FU56 IU43 B5
RES 100R 3U67
BL-SPI-CSn +3V3-STANDBY
3U65 D2 IU44 B5
FU57
100R RES 3U84 3U66 D2 IU45 B4
BL-SPI-CLK

3
FU74 3U67 D2 IU47 B4
100R RES 3U71
STANDBY 3U68 B3 IU48 E4
7U48-2
2U68 100R BC857BS(COL) 3U69 B3 IU49 E3

5
3U70 B4 IU50 F4
5

7U40-2 3U83-2
3U62-4

1u0 3U83-3 7 2
3 6 3U71 D3 IU51 F3
10K

BC847BPN(COL)
2U47
4
IU48 100K IU40 100K 3U72 F3 IU52 F5
4

10n
E 1M95
+3V3-STANDBY
5
E 3U73 F3 IU55 D3
2

FU58 3
3U74 A4 IU56 C3
3U62-2

1 3U60-3 FU73
FU59 3 6 ENABLE-1V8
10K

2 IU61
FU60 3U75 A4 IU57 F6
BZX384-C6V2

3 22K
RES 10K
6

3U61

FU61 3U76 F2 IU61 E4


7

3U62-3

4
6U40

FU62
10K

5
FU63
1U40 +12V IU49 3U80 F4 IU62 F4
6 6
2

FU64 7U40-1 3U81 C3 IU63 F3


3
3U60-2

7 T 3.0A 32V IU51 FU72


22K

FU65 BC847BPN(COL) DETECT2 3U82 C5


8 FU66 2 IU64 C6
9 +24V-AUDIO-POWER
3U83-1 D6
3U72

FU67 1
1K0

7U41-2
7

10 FU68 3U76
1u0 RES

MAINS-OK 3 BC847BS(COL) 3U83-2 E5


11 IU63
5
2U55

100R IU57
3U83-3 E5
3U60-4

3U60-1 ENABLE-3V3n
100p RES

3U80
100p RES

1-1735446-1 5 8 1
4K7

22K

F GND-AUDIO 3U73 3U62-1 IU50


IU62
22K F 3U83-4 C5
2U48

2U49

2U50

2U54

4 IU52
10n

10n

+3V3-STANDBY
8 1
10K 6
3K3
3U63

RES 10K

7U41-1
BC847BS(COL) 2
1

1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 126

DC/DC

DC/DC
B03D B03D
1 2 3 4 5 6 7 8 9 2UA0 A5 3UB3 F6
2UA1 A4 3UB4 F5
2UA2 B5 3UB5 F5
RESERVED 2UA3 B5 3UB6-1 C2
2UA4 A7 3UB6-2 C2
+2V5-REF +12V +3V3
7UC0
LF25ABDT
∗ 2UA5 B6 3UB6-3 C2

3K3 1%

1K0
2UA0
2UA6 B7 3UB6-4 C2

3UA4
+12V 1 3
A 3UA1
100n 7UA2
PHD38N02LT
IN
COM
OUT
A 2UA7 D4 3UB7-1 D3

2UA4
3UB7-2 D2

1u0
7UA1-1 2UA8 D5
*
3UA0

8
IUA1 3 LM833

2K2
IUA3 IUA4

2
3UA5
2
1 1 2UA9 D5 3UB7-3 D2

100n
FUA0

3
22R
2UB0 C7 3UB7-4 C2

2UA1
FUA1

3K3 1%
+2V5-REF

4
3UA3

2UA3
47K
1
3UA2 2UB1 D6 5UA0 E8

1n0
7UA0
TS2431 2UB2 D7 7U06-1 F2

2UA2
K

IUA9
2UB3 F6 7U06-2 F1

330p
R

2
2UB4 F6 7UA0 B2

3UA6
A

B B

1K0
3 FUA4
2UB5 F8 7UA1-1 A5
3UA7
+2V5 2UB6 F8 7UA1-2 C5
IUA2 1K0
2UB7 F7 7UA2 A6

22K

1u0

1u0
3UA8

2UA5

2UA6
CUA0 +2V5-LVDS
IUB6
+5V5-TUN +5V-TUN 2UB8 D2 7UA3 C6
3U12 C3 7UA4 E5
7UA6 3U13 C3 7UA5 E8
BC817-25W
3U15-1 C8 7UA6 C3
3U12

330R
1%
3UB6-2
2 7

+12V IUB3

C 3UB6-3
3
1K0 IUB2
6 6 +12V
+1V8
+3V3
∗ +3V3 C
3U15-2 C8
3U15-3 D8
7UA7-1 C3
1K0 +5V 1
3U15-1
8 +5V 1
3U16-1
8 7UA7-2 D2
3UB6-4
4 5
1K0
2 IU26 100R 100R 3U15-4 D8 7UC0 A8
3UB6-1 7UA3 3U15-2 3U16-2
3U16-1 C9

2UB0
IUB5
1 8 3 1 7UA7-1 PHD38N02LT 2 7 2 7 CUA0 B9

1u0
BC847BS(COL)
3U13

330R
1%

+2V5-REF 1K0 7UA1-2 100R 100R


3UB7-4 3U16-2 C9 FUA0 A2

8
4 5 5 IUA7 5 LM833 FUA2 3UB0 IUA5 3U15-3 3U16-3
7 3 6 3 6
470R
7UA7-2 4 IUB4 6 100R 100R
3U16-3 D9 FUA1 A7
BC847BS(COL) 22R
3U16-4 D9 FUA2 D5

4
3U15-4 3U16-4
470R

470R

100n

FUA3 4 5 4 5
3U25-1 E3
7

2UA7

+1V2 100R 100R FUA3 D7


3UB7-2

3UB7-3

3UB7-1
2UB8

2UA9
470R
22u

1n0
3U25-2 E3 FUA4 B9
D D

2UB1

2UB2
RES 1u0

1u0
3U25-3 E2 IU26 C3
2

2UA8

330p
IUA8
∗ NOT FOR 5000 SERIES 3U25-4 E2 IU29 E2
3U26-1 F3

3UA9
IU30 F3

1K0
ENABLE-1V8 3U26-2 F3 IUA1 A4
4
3U25-4
5 3U26-3 F3 IUA2 B5
3UB1 SENSE+1V2
100K RES RESERVED 3U26-4 F3 IUA3 A6
7
100K RES

IUA6 5UA0
3U25-2

1K0
3U25-3
3U29-1 E3 IUA4 A6
3 6
30R 3U29-2 E3 IUA5 C6
E E
2

100K RES 3U29-1 RES


1 8 +12V 7UA5
LDS3985M50
3U29-3 E3 IUA6 E5
470R
IU29 3U29-2 RES 3U29-4 F3 IUA7 C4
1

2 7 1 5
100K RES

+5V5-TUN +5V-TUN
3U25-1

IN OUT
3UA0 A2 IUA8 D5

3UB2

4K7
470R 7UA4 3 4
3 6 +3V3 3
3U29-3
6
RES TS431AILT INH BP IUB1
3UA1 A3 IUA9 B6
8

RES 5 3 COM
RES IU30 470R A K 3UA2 B3 IUB0 F6

2UB7

2UB5

2UB6
100n
7U06-2 5 7U06-1 2

1u0

1u0
3U29-4 RES
BC847BS(COL) BC847BS(COL) 4 5 2 1 3UA3 B4 IUB1 E8

2
NC NC
3UB3

4 1 470R REF 4K7

3U26-1 RES
3UA4 A4 IUB2 C2
1 8
3UA5 A6 IUB3 C3
4

470R
F 2
3U26-2
7
RES
3UB5 3UB4 IUB0 2UB3
F 3UA6 B5 IUB4 D3
470R +5V 3UA7 B6 IUB5 C2
100K 1K0 22n
+3V3 3
3U26-3
6
RES
2UB4
3UA8 B5 IUB6 B3
470R 3UA9 D5
3U26-4 RES 330p
4 5 RES 3UB0 D6
470R
3UB1 E6
3UB2 E6
1 2 3 4 5 6 7 8 9
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DC/DC

DC/DC
B03E B03E
1 2 3 4 5 6 7 8
2U27 B8
2U28 D8
2UD0 A2
2UD1 A2
2UD2 A3
2UD3 B3
A 5UD0 IUD0
A 2UD4 B5
+12V
30R +5V5-TUN 2UD5 B5
7UD0-1
2UD6 B6

2UD0

2UD1

2UD2
ST1S10PH

10u

10u

10u

6
A

SW
ENABLE-3V3-5V 2 7
IUD3 5UD1 IUD7
6UD0 FUD3 2UD7 B6
INH SW +5V
VIN
3u6 SS36 +1V1
2UD8 C2

RES 2UE9
5 3

220u 16V
RES 1n0
SYNC VFB 2UD9 C2

2UD3

2UD4

2UD5

2UD6

RES 2U27

100n
GND

22u

22u

22u
A P HS 2UE0 C3

9
6
2UE1 D5
7U05-1 2
2UE2 D6
B IUD6 2UD7
BC847BS(COL)
RES 1
IU27
B 2UE3 D6
7UD0-2 4n7 2UE4 D6

13

15

RES 3U06
ST1S10PH

10K
3UD2

3UD0

3UD1
2UE5 E4

68K

33K
1%

1%
10 VIA 12 120K
2UE6 E6
11
2UE7 F4

14
2UE8 F5
2UE9 B8
∗∗ 5UD3
3U06 B8
C +12V
IUD1
C 3U07 D8
30R
7UD1-1
3UD0 B5
2UD8

2UD9

2UE0

ST1S10PH 3UD1 B5
10u

10u

10u

6
A

SW
IUD4 5UD2 FUD2
ENABLE-3V3-5V 2
INH SW
7 +3V3 3UD2 B6
VIN
5 3
3u6 +1V1 3UD3 D5

220u 16V
SYNC VFB
3UD4 D5

2UE1

2UE2

2UE3

2UE4

RES 2U28
1% 100K

100n
GND

4n7

22u

22u
A P HS 3UD3
3UD5 D5
4

9
3 BC847BS(COL)

5 IU28
5UD0 A2
7U05-2
RES 5UD1 A5
D 7UD1-2
IUD2 4 D 5UD2 C5
13

15

5UD3 C2

RES 3U07
ST1S10PH

10K
3UD4

3UD5

33K
1M0

1%
10 VIA 12 6UD0 A6
11
6UD1 E4
7U05-1 B7
14

7U05-2 D7
7UD0-1 A4

7UD2
LD1117DT25 7UD0-2 B4
6UD1 IUD5 7UD1-1 C4
E +5V 3
IN OUT
2 +2V5 E 7UD1-2 D4
S1D COM (∗) FOR 5000 SERIES ONLY

22u 16V
7UD2 E5
2UE5

2UE6
100n

(∗∗) NOT FOR 5000 SERIES 7UD3 F5


1

FUD2 C5
FUD3 A7
7UD3 IU27 B8
LD1117DT33
IU28 D8
3 2
IN OUT +3V3 IUD0 A2
F COM F IUD1 C2
22u 16V
2UE7

2UE8
100n

IUD2 D5
1

IUD3 A5
IUD4 C5
IUD5 E4
IUD6 B6
IUD7 A5
1 2 3 4 5 6 7 8
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Temp Sensor + AmbiLight

Temp Sensor + AmbiLight


B03F B03F
1 2 3 4 5 6 7
1UM0 A4
5UM0 A3
5UM1 A3
FUM0 A5
IUM0 A4
5UM1 IUM0 1UM0 FUM0
+3V3 V-AMBI

A 30R
5UM0
T 1.0A 63V
A
+5V
RES 30R

B B

C C

D D

E E

1 2 3 4 5 6 7 DC/DC
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Fan Control

Fan-Control
B03G B03G
1 2 3 4 5 6 7 8 9
2US3 A7
+12V +12V
3US2 A3
+3V3 3US3 B3

8
3US4-1
3US4-1 A4

10K

7
+12V

3US5-2
3US2

2US3

100n
A A

10K
3US4-2 D4

10K

1
3 7US1-1
3US7 LM339P
9

2
FAN-CTRL1
1K0
8
14
IUS3 3US5-3
6 3
IUS6
3US4-3 C4
10K
IUT1 12
7US2
BC807-25W 3US4-4 C5
+12V

+3V3
IUS7
3US5-1 B6

3US9
3US5-2 A6

22R
8
3US5-1
+12V

10K
3US5-3 A5

3US3

10K
B 3 7US1-2
B

1
IUT2
11 LM339P
13
IUS4 3US5-4
5 4 BC807-25W
3US5-4 B5
FAN-CTRL2 10 7US3

12
10K IUS8
3US6 C6
IUS9
3US7 A4

3US6
3US9 B6

47R
FAN-DRV 7US1-1 A5
C
+3V3
C 7US1-2 B5
+12V 7US1-3 C5

5
IUS5

3US4-4
+12V
7US1-4 D5

10K
6
3US4-3

10K
7US1-3
7US2 A6

4
3
5 LM339P
2

3
TACH01 4
7US3 B6

12
+12V
9US0 D4
IUS0 D5
9US0

D D
RES

+12V
7

IUS3 A5
3US4-2

10K

7US1-4

3
7 LM339P
1
IUS4 B5
2

IUS0
TACH02 6

IUS5 C5
12

TACHO IUS6 A6
IUS7 B7
E E IUS8 B6
IUS9 B6
IUT1 A4
IUT2 B4

F F

1 2 3 4 5 6 7 8 9
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Vdisp Switch

VDisp-Switch
B03H B03H
1 2 3 4 5 6 7 2UU0 C6
2UU1 C4
3UU0-1 C4
1 9UU0-1 8
RES 3UU0-2 C4
2 9UU0-2 7
RES 3UU0-3 C2
3 9UU0-3 6
RES
4 9UU0-4 5
3UU1 C4
A RES
1 9UU1-1 8
A 3UU2 D6
RES
2 9UU1-2
3UU3-1 C4
7
RES
3 9UU1-3 6
3UU3-2 C5
RES
4 9UU1-4 5
FUU0 3UU3-3 C6
RES 3UU3-4 C7
7UU0 B4
7UU1 B5
7UU2-1 C3
B 7UU0
B 7UU2-2 C3
SI4835DDY
RES 7UU1 +VDISP-INT 7UU3 C6
+12VD SI3441BDV
9UU0-1 A4
8
3UU3-1
1
9UU0-2 A4
4
PUMD12
47K RES
IUU3
9UU0-3 A4
7UU2-2 3UU1 2UU1 3UU3-2
5
47R IUU2
2
47K RES
7
9UU0-4 A4
IUU1 1u0
3
C
IUU0
7
3UU0-2
2
7UU3 RES
BC847BW C 9UU1-1 A4

1
47K 9UU1-2 A4

3UU0-1
6

47K
3 IUU4 3UU3-3 IUU5 3UU3-4
1 6 3 4 5
3UU0-3
2 7UU2-1
+3V3
9UU1-3 A4

8
+3V3-STANDBY 47K RES 47K RES
6 3 PUMD12
47K 2
9UU1-4 A4

2UU0

100n
1

FUU0 A5
IUU6
VDISP-SWITCH IUU0 C3
3UU2

4K7 RES
+3V3 IUU1 C4
D D IUU2 C5
LCD-PWR-ONn IUU3 C6
IUU4 C6
IUU5 C7
IUU6 D6

E E

1 2 3 4 5 6 7
4 2009-10-22

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10-14 B04 820400089524 Analog I/O


Analogue Externals A

Analogue Externals A
B04A B04A
1 2 3 4 5 6 7 8 9 10 11 12 13 1E00 A4
1E01-1 D5
3E78 F2
3E79 F2
IE22 B2
IE23 C2
1E01-2 H5 3E80 C10 IE48 G2
1E02 C13 3E82 D10 IE51 G10
1E12 D4 3E83 E10 IE52 H2
1E18 F4 3E84 E10 IE53 D1
1E19 F4 3E85 F10 IE54 E1
1E22 H4 3E86 F10 IE55 F1
RESET-AVPIP 1E23 I4 3EA1 D6 IE56 E9
1E24 I11 3EA2 D6 IE57 F9
3E63-1 FE60
AP-SCART-OUT-R 1E25 I4 3EA7-1 A7 IE59 E8
FE70 IEC0 IE67 1 8 1E26 G11 3EA7-2 H13 IE60 E6
3E37-4 3EA7-1 2EA4 100R
AP-SCART-OUT-R AUDIO-OUT-L

CDS4C12GTA
1E27 H11 3EA7-3 H13 IE61 E6
A 4 100R 5 8 470R 1 1u0 16V A 1E31 B4 3EA7-4 B7 IE62 H10

2E29

RES 6E10

1E45

2E50
100p

100p
12V
CDS4C12GTA
FEA0
7E01-1 6 AP-SCART-OUT-L 1E45 A11 3EB1 E6 IE67 A8

2E01

RES 6E01

1E00

2E87
100p

100p
1E46 B11 3EB3 E6 IE68 B8

12V
IEC1
2
1E47 C11 3EB6-1 G6 IE70 E7
1 1E48 C11 3EB6-2 H13 IE89 D7
PUMH7
IE20 FE61
1E49 D11 3EB6-3 H13 IE90 D7
AUDIO-IN2-R 3E11-1
1E52 F11 3EB6-4 G6 IE91 G6
IEC2 2EA5 IE68 1 8
3EA7-4 1K0 1E53 C4 3EB9-1 H6 IE92 G7
AUDIO-OUT-R

CDS4C12GTA
IE22 FE71
AUDIO-IN1-R
3E07-4
5 470R 4 1E54 D4 3EB9-2 I13 IE93 H7
1u0 16V
1E55 E4 3EB9-3 I13 IE94 H6

2E30

RES 6E08

1E46

2E51
100p

100p
12V
4 1K0 5 FEA1
7E01-2 3

CDS4C12GTA
AP-SCART-OUT-R 1E56 E11 3EB9-4 I6 IE96 G6
B FEC8 B 1E57 E11 5E73 D2 IEC0 A7
2E06

RES 6E03

1E31

2E88
100p

100p
12V
5
1EP2 F13 5E74 E2 IEC1 A6
+3V3
4
FE62
2E01 A3 5E76 F2 IEC2 B7
PUMH7 AP-SCART-OUT-L 3E63-4
2E04 D3 5E77 D10
4 5
100R 2E06 B3 5E78 E10

CDS4C12GTA
2E10 C3 5E79 F10

3E25

10K
3E37-1 FE72

2E32

RES 6E12

1E47

2E70
100p

100p
AP-SCART-OUT-L 2E12 F4 5E80 E8

12V
1 100R 8 2E13 G11 6E01 A3
3E24
A-PLOP
CDS4C12GTA
2E14 F4 6E02 E11
2K2
2E15 D4 6E03 B3
RES 6E07
2E10

1E53

2E90
100p

100p
12V

AUDIO-IN2-L SCART2 2E16 D12 6E07 C3


C IE21
4
3E11-4
5 (AV2)
C 2E17 E12 6E08 B11
1K0 2E18 E4 6E09 D3

CDS4C12GTA
1E02 2E19 F12 6E10 A11
IE23 3E07-1 * EU

2E31

RES 6E14

1E48

2E82
100p

100p
AUDIO-IN1-L 2E24 G2 6E12 C11

12V
1 1
1K0 8 2E29 A10 6E14 C11
CDS4C12GTA

+5V 3E80 18R 2 2E30 B10 6E22 E3


AP 2E31 C10 6E23 D3
2E04

RES 6E09

1E54

2E91
100p

100p
12V

YPBPR1-PB 9E50 9E51 3 2E32 C10 6E24 D11


FE55 5E77 BEC0 3E82
AV4-PB 2E33 E12 6E26 F3
3E74 18R

3EA2
SCART1 4

1R0

CDS4C12GTA
1u8 18R 2E41 H12 6E28 F3

2E89

2E92
150p

150p

RES 6E24

1E49

2E16
2E44 I4 6E29 H3

100p
(AV1) 5

12V
IE53 5E73 IE90
D AV1-B
1u8
BEC3 3E75

1E01-1 6
D 2E50 A12 6E30 I3
CDS4C12GTA

18R 2E51 B12 6E31 I11


RES FE68
2E70 C12 6E32 I3

2EB1

3EA1
2E79

2E80

RES 6E23

1E12

2E15

9E01

9E02
150p

150p

100p

100n
1 7

1K0
12V

* EU 2E73 H7 6E34 E11


AV2-STATUS FE63
2 8 2E74 F7 6E35 F11
IE89 IE05

CDS4C12GTA
RES 3
IE13 3E16 12K FE64
9
2E75 H4 6E36 G11
2E76 I4 6E37 H11

3E18 2

RES 6E02
3E17

1E56

2E33

100p
4K7
YPBPR2-SYNCIN2

12V
IE61

2EB3
4 4 10 2E77 G12 7E01-1 A6

39K
2E99

1u0
* EU 7E06-2 12
IE18 3E31 3E83 18R FE66 11 2E78 I12 7E01-2 B6
AV1-STATUS 5 5 11
5p6 10 2E79 D1 7E04 H6

1
6 7E06-1
CDS4C12GTA

12K FE73 9
6 3 BC847BPN(COL) IE70 5E80 5E78 12 2E80 D2 7E05 G6
2E81 IE59 CVBS-MON-OUT1 IE56 BEC1 8
E AP AV4-Y 3E84
E
3E32

RES 6E22

1E55

2E18

100p

2 2E81 E7 7E06-1 E7
4K7

12V

FE74 7
YPBPR1-SYNCIN1 9E52 9E53 7 IE60 13

CDS4C12GTA
2u2 10u 1u8 18R 6 2E82 C12 7E06-2 E6

2
1 3EB1 2

2E97

2E98

150p
2E94
1

39p

18p
3E76 18R FE75 5 2E83 F1 7E09-1 H2

RES 6E34
3E19

2E93

1E57

2E17
150p

100p
8 BC847BPN(COL) 14

18K

12V
820R 4
2E84 F2 7E09-2 G10

1 3EB3 2
FE67 3

330R
9 15 2E85 F1 9E01 D6
IE54 5E74 BEC4 3E77 FE80 2

1
AV1-G IE08 RES 1 2E86 F2 9E02 D7
9E08 10 16
CDS4C12GTA

1u8 18R 2E87 A4 9E05 F4


2E83

2E84
150p

150p

3E85 18R 1EP2


2E88 B4 9E06 G4
6E26

1E18

2E14

100p

11 17
12V

CDS4C12GTA
IE14 IE57 5E79 BEC2 3E86 2E89 D9 9E07 F4

RES 6E35

1E52

2E19

100p
9E07 12 AV4-PR 18

12V
2E90 C4 9E08 F4
RES

AP RES 1u8 18R 2E91 D4 9E09 G4

150p
YPBPR1-PR 9E10 13 19

2E96
F F

2E95
2E92 D10 9E10 F4

150p
9E54 9E55 IE16 +5V
3E78 18R 9E05 14 20 2E93 E10 9E50 D1
IE55 5E76 BEC5 3E79 FE81 2E94 E9 9E51 D2
AV1-R 15 RES +3V3
21
2E95 F10 9E52 E1
CDS4C12GTA

1u8 18R FE82 FE79


2E85

2E86

2E74
150p

150p

100n

16 2E96 F9 9E53 E2
RES 6E28

1E19

2E12

100p
12V

MTJ-505H-01 NI LF 2E97 E8 9E54 F1


9E09 17

100n 16V
2E98 E8 9E55 F2

3E73

2E13
4K7
IE17 IE96 IE91
RES 9E06 18 1 3EB6-1 8 2E99 E8 BEC0 D10
FE83 470R 2EA4 A7 BEC1 E10
19
7E05
IE92 3E45 IE51 2EA5 B7 BEC2 F10
CVBS-OUT-SC1 AV2-BLK 3
+3V3 FE84 BC847BW 2EB1 D6 BEC3 D2
* EU 20 68R
G G 2EB3 E7 BEC4 E2
4 3EB6-4 5

7E09-2 5
470R

21 PUMH7 3E07-1 C3 BEC5 F2

CDS4C12GTA
FE76
3E44

2E24

100n

4
4K7

3E07-2 H13 FE55 D9

3E61

RES 6E36

1E26

RES 2E77

100p
75R

12V
FE85
3E07-3 H13 FE60 A12
MRC-021V-29 PC RES 3E07-4 B3 FE61 B12
3E48 3E37-2
IE48 3E11-1 B11 FE62 B12
AV1-BLK 6 2 100R 7
1E01-2 68R 3E11-2 I13 FE63 D12
7E09-1 2 MT 3E37-3 3E11-3 I13 FE64 D12
+5V
PUMH7 23 22 3 6 3E11-4 C11 FE66 E12
CDS4C12GTA

IE62 3E39 FE78 100R


1 AV2-CVBS 3E16 D11 FE67 E12
3E07-2
RES 6E29
3E43

1E22

RES 2E75

100p

MRC-021V-29 PC
75R

12V

CDS4C12GTA
27R 3E17 E10 FE68 D12
2 1K0 7
H H 3E18 E7 FE70 A5

RES 6E37

1E27

2E41
100n

100p
12V
2E73 3E07-3
3E19 E7 FE71 B4
3EB9-1 IE94 3 1K0 6 3E24 C7 FE72 C4
IE52 1 8
3E62 3EA7-2 2 3EB6-2 7 3E25 C13 FE73 E4
AV1-CVBS 470R
7E04 IE93 2 470R 7 3E31 E3 FE74 E4
CDS4C12GTA

27R 3E52 FE77 470R


BC847BW
3EA7-3 3EB6-3
3E32 E3 FE75 E4
4 3EB9-4 5
RES 6E32

1E25

2E44

100p

3 6

CDS4C12GTA
3E37-1 C3 FE76 G12
12V

68R
470R

3 470R 6 470R 3E37-2 G13 FE77 H12

RES 6E31

1E24

RES 2E78

100p
12V
3E63-2 2 3EB9-2 7 3E37-3 H13 FE78 H12
2 7 3E37-4 A3 FE79 F13
100R 470R
3E63-3 3E39 H10 FE80 E4
CVBS-OUT-SC1 3 3EB9-3 6
I RES 3 6
I 3E43 H2 FE81 F4
CDS4C12GTA

3E49 100R 470R


3E44 G2 FE82 F4
3E11-2
RES 6E30

1E23

RES 2E76

100p

3E45 G7 FE83 G4
12V

68R
2 7
1K0 3E48 G7 FE84 G4
3E11-3 3E49 I7 FE85 G5
3 1K0 6 3E52 H7 FEA0 A7
3E61 G11 FEA1 B7
3E62 H2 FEC8 B13
3E63-1 A11 IE05 D10
3E63-2 I13 IE08 E5
3E63-3 I13 IE13 D6
3E63-4 B11 IE14 F5
3E73 G10 IE16 F5
1 2 3 4 5 6 7 8 9 10 11 12 13 3E74 D2 IE17 G5
3E75 D2 IE18 E3
1X02
REF EMC HOLE 3E76 E2 IE20 B10
3E77 E2 IE21 C10

4 2009-10-22

CLASS D
8204 000 8952

18770_528_100118.eps
100218

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 132

Analogue Externals B

Analogue Externals B
B04B B04B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1E03 B3
1E04 C3
1E07 A12
1E08-1 B3
1E08-2 E3
1E08-3 D3
1E09 F3
1E28 B4
A A 1E29 D4
1E37 F4
SPDIF out 1E38 G4
YPBPR 1E39 C4
1E07 1E42 E4
IE15 5E06
YKC21-5598 FE54 EU 9E29
IE71 3E87 IE72
AV3-Y SPDIF-OUT
FE59 CON_JACK 1E43 B4
2 1 1E44 B10

CDS4C12GTA
1E08-1 18R 30R

CDS4C12GTA
YPBPR1-SYNCIN1
1E75 H5

2E27

1E43

RES 6E40

2E22

1E44

RES 6E46
100p
1 2 YKB11-0946V

12V

12V
10p
YELLOW
AP 9E04 3E88 IE73
AV2-CVBS
FE41 1E76 I5
B 27R B 1ECB I4
2E20 H4
FE51 EU IE74 3E89 IE75
MTJ-032-21B-41 NI FE 9E57 AV3-PB 2E21 I4
2

CDS4C12GTA
1E03 18R
YPBPR1-PB 2E22 B9

2E67

RES 6E51
100p

1E28
1 2E27 B4

12V
2E35 F6
2E36 F4
FE48 2E37 G4
MTJ-032-21B-41 NI FE EU 9E58 IE76 3E90 IE77
AV3-PR
2
2E38 G6
C 1E04 18R
C

CDS4C12GTA
YPBPR1-PR 2E39 D4

2E68

RES 6E52
100p

1E39
1
2E40 E4

12V
FE42 2E67 B4
2E68 C4
2E71 E5
2E72 D5
YPBPR AUDIO 3E14 H6
3E15 H6
YKC21-5598 3E97
AUDIO-IN3-R
3E20 G5
D 6 D 3E21 F5
CDS4C12GTA
1E08-3 FE50 1K0 IE31
3E87 B6
2E39

1E29

RES 6E06

2E72
5
100p

100p
RED 12V
3E88 B6
FE43
3E89 B6
3E90 C6
FE49 3E96 IE29
YKC21-5598 AUDIO-IN3-L 3E96 E5
4
CDS4C12GTA

1E08-2 1K0 3E97 D5


5E06 B9
2E40

1E42

2E71
3
100p

100p
RES 6E38

12V

WHITE
6E06 D5
E E 6E15 H5
6E16 I5
6E19 F5
6E20 G5
VGA ( OR DVI ) AUDIO 6E38 E5
6E40 B5
5
4 IE09
6E46 B11
1E09 FE02 3E21
2 AUDIO-IN4-L 6E51 B4
CDS4C12GTA

1K0 6E52 C4
3
F F
V_NOM
2E36

1E37

6E19

2E35

100p

7 9E04 B5
12V
1n0

MSJ-035-10A B AG PPO 8
1 9E29 B5
9E57 B5
FE01
9E58 C5
BE20 H6
FE03 3E20 IE10 BE21 H6
AUDIO-IN4-R
BE22 I4
CDS4C12GTA

1K0
FE01 F4
V_NOM
2E37

1E38

6E20

2E38

100p
12V
1n0

FE02 F5
G G FE03 G5
FE41 B12
FE42 C4
FE43 D4
FE44 H5
SVHS IN FE45 H5
FE44 BE20 3E14 FE46 I4
C-SVHS
FE48 C4
CDS4C12GTA

18R
FE49 E4
2E20

1E75
100p

RES 6E15

12V
6

H H FE50 D4
2 FE51 B4
4 FE54 B4
FE45 BE21 3E15
Y-SVHS FE59 B10
3
CDS4C12GTA

27R IE09 F6
2E21

1E76
100p

RES 6E16

1 IE10 G6
12V

MDC-066H-A LF
FE46
1ECB
BE22
IE15 B9
IE29 E6
IE31 D6
I I IE71 B6
IE72 B7
IE73 B7
IE74 B6
IE75 B7
IE76 C6
IE77 C7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 2009-10-22

ANALOG I/O
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2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 133

Ethernet + Service

Ethernet + Service
B04C B04C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1E06 A13
1E70 B3
1E85 A11
1E86 A11
5E08 IE07 1N00 G7
+3V3 +3V3-ET-ANA 2E48 B5
30R
IE49 3E53-1 FE56 2E49 B5
2 3E53-2 7

2E62

2E63

2E66
8 1

100n

100n
TXD1-MIPS
A A 2E52 B3

10u
47R 47R 1E06
IE50 3E53-3 FE57 UART 2E53 B4
RXD1-MIPS 4 3E53-4 5 6 3 2
3 SERVICE 2E54 B3

BZX384-C5V1
+3V3-ET-ANA +3V3 47R 47R 1 CONNECTOR 2E55 B3

BZX384-C5V1
YKB21-5157V

6E43

6E44

1E85

1E86
FE58 2E56 H2
IE32 IE38 IE06 2E57 H2
3E30 IE33 2E58 H3
2E59 H4

2E52

2E53

2E48
100n

100n

2E49

10u
4n7
1M0
1E70
+3V3 2E60 H5
B NX3225GA
B 2E62 A3
25M 2E63 A3
3E66 RES

3E67 RES

2E54
10p

10p
7E10-1
2E66 A3

27

12
LAN8710A-EZK

1
2E55 3E22-1 F2
3E33

CR 1A 2A IO
10K

10K

10K

VDD
5
CLKIN 3E22-2 F3
1
4 XTAL 31
2
RX
P
30
ETH-RXP 3E22-3 F2
N ETH-RXN
IE26
RESET-ETHERNETn 19
RST
3E22-4 F2
29 ETH-TXP
ETH-RXD(0) 11 TX
P
28 ETH-TXN
3E26 F5
0 N
ETH-RXD(1) 10 MODE 3E30 B3
C ETH-RXD(2) 9
8
1
RMIISEL TXCLK
20 ETH-TXCLK C 3E33 B2
ETH-RXD(3) PHYAD2
3E69 10K 26
3E70 RES
RXD<0:3> RXDV ETH-RXDV 3E34 D6
IE63
ETH-COL RES 10K 15
COL RXER
13 ETH-RXER 3E35 D6
9E43 3E71 10K 3E64 10K
RES
CRS_DV RXD4 +3V3 3E40 D5
MODE2 0 IE64 RES
21
PHYAD
1
7
3E65 10K
ETH-RXCLK 3E51 E1
ETH-TXEN TXEN RXCLK +3V3
RES
3E53-1 A10
ETH-TXD(0) 22 3 ETH-REGOFF
ETH-TXD(1) 23
0 REGOFF
10K 3E34 3E68 10K 3E53-2 A9
1 1 +3V3
ETH-TXD(2) 24
2 TXD
LED
2
2 RES ETH-INTSEL 3E53-3 A10
ETH-TXD(3) 25 10K 3E72 3E35 10K
D ETH-TXER 18
3
4
INTSEL
14 9E42
RES
+3V3
D 3E53-4 A9
INT CRS ETH-CRS 3E64 C6
TXER
RBIAS
32 3E65 D6
ETH-MDC 17 IE39 3E66 B2

1%
MDC

3E40

12K1
ETH-MDIO 16
MDIO
3E67 B2
3E51 1K5 +3V3 VSS
3E68 D6
33

3E69 C2
7E10-2
LAN8710A-EZK 3E70 C1
34 VIA 36
35 37 3E71 C3
E E 3E72 D6
3E95-1 F3
3E95-2 F3
3E95-3 F4
3E95-4 F4
3E98 F5
5E08 A3
+3V3-ET-ANA
6E43 A9
6E44 A10
F F 6E47 G2
6E48 G3
8 100R 1

7 100R 2

6 100R 3

5 100R 4
3 100R 6

4 100R 5

1 100R 8

2 100R 7

3E95-1

3E95-2

3E95-3
3E22-2
3E22-3

3E22-4

RES 3E22-1

3E95-4

6E49 G4
3E26

3E98
22R

22R

CONFIGURATION RESISTOR SETTINGS 6E50 G5


6E47

6E48

6E49

6E50
RES

RES

RES

7E10-1 B4
NUP1301ML3

NUP1301ML3

NUP1301ML3

NUP1301ML3

7E10-2 E4
9E42 D5
Resistor POP EMPTY
ETHERNET CONNECTOR 9E43 C3
G G BE00 G6
1N00
BE01 G6
ETH-TXP FE27 BE00 1 3E64 (RES) PHYADD(0) = 1 PHYADD(0) = 0 BE02 G6
ETH-TXN FE28 BE01
ETH-RXP FE29 BE02
2 BE03 H6
3
FE30
4 3E65 (RES) PHYADD(1) = 1 PHYADD(1) = 0 FE27 G6
ETH-RXN FE31 BE03
5
6
FE28 G6
7 3E66 (RES) PHYADD(2) = 1 PHYADD(2) = 0 FE29 G6
8
FE30 G6
RES 2E56

RES 2E57

2E58

2E59

2E60

3E67 (RES)
15p

15p

15p

15p

22n

1551151-1
RMII mode selected MII mode selected FE31 H6
H H FE32 I5
RES
RES

FE34
3E68 (RES) Internal 1.2V reg. disabled Internal 1.2V reg. enabled FE33 I5
FE34 H6
3E69 (RES) MODE(0) = 0 MODE(0) = 1
FE56 A11
3E70 (RES) MODE(1) = 0 MODE(1) = 1 FE57 A11
FE58 A11
3E71 (RES) MODE(2) = 0 MODE(2) = 1 IE06 B4
FE32 IE07 A3
INTERRUPT FUNCTION INTERRUPT FUNCTION IE26 C2
I ETH-INTSEL
3E72 I IE32 B3
DISABLED ON ENABLED ON
ETH-REGOFF IE33 B3
FE33 nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL
IE38 B4
IE39 D5
IE49 A10
IE50 A9
IE63 C6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 IE64 C6

4 2009-10-22

ANALOG I/O
8204 000 8952

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100118

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 134

HDMI

HDMI
B04D B04D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1P02 E2 5EC0 A8
1P03 C2 5EC2 F7
I2C Address 1P04 A2 5EC3 A11
5EC0 FEC0 FEC3 MICOM-VCC33 2EC0 A9 6EC1 H3
30R
SII9187A = 0xB2 2EC1 A8 7E02 G3
HDMI CONNECTOR 3 +3V3

3ECH
2ECV
2EC0

2EC2
RES 2EC1

100n

10K
10u

1u0
220u 16V
1P04 2EC2 A10 7EC0 G3
A 1
2
ARX2+
FECB
A 2EC3 B10 7EC1 B9
ARX2-
3
4 ARX1+ 2EC6 B9 9EC0 G4
RES
5
6 ARX1- AIN-5V FEC7 5EC3 +3V3 2EC7 B9 9EC2 C11
ARX0+ +3V3-HDMI
7
8 30R 2EC8 B9 9EC3 E11

RES 2ECW
2EC6

2EC7

2EC8

2EC3
100n

100n

100n

100n
10u
ARX0-
9
10 ARXC+ 2ECC G8 FEC0 A9

3 3EC1-3 6
11
ARXC- 2ECM B8 FEC1 B2

47K
12
13 PCEC-HDMI
14 7EC1 2ECN D8 FEC2 B2

27
64

37

38
B FEC1 ARX-DDC-SCL ARX-DDC-SCL SII9287B
B

9
15
2ECP E8 FEC3 A10

MICOM_VCC33

SBVCC33
16 FEC2 ARX-DDC-SDA ARX-DDC-SDA VCC33
17 ARX-HOTPLUG +5V-EDID
FEC4
2ECQ F8 FEC4 B2

8 3EC1-1 1
AIN-5V 1 8 31
18 3ECM-4 IE42 (CBUS) HPD0

6
19 FEC5 ARX-HOTPLUG 4 5 3ECN-1 100K 32

47K
AIN-5V R0PWR5V
FEC6 21 2ECU I3 FEC5 B2

10K

10K
20 10R
ARX-DDC-SDA 1u0 2ECM 29 3ECP-1 3ECP-3
23 22 DSDA0
ARX-DDC-SCL 30 49 2ECV A9 FEC6 B2

3
DSCL0 R4PWR5V

ARXC-
ARXC+
65
66
N
R0XC
DSCL4
48
47
VGA-SCL-EDID-HDMI 2ECW B10 FEC7 A10
AIN-5V P DSDA4 VGA-SDA-EDID-HDMI
1P03
HDMI CONNECTOR 2
ARX0- 67 51 9EC2 CEC-HDMI
3E23 F4 FECA F3
N CEC_D
1 BRX2+ ARX0+ 68
P
R0X0 RES 3EC1-1 B4 FECB A10
C 2
3 BRX2- ARX1- 69
N
C 3EC1-3 B4 FECC D2
BRX1+ ARX1+ 70 R0X1
4 P
5
BRX1- ARX2- 71
3EC3 E10 FECD D2
6 BIN-5V N
7 BRX0+
BRX-HOTPLUG
ARX2+ 72
P
R0X2
57 HDMIA-RX2-
3EC5 E10 FECE D2
8 N
9 BRX0-
BRXC+ 3 3ECM-3 6
2
3ECN-2
7
100K
IE43
35
36
(CBUS) HPD1
TX2
P
56 HDMIA-RX2+
3ECA-1 D4 FECF D2
10 BIN-5V R1PWR5V

7 3ECA-2 2
11
BRXC- BRX-DDC-SDA
10R
1u0 2ECN 33 TX1
N
59
58
HDMIA-RX1-
HDMIA-RX1+
3ECA-2 D4 FECG D2
12 47K DSDA1 P
13 PCEC-HDMI BRX-DDC-SCL 34
DSCL1
61 HDMIA-RX0-
3ECA-3 F4 FECJ F2
14 N
15
FECC BRX-DDC-SCL BRX-DDC-SCL BRXC- 1
N
TX0
P
60 HDMIA-RX0+
3ECA-4 F4 FECK F2
D 16 FECD BRX-DDC-SDA BRX-DDC-SDA BRXC+ 2
P
R1XC
63
D
17 N HDMIA-RXC-
3ECD G3 FECL F2
1 3ECA-1 8

FECE BRX0- 3 TXC 62 HDMIA-RXC+


18 BIN-5V N P
FECF 4 R1X0
19 BRX-HOTPLUG BRX0+ P 3ECE H3 FECM F2
47K

FECG 21 3ECJ RES RES


20 MICOM-VCC33
5 55 4K7 3ECK
23 22 BRX1-
BRX1+ 6
N
P
R1X1
TPWR_CI2CA
IE12 4K7
3ECF I3 FECN F2
BRX2- 7
N CEC_A
50
FECR
9EC3 PCEC-HDMI 3ECG I3 FECP F2
8 R1X2 RES
BIN-5V
CRX-HOTPLUG
BRX2+ P
FECY 3ECL RES
3ECH A10 FECR E10
3 6 41 52
HDMI CONNECTOR 1 CIN-5V
2 3ECM-2 7 3ECN-3 100K
IE44
42
(CBUS) HPD2
R2PWR5V
INT
4K7
+3V3
3ECJ D10 FECW H9
1P02
E 1 CRX2+ CRX-DDC-SDA
10R
1u0 2ECP 39
DSDA2 E 3ECK D11 FECY E10
CRX-DDC-SCL 40
2
3 CRX2-
DSCL2 3ECL E11 FECZ I3
CRX1+ CRXC- 11
4
5 CRXC+ 12
N
P
R2XC
CSCL
54 SCL-SSB 3ECM-1 F8 IE11 I3
CRX1- 53 3EC3 100R SDA-SSB
6
7 CRX0+
CIN-5V
CRX0- 13
N
CSDA
3EC5 100R 3ECM-2 E8 IE12 D10
CRX0+ 14 R2X0
8
9 CRX0-
P
10 3ECM-3 D8 IE42 B8
CRXC+ CRX1- 15 RSVDL 28
10 N
3ECM-4 B8 IE43 D8
5 3ECA-4 4

CRX1+ 16 R2X1
11 P
CRXC-
12
3ECN-1 B8 IE44 E8
47K

FECJ PCEC-HDMI CRX2- 17


13 N
FECA ARC-eHDMI+ CRX2+ 18 R2X2
F
14
15
FECK CRX-DDC-SCL CRX-DDC-SCL DRX-HOTPLUG
P
F 3ECN-2 D8 IE45 F8
FECL CRX-DDC-SDA CRX-DDC-SDA 4 5 45
16
17 DIN-5V
1 3ECM-1 8 3ECN-4 100K IE45 46
(CBUS) HPD3
R3PWR5V
74 3ECN-3 E8 IE65 I7
3 3ECA-3 6

FECM CIN-5V 10R 75


18
FECP19 FECN CRX-HOTPLUG DRX-DDC-SDA 1u0 2ECQ 43
DSDA3
76 3ECN-4 F8 IE66 I7
47K

21 20 DRX-DDC-SCL 44 77
23 22
3E23 +3V3-STANDBY 5EC2
DSCL3
78 3ECP-1 B10 IEC4 G3
eHDMI+ DRXC- 19 79
N
RES 22K 30R DRXC+ 20
P
R3XC 80
81
3ECP-3 B10 IEC5 G3
7E02 RES
BC847BW
CIN-5V ARC-eHDMI+ DRX0- 21
22
N
R3X0
VIA 82
83
3ECU-2 I8 IEC6 G4
DRX0+ P
84 3ECU-4 I8 IEC7 H3
2ECC
23 85

10p
DRX1- N
G 7EC0
BC847BW IEC6
DRX1+ 24
P
R3X1 86
87
G
3ECD 9EC0 25 88
PCEC-HDMI CEC-HDMI DRX2- N
IEC4 DRX2+ 26 R3X2 89
100R IEC5 P

EPAD

73
IEC7

FECW 7EC1 3ECN 3ECF


3ECE

22K

+3V3-STANDBY
NON-INSTAPORT 9187A 4X 3K3 3K3
H H
INSTAPORT 9287B 4X 100K 100K
6EC1
+5V +5V-VGA

BAT54

IE11

IE65 +3V3
2 3ECU-2 7
3ECG

4R7

DDCA-SDA
10K
IE66 4 3ECU-4 5
I 3ECF FECZ 2ECU DDCA-SCL
10K
I
100K 1u0

+5V-EDID

1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 2009-10-22

HDMI
8204 000 8952

18770_531_100118.eps
100118

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 135

Headphone

Headphone
B04E B04E
1 2 3 4 5 6 7 8 9
2EE0 C5
2EE1 D5
2EE2 E4
+3V3-STANDBY 2EE3 E2
A A 2EE4 E3
2EE5 D5
4 2EE6 E6
5
PUMD12
7EE0-2 2EE7 E6
A-PLOP
3 3EE0-1 E3
3EE0-3 F3
B B 3EE0-4 E3
6 A-STBY
3EE1-1 C5
RESET-AUDIO
FEE0
2 7EE0-1 3EE1-2 D8
PUMD12
1 3EE1-3 D8
3EE1-4 D5
3EE2-1 D7
3EE2-2 E7
C C
2EE0
3EE2-3 E7
47p
3EE2-4 E7
1
3EE1-1
8 7EE0-1 B5

6
22K

3EE1-2

3EE1-3
7EE0-2 B6

22K

22K
3EE1-4
4 5
7EE1 D4

3
22K
2EE5 FE35 E7
D 47p +3V3 D FE36 E7
FEE0 B4
IEE0 E2

2EE1

100n
7EE1
TPA6111A2DGN 3EE2-1
8
1 8 IEE1 E2
Φ VDD 33R

ADAC(3)
IEE0 2EE3 IEE1
8
3EE0-1
1
IEE3
2 AMPLIFIER 1
2EE6 IEE7
2
3EE2-2
7
FE36
AMP1
IEE2 E2
1 1

ADAC(4)
IEE2 1u0 2EE4 10K
5
3EE0-4
4 6
2
IN-
VO
4V 100u 33R IEE3 E3
E 1u0 10K IEE4
5
SHUTDOWN 2
7
2EE7 IEE8
3
3EE2-3
6
FE35
AMP2
E IEE4 E3
2EE2 IEE6
3
BYPASS
VIA
10
11
4V 100u
4
33R
3EE2-4
5
IEE5 F3
1u0
GND GND_HS 33R IEE6 E4
4

IEE7 E6
3EE0-3
A-PLOP 3
10K
6
IEE5
IEE8 E6

F F

1 2 3 4 5 6 7 8 9
4 2009-10-22

AUDIO
8204 000 8952

18770_532_100119.eps
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2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 136

10-15 B05 820400089832 DDR


DDR

DDR
B05A B05A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2B10 C5
2B11 C11
2B12 C5
2B13 C11
2B14 C2
2B15 C2
2B16 C2
A A 2B17 C2
2B18 C3
2B19 C3
2B20 C3
2B21 C3
2B31 C8
2B32 C8
2B33 C8
B B 2B34 C9
2B35 C9
2B36 C9
+1V8 +1V8 2B37 C9
2B38 C9
2B48 F6

2B10

RES 2B11
2B12

2B13
47u

1u0

47u

1u0
2B49 F12

RES
2B50 F6
C C 2B51 F12
2B52 F3
2B53 F10
2B14

2B15

2B16

2B17

2B18

2B19

2B20

2B21

2B31

2B32

2B33

2B34

2B35

2B36

2B37

2B38
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
2B54 F3
7B00 7B02
2B55 F10
M9

M9
G1
G3
G7
G9

G1
G3
G7
G9
R1

C1
C3
C7
C9

R1

C1
C3
C7
C9
A1
E1

A9

E9

A1
E1

A9

E9
J9

J1

J9

J1
EDE1116AGBG-1J-F EDE1116AGBG-1J-F
3B10 D13

VDDL

VDDL
VDD VDDQ VDD VDDQ
DDR2-ODT K9 DDR2-ODT K9
ODT ODT
DDR2-CKE K2
CKE
A2 DDR2-CKE K2
CKE Φ A2 3B11 D6
DDR2-WE K3 E2 DDR2-WE K3 E2
DDR2-CS L8
WE
CS Φ NC
R3 DDR2-A14 DDR2-CS L8
WE
CS
SDRAM NC
R3 DDR2-A14 3B12 D12
D DDR2-RAS
DDR2-CAS
K7
L7
RAS
CAS
SDRAM R7
R8 DDR2-A13
DDR2-RAS
DDR2-CAS
K7
L7
RAS
CAS
R7
R8 DDR2-A13
D 3B13 D7
3B14 D13
DDR2-BA0 L2 DDR2-BA0 L2
0 0
DDR2-BA1 L3
1 BA 0
G8
3B53
DDR2-D0 DDR2-BA1 L3
1 BA 0
G8
3B10
DDR2-D16 3B15 E6
DDR2-BA2 L1 G2 3B11 33R DDR2-D1 DDR2-BA2 L1 G2 3B12 33R DDR2-D17
2 1
H7 33R 3B13 DDR2-D3
2 1
H7 33R 3B14 DDR2-D18
3B16 E12
2 2
DDR2-A0 M8
M3
0 3
H3
H1
3B15
33R
33R
3B17
DDR2-D2 DDR2-A0 M8
M3
0 3
H3
H1
3B16
33R
33R
3B18
DDR2-D19 3B17 E7
DDR2-A1 1 4 DDR2-D4 DDR2-A1 1 4 DDR2-D20
DDR2-A2 M7
2 5
H9 3B19 33R DDR2-D5 DDR2-A2 M7
2 5
H9 3B20 33R DDR2-D21 3B18 E13
DDR2-A3 N2 F1 33R 3B21 DDR2-D6 DDR2-A3 N2 F1 33R 3B22 DDR2-D22
DDR2-A4 N8
3
4
6
7
F9 3B23 33R DDR2-D7 DDR2-A4 N8
3
4
6
7
F9 3B24 33R DDR2-D23 3B19 E6
N3 DQ C8 33R 3B25 N3 DQ C8 33R 3B26
DDR2-A5
DDR2-A6 N7
5 8
C2 3B27 33R
DDR2-D8
DDR2-D9
DDR2-A5
DDR2-A6 N7
5 8
C2 3B28 33R
DDR2-D24
DDR2-D25
3B20 E12
6 A 9 6 A 9
E DDR2-A7
DDR2-A8
P2
P8
7
8
10
11
D7
D3 3B31
33R 3B29
33R
DDR2-D10
DDR2-D11
DDR2-A7
DDR2-A8
P2
P8
7
8
10
11
D7
D3 3B32
33R 3B30
33R
DDR2-D26
DDR2-D27
E 3B21 E7
DDR2-A9 P3
9 12
D1 33R 3B33 DDR2-D12 DDR2-A9 P3
9 12
D1 33R 3B34 DDR2-D28 3B22 E13
DDR2-A10 M2 D9 3B35 33R DDR2-D13 DDR2-A10 M2 D9 3B36 33R DDR2-D29
DDR2-A11 P7
10 13
B1 33R 3B37 DDR2-D14 DDR2-A11 P7
10 13
B1 33R 3B38 DDR2-D30
3B23 E6
11 14 11 14
DDR2-A12
3B42 RES
R2
12 15
B9 3B39 33R DDR2-D15 DDR2-A12
3B40 RES
R2
12 15
B9 3B41 33R DDR2-D31 3B24 E12
33R 33R
DDR2-CLK_P 220R J8
UDM
B3 3B56 DDR2-DQM1 DDR2-CLK_P 220R J8
UDM
B3 3B55 DDR2-DQM3 3B25 E7
DDR2-CLK_N K8 CK F3 3B57 33R DDR2-DQM0 DDR2-CLK_N K8 CK F3 3B58 33R DDR2-DQM2
LDM
33R
LDM
33R
3B26 E13
3B43 F7 J2 DDR2-DQS2_P 3B44 F7 J2
DDR2-DQS0_P
DDR2-DQS0_N 33R 3B45 E8 LDQS
VREF DDR2-VREF-DDR
DDR2-DQS2_N 33R 3B46 E8 LDQS
VREF DDR2-VREF-DDR 3B27 E6
2B48 2B49
3B47
33R 2B52
2p2 B7 3B48
33R 2B53
2p2 B7
3B28 E12
DDR2-DQS1_P DDR2-DQS3_P 100n
F
100n
F 3B29 E7
VSSDL

VSSDL
DDR2-DQS1_N 33R 3B49 A8 UDQS DDR2-DQS3_N 33R 3B50 A8 UDQS
2B50 2B51
33R 2B54 33R 2B55
2p2 VSS VSSQ 2p2 VSS VSSQ 3B30 E13
100p 100p
A3
E3
J3
N1
P9

J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
3B31 E6
3B54
DDR2-CLK_N 3B32 E12
DDR2-CLK_P
100R AT T-POINT 3B33 E7
3B34 E13
3B35 E6
3B36 E12
3B37 E7
G G 3B38 E13
3B39 E6
3B40 E9
3B41 E12
3B42 E3
3B43 F2
+1V8 3B44 F9
3B45 F3
H H 3B46 F9
3B47 F2
180R 1%
3B51

3B48 F9
3B49 F3
FB00
DDR2-VREF-DDR
3B50 F9
3B51 H2
180R 1%

3B52 I2
3B52

3B53 D7
I I 3B54 F3
3B55 E13
3B56 F7
3B57 F6
3B58 F12
7B00 D4
7B02 D10
FB00 I2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2 2009-10-30

DDR 2
8204 000 8983

18770_533_100119.eps
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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 137

10-16 B05 820400089535 DDR


DDR

DDR
B05A B05A
1 2 3 4 5 6 7 8 9 10 11 12 13
2B00 A2 3B02-1 C7
2B01 A3 3B02-2 B6
2B02 A3 3B02-3 C7
+1V8 DDR2-VREF-DDR +1V8 DDR2-VREF-DDR
2B03 A3 3B02-4 B6
2B04 A3 3B03 D9
2B05 A3 3B04-1 C12
A A
2B06 A4 3B04-2 B13
2B07 A4 3B04-3 B12

2B08
100p

100n
2B36
2B08 A6 3B04-4 C12
2B40

2B00

2B01

2B02

2B03

2B04

2B05

2B06

2B07
100n

100n

100n

100n

100n

100n

100n

100n
47u

2B17

2B37
100n

100p
2B41

2B09

2B10

2B11

2B12

2B13

2B14

2B15

2B16
100n

100n

100n

100n

100n

100n

100n

100n
47u
2B09 B8 3B05-1 C13
2B10 B8 3B05-2 C13
7B02
2B11 B9 3B05-3 B12

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
EDE1108AGBG-1J-F 7B03
B B 2B12 B9 3B05-4 C13

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
VDD VDDQ
H8 VDDL VREF
AT T-POINT
DDR2-A0
DDR2-A1 H3
0
Φ DDR2-A0 H8
VDD VDDQ 2B13 B9 3B06 H3
3B22
DDR2-A2 H7
J2
1
2 SDRAM 0
C8
C23B02-4 4 5
2
3B00-2
7
33R
DDR2-D16 DDR2-A1 H3
H7
0
1 Φ C8 2 3B04-2 7 2B14 B9 3B07-1 G6
DDR2-CLK_P DDR2-A3 3 1 33R 3
DDR2-D17 DDR2-A2 2 SDRAM 0 DDR2-D24
DDR2-A4 J8 D7 6 3B00-3 DDR2-D18 DDR2-A3 J2 3B05-3
C2 3 6 33R DDR2-D25
240R
DDR2-CLK_N DDR2-A5 J3
4
5
2
3
D33B02-2 2 7 33R DDR2-D19 DDR2-A4 J8
3
4
1
2
3B04-3
D7 3 6 33R DDR2-D26 2B15 B9 3B07-2 G7
DDR2-A6 J7 DQ D1 33R 1 8 3B02-1 DDR2-D20 DDR2-A5 J3 D3 33R 33R 2 7 3B05-2 DDR2-D27
3B27
DDR2-CLK_P DDR2-A7 K2
6 A
7
4
5
D93B00-4 4 5 33R DDR2-D21 DDR2-A6 J7
5
6 A
DQ
3
4
D1 1 8 3B05-1
33R
DDR2-D28 2B16 B10 3B07-3 G7
240R DDR2-A8 K8 B1 33R 3 6 3B02-3 DDR2-D22 DDR2-A7 K2 D93B04-4 4 5 DDR2-D29
8 6 7 5
DDR2-CLK_N DDR2-A9 K3
H2
9 7
B9 3B00-1 1 8
33R
33R DDR2-D23 DDR2-A8 K8
K3
8 6
B1
B93B04-1 1
33R
8
4 5 3B05-4
33R
DDR2-D30 2B17 A11 3B07-4 G6
DDR2-A10 10 DDR2-A9 9 7 DDR2-D31
3B28
DDR2-CLK_P DDR2-A11 K7
L2
11
B7 3B12
DDR2-A10 H2
K7
10
33R 2B18 F2 3B08-1 G7
C 240R
DDR2-CLK_N
DDR2-A12
DDR2-A13 L8
12
13
DQS A8 3B13 33R
DDR2-DQS2_P
DDR2-DQS2_N
DDR2-A11
DDR2-A12 L2
11
12
B7 3B14 DDR2-DQS3_P C 2B19 F3 3B08-2 G6
2B44 DDR2-A13 L8 DQS A8 3B15 33R DDR2-DQS3_N
33R 13
DDR2-BA0
DDR2-BA1
G2
G3
0
A2
RES 2p2
DDR2-BA0 G2
2B45 RES
2p2
33R 2B20 F3 3B08-3 G7
1 BA NU|RDQS 0
DDR2-BA2
DDR2-ODT
G1
2 DDR2-BA1
DDR2-BA2
G3
G1
1 BA
2
NU|RDQS
A2
2B21 F3 3B08-4 G6
RES F9
DDR2-CLK_P
3B01
240R E8
ODT DDR2-ODT
3B03 RES F9
ODT
2B22 F3 3B09 H9
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2
CKE DDR2-CLK_N F8 CK 2B23 F3 3B10-1 G12
DDR2-CS G8 DDR2-CKE F2
DDR2-RAS F7
CS
RAS
L3 DDR2-A14 DDR2-CS G8
CKE
CS
2B24 F4 3B10-2 G13
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14

D DDR2-WE F3
CAS
WE DDR2-CAS G7
RAS
CAS
NC L7
D 2B25 F4 3B10-3 G12
DDR2-DQM2 3B23 B3 DDR2-WE F3
DM|RDQS WE
33R VSS
VSSDL
VSSQ
DDR2-DQM3 3B24 B3
DM|RDQS 2B26 F6 3B10-4 G12
33R VSS VSSQ
2B27 F8 3B11-1 G12
A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
2B28 F8 3B11-2 G13
2B29 F9 3B11-3 G12
2B30 F9 3B11-4 G13
2B31 F9 3B12 C7
E E 2B32 F9 3B13 C6
+1V8 +1V8
DDR2-VREF-DDR
2B33 F9 3B14 C13
2B34 F10 3B15 C12
DDR2-VREF-DDR
2B35 F11 3B16 H7
2B36 A6 3B17 H7
2B37 A11 3B18 H13
2B38 F6 3B19 H12
2B26

2B38
100n

100p
2B42

2B18

2B19

2B20

2B21

2B22

2B23

2B24

2B25
100n

100n

100n

100n

100n

100n

100n

100n

F F

2B39
47u

2B35

100p
100n
2B43

2B27

2B28

2B29

2B30

2B31

2B32

2B33

2B34
100n

100n

100n

100n

100n

100n

100n

100n
2B39 F11 3B20 H1

47u
2B40 A2 3B21 I1
2B41 B8 3B22 B1
7B00
2B42 F2 3B23 D3
H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1

EDE1108AGBG-1J-F 7B01

H9

C1
C3
C7
C9
A1
E9

E1

A9

E2
L1
VDDL VREF EDE1108AGBG-1J-F
DDR2-A0 H8
VDD VDDQ
VDDL VREF 2B43 F8 3B24 D9
Φ
0 VDD VDDQ
DDR2-A1 H3 DDR2-A0 H8
DDR2-A2 H7
1
2 SDRAM 0
C8 2 3B07-2 7 DDR2-D0 DDR2-A1 H3
0
1 Φ 3B10-2
2B44 C6 3B25 I3
DDR2-A3 J2 C23B08-4 4 5 33R DDR2-D1 DDR2-A2 H7 SDRAM C8 2 7 DDR2-D8
3 1 2 0
G DDR2-A4 J8
J3
4 2
D7
D3 3B08-2 2
33R
7
3 6 3B07-3
33R
DDR2-D3 DDR2-A3 J2
J8
3 1
3B11-3 3
C2
3B10-3 33R 3
D7
6
6 33R
33R DDR2-D9
G 2B45 C12 3B26 I9
DDR2-A5 5 3 DDR2-D2 DDR2-A4 4 2 DDR2-D10
DDR2-A6
DDR2-A7
J7
K2
6 A
DQ
4
D1
D9 3B07-4 4
33R
5
1 8 3B08-1
33R
DDR2-D4
DDR2-D5
DDR2-A5
DDR2-A6
J3
J7
5
DQ
3
D3
D1
2
1
7 3B11-2
8 33R
DDR2-D11
DDR2-D12
2B46 H6 3B27 C1
7 5 6 A 4
DDR2-A8
DDR2-A9
K8
K3
8 6
B1
B9 3B07-1 1
33R
8
3 6 3B08-3
33R
DDR2-D6
DDR2-D7
DDR2-A7
DDR2-A8
K2
K8
7 5
D93B10-4 4
B1
5 3B11-1
33R 4
33R
5 3B11-4
DDR2-D13
DDR2-D14
2B47 H12 3B28 C1
9 7 8 6
DDR2-A10
DDR2-A11
H2
K7
10
33R DDR2-A9
DDR2-A10
K3
H2
9 7
B93B10-1 1 8
33R
33R DDR2-D15
3B00-1 C6 7B00 G4
11 10
DDR2-A12
DDR2-A13
L2
L8
12
13
DQS
B7
A8 3B17
3B16
33R
DDR2-DQS0_P
DDR2-DQS0_N
DDR2-A11
DDR2-A12
K7
L2
11
12
B7 3B18 DDR2-DQS1_P
3B00-2 B7 7B01 G10
2B46 RES L8 DQS A8 3B19 33R
+1V8
DDR2-BA0 G2
0
2p2
33R DDR2-A13 13
2B47 RES 33R
DDR2-DQS1_N
3B00-3 B7 7B02 B4
DDR2-BA1 G3 A2 DDR2-BA0 G2 2p2
DDR2-BA2 G1
1 BA
2
NU|RDQS
DDR2-BA1 G3
0
1 BA NU|RDQS
A2 3B00-4 C6 7B03 B10
G1
H DDR2-ODT
3B06 RES F9
ODT
DDR2-BA2
DDR2-ODT
2 H 3B01 C3 FB00 H1
180R 1%

DDR2-CLK_P 240R E8 3B09 RES F9


ODT
3B20

DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8


DDR2-CKE F2 DDR2-CLK_N F8 CK
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
FB00 RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
DDR2-VREF-DDR CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM0 3B25 B3 DDR2-WE F3
DM|RDQS WE
180R 1%

DDR2-DQM1 3B26 B3
33R VSS VSSQ DM|RDQS
3B21

VSSDL 33R VSS VSSQ


A3
E3
J1
K9

E7

A7
B2
B8
D2
D8

VSSDL

A3
E3
J1
K9

E7

A7
B2
B8
D2
D8
I I

1 2 3 4 5 6 7 8 9 10 11 12 13 5 2009-12-07

DDR 4
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 138

10-17 B06 820400089962 LVDS DVBS


Display Interfacing - VDisp

Display Interfacing - VDisp


B06A B06A
1 2 3 4 5 6 7 8

1G00 C4
1G03 B4
A A 2G43 C4
2G44 C3
3G28 C5
5G01 C3
5G02 C3
6G00 C6
B 1G03 B FG0H C5
T 3.0A 32V IG11 C5

5G01 1G00 FG0H


+VDISP-INT +VDISP
30R T 3.0A 32V

2G43

100n
5G02

30R
C 2G44
C
22u
RES

3G28 IG11
6G00

2K2 LTST-C190KGKT

D D

E E

F F

1 2 3 4 5 6 7 8

2 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 139

Video Out - LVDS

Video Out - LVDS


B06B B06B
1 2 3 4 5 6 7 8 9 10 11 12 13 1G50 G5 FG1C D4
1G51 G11 FG1D D4
1X05 G1 FG1E E4
2G24 C10 FG1F E4
2G25 C11 FG1G E4
A A 2G26 C11 FG1H E4
2G27 C11 FG1J E4
2G28 E11 FG1K E4
2G29 E11 FG1L E4
2G75 C10 FG1M E4
+3V3
2G76 C10 FG1N E4
B B 2G77 C10 FG1P F4
2G78 C10 FG1Q F4
2G79 C10 FG1R F9
+VDISP
2G7A C10 FG1S F9
RES

3G34

10K
2G92 C4 FG1T F9
2G93 C4 FG1U F9

100p

100p

100p

100p
FI-RE51S-HF

10p

10p

10p

10p

10p

10p
8
7
6
5
9G0K-1
9G0K-2
9G0K-3
9G0K-4
2G94 D4 FG1V F9

3G33

3G35
60 61

10K

10K
C 58 59 C

2G7A
2G77
2G75

2G76

2G78

2G79

2G24

2G25

2G26

2G27
RES

RES

RES
2G95 D4 FG1W F9

RES
56 57

1
2
3
4
54 55
RES FG34
3G32
FI-RE41S-HF
CTRL-DISP
SDA-DISP 100R 3G2W FG2H
52 53
51 2G96 D4 FG1Y D9
10p 50 51 SCL-DISP 50
2G92
48 49
100R
100R
3G2Y
3G2Z
FG2G 49
48
2G97 D4 FG1Z D9
10p 2G93 46 47 BACKLIGHT-PWM_BL-VS FG2K

10p
FG2J
44 45 BACKLIGHT-BOOST 100R 3G37 FG2R
47
46
2G98 D4 FG20 D9
2G94 42 43 BACKLIGHT-PWM-ANA-DISP 3G36 100R

10p 2G95
FG30 41
FG04
100R
3G30 FG2L
45
44 2G99 D4 FG21 D9
FG31 40 CTRL-DISP 43
FG32
FG33
39 CTRL-DISP 3G31 RES 100R
FG2M
42 3G2W C8 FG22 E9
D 10p 2G96
38
37 PX1A-
100R RES
FG2E
FG2F
41
40 D 3G2Y C8 FG23 E9
36 PX1A+ 39
10p
10p 2G97
2G99
35
34
PX1B-
PX1B+
FG1Y
FG1Z
38
37
3G2Z D8 FG24 E9
10p 2G98 FG20
PX3A- FG1C 33
32
PX1C-
PX1C+ FG21
36
35
3G30 D9 FG25 E9
PX3A+ FG1D
PX3B- FG1E
31
30 PX1CLK- FG22
34
33
3G31 D8 FG26 E9
PX3B+ FG1F PX1CLK+ FG23
PX3C- FG1G
FG1H
29
28 FG24
32
31 3G32 C8 FG27 E9
PX3C+ 27 PX1D- 30

PX3CLK-
FG11 26 PX1D+
PX1E- FG26
FG25
29 3G33 C9 FG28 E9
25 28

E PX3CLK+ FG1J
24 PX1E+ FG27
27
E 3G34 B9 FG29 E9
23 10p 2G28 26
FG1K
PX3D-
PX3D+ FG1L
22
21 PX2A- FG28 10p 2G29
25
24
3G35 C9 FG2A E9
PX3E- FG1M PX2A+ FG29
PX3E+ FG1N
20
19 PX2B- FG2A
23
22
3G36 D8 FG2B E9
PX2B+ FG2B
18
17 PX2C- FG2C
FG2D
21
20 3G37 D9 FG2C E9
PX4A- FG12 16 PX2C+ 19
PX4A+
PX4B-
FG13
FG14
15
PX2CLK-
FG1R 18 9G0G G11 FG2D F9
14 17
PX4B+
PX4C-
FG15
FG16
13 PX2CLK+ FG1S 16 9G0K-1 C4 FG2E D9
12 15
PX4C+ FG17
11 PX2D-
PX2D+ FG1U
FG1T
14 9G0K-2 C4 FG2F D9
F PX4CLK- FG18
FG19
10
9 PX2E-
FG1V
FG1W
13
12 F 9G0K-3 C4 FG2G C9
PX4CLK+ 8 PX2E+ 11

PX4D- FG1A
7
6 FG2P
10
9
9G0K-4 C4 FG2H C9
PX4D+ FG1B
5 8
PX4E- FG1Q
FG1P
4 7 FG04 D8 FG2J D5
PX4E+ 3 6
2 +VDISP RES 9G0G FG2N
5 FG11 E4 FG2K D9
1 4
1G50
3
2
FG12 F4 FG2L D10
1 FG13 F4 FG2M D10
TO DISPLAY 1G51
G G FG14 F4 FG2N G11
TO DISPLAY
FG15 F4 FG2P F11
1X05
EMC HOLE
FG16 F4 FG2R D11
FG17 F4 FG30 D5
FG18 F4 FG31 D5
FG19 F4 FG32 D5
FG1A F4 FG33 D5
H H
FG1B F4 FG34 C11

1 2 3 4 5 6 7 8 9 10 11 12 13

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AmbiLight CPLD

AmbiLight CPLD
B06C B06C
1G35 F2 2G10 E3 2G13 E8 2G16 E8 2G19 E9 2GA2 A3 2GA5 B3 3G10-3 D7 3G11-2 D3 3G13 D7 3GA1 D7 3GA2-3 F3 3GA5-2 B13 3GA6-1 E14 3GA6-4 E13 6GA0 F13 6GA3 F14 7GA1-2 D14 9GA0 H5 FGA1 A3 FGA4 F4 IGA0 C12 IGA3 C12
1G36 F2 2G11 E3 2G14 E8 2G17 E9 2GA0 A3 2GA3 B3 3G10-1 D7 3G10-4 D7 3G11-3 D7 3G14 D4 3GA2-1 F3 3GA2-4 F3 3GA5-3 B13 3GA6-2 E14 5GA0 A2 6GA1 F13 7GA0 C5 7GA2-1 E13 9GA1 C7 FGA2 F3 FGA5 F4 IGA1 C12
1G37 B14 2G12 E3 2G15 E8 2G18 E9 2GA1 A3 2GA4 F3 3G10-2 D7 3G11-1 D4 3G12 D7 3G15 E2 3GA2-2 F3 3GA5-1 B13 3GA5-4 B13 3GA6-3 E13 5GA1 A2 6GA2 F14 7GA1-1 D14 7GA2-2 E13 FGA0 A5 FGA3 F4 FGA6 F4 IGA2 C12

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

5GA0 FGA0
+3V3 VINT
30R

2GA0

2GA1

2GA2
100n

100n
1u0
A DEBUG ONLY A

5GA1 FGA1
+3V3 VIO
30R
2GA3

2GA5

100n
1u0

1G37
+3V3 1
2
B GCK3
GTS1
3GA5-4
3GA5-3
4
3
5
6 100R
3
4
B
GTS2 3GA5-2 2 7 100R 5
GSR 3GA5-1 1 8 100R 6
100R
VINT VIO SD51022

IGA0
7GA0 CPLED1

15
35

26
XC9572XL-10VQG44C0100
VCCINT Φ VCCIO AMBI-SPI-CLK-OUT-R IGA1
PXCLK54 43 AMBI-SPI-SDI-OUT_G1-R CPLED2
IXO1_43|GCK1
GCK2 44 AMBI-SPI-SDO-OUT-R
IXO1_44|GCK2
GCK3 1 IGA2
IXO1_1|GCK3
C PNX-SPI-CS-AMBIn 2
IXO1_2 IXO3_5
5 PNX-SPI-CSBn
CPLED3
C
PNX-SPI-CS-BLn 3 6 9GA1 RES BACKLIGHT-PWM IGA3
IXO1_3 IXO3_6
PNX-SPI-SDO 39 7 GCK2
IXO1_39 IXO3_7
PNX-SPI-SDI 40 8 CPLED1 +3V3
IXO1_40 IXO3_8
PNX-SPI-CLK 41 IXO3_12 12 BL-SPI-SDO
IXO1_41
42 13 BL-SPI-SDI 3
IXO1_42 IXO3_13
14 BL-SPI-CSn
IXO3_14
GTS1 36 16 3GA1 RES BACKLIGHT-PWM_BL-VS GCK3 5 7GA1-2
IXO2_36|GTS1 IXO3_16
GTS2 34 18 47R BL-SPI-CLK BC847BS(COL)
IXO2_34|GTS2 IXO3_18
GSR 33 4
IXO2_33|GSR
AMBI-SPI-CS-OUTn_R2-R 19 4 5 AMBI-PROG_B1 +3V3
IXO4_19
AMBI-PWM-CLK_B2 29 20 3G10-4 100R 3 6 AMBI-BLANK_R1
IXO2_29 IXO4_20
AMBI-SPI-CS-OUTn_R2 7 2 3G14 100R 30 21 2 7 3G10-3 100R AMBI-SPI-CS-EXTLAMPSn 6
IXO2_30 IXO4_21
D AMBI-LATCH1_G2
AMBI-TEMP
3G11-2 100R 8
3G11-1
1
100R
31
32
IXO2_31
IXO2_32
IXO4_22
IXO4_23
22
23
3G10-2 100R
3G13 100R
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1 GTS1 2 7GA1-1
D
CPLED3 37 27 3G12 10R 1 8 AMBI-SPI-SDO-OUT BC847BS(COL)
IXO2_37 IXO4_27
CPLED2 38 28 3 6 3G10-1 100R AMBI-LATCH2_DIS 1
IXO2_38 IXO4_28
3G11-3 100R +3V3
2G10 RES

2G11 RES

2G12 RES

2G13 RES

2G14 RES

2G15 RES

2G16 RES

2G17 RES

2G18 RES

2G19 RES
11
TCK
9 3
TDI
3G15

24
10K

10p

10p

10p

10p

10p

10p

10p

10p

10p

10p
TDO
10 GTS2 5 7GA2-2
TMS BC847BS(COL)
GND 4
+3V3
4
17
25

+3V3

E GSR 2 7GA2-1
E
BC847BS(COL)
1

5 330R 4

6 330R 3

7 330R 2

8 330R 1
DEBUG ONLY

3GA6-4

3GA6-3

3GA6-2

3GA6-1
1G36 1G35
1 1 3GA2-1 1 8 100R FGA6
2 2 3GA2-2 2 7 100R FGA4

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
3 3 3GA2-3 3 6 100R FGA5
4 4 3GA2-4 4 5 100R FGA3
5 5 FGA2
6 6

6GA0

6GA1

6GA2

6GA3
+3V3
F 7 8
F
100n RES

SD51022
2GA4

G G

BACKLIGHT-PWM 9GA0 BACKLIGHT-PWM_BL-VS

H H

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 141

SPI-Buffer

SPI-Buffer
B06D B06D
1 2 3 4 5 6

2GE0 A2
3GE0-1 B4
3GE0-3 B4
+3V3 3GE1-3 B4
+3V3
3GE1-4 B3
A A
3GE2 A4

3GE2
7GE1

10K
3GE3 B4

2GE0

100n
PDTC114EU

7GE0 PNX-SPI-CSBn
3GE4 B3

20
74LVC245A
3EN1
1 7GE0 B3
3EN2
G3
19
IGE0
7GE1 A4
3GE0-3

B
PNX-SPI-CLK 18
1
2
2 3
47R
6
3GE0-1
BL-SPI-CLK
B 9GE0-1 C3
17 3 1 8 BL-SPI-SDO
PNX-SPI-SDO 16
15
4
5
3GE1-3 6 3
47R RES 5
47R
4 3GE1-4
AMBI-SPI-CLK-OUT-R 9GE0-2 C3
AMBI-SPI-SDO-OUT-R
AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI
14
13
6
7 3GE4
3GE3
47R RES
47R RES PNX-SPI-SDI 9GE0-3 D3
12
11
8
9
47R 9GE1 C3
9GE2 D3
10

9GE3 D3
7

C
PNX-SPI-CLK 9GE0-2 2 BL-SPI-CLK
C IGE0 B3
6 9GE0-3 3
IGE1 D2
PNX-SPI-SDO BL-SPI-SDO

BL-SPI-SDI 9GE1 PNX-SPI-SDI

9GE2 ∗
PNX-SPI-CS-BLn IGE1 5 9GE0-4 ∗∗4 BL-SPI-CSn

PNX-SPI-CS-AMBIn 9GE3 AMBI-SPI-CS-OUTn_R2-R


D D

∗ Buffer

∗∗ Direct

1 2 3 4 5 6 2 2009-10-22

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10-18 B06 820400089572 LVDS Non DVBS


Display Interfacing - VDisp

Display Interfacing - VDisp


B06A B06A
1 2 3 4 5 6 7 8

1G00 C4
1G03 B4
A A 2G43 C4
2G44 C3
3G28 C5
5G01 C3
5G02 C3
6G00 C6
FG0H C5
B 1G03 B IG11 C5
T 3.0A 32V

5G01 1G00 RES FG0H


+VDISP-INT +VDISP
30R RES T 3.0A 32V

2G43

100n
5G02

30R RES
C C
2G44

22u
RES 3G28 IG11
6G00

2K2 LTST-C190KGKT

D D

E E

F F

1 2 3 4 5 6 7 8
2 2009-10-22

LVDS Non DVBS


8204 000 8957

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 143

Video Out - LVDS

Video Out - LVDS


B06B B06B
1 2 3 4 5 6 7 8 9 10 11 12 13 1G50 G5 FG1C D4
1G51 G11 FG1D D4
1X05 G1 FG1E E4
2G24 C10 FG1F E4
A A 2G25 C11 FG1G E4
2G26 C11 FG1H E4
2G27 C11 FG1J E4
2G28 E11 FG1K E4
2G29 E11 FG1L E4
2G75 C10 FG1M E4
B
+3V3
B 2G76 C10 FG1N E4
2G77 C10 FG1P F4
2G78 C10 FG1Q F4
+VDISP 2G79 C10 FG1R F9

RES
RES
2G7A C10 FG1S F9

3G34

10K
2G92 C4 FG1T F9

RES

RES

100p

100p

100p

100p
FI-RE51S-HF

10p

10p

10p

10p

10p

10p
8
7
6
5
2G93 C4 FG1U F9

9G0K-1
9G0K-2
9G0K-3
9G0K-4

3G33

3G35
60 61

10K

10K
C 58 59 C
2G94 D4 FG1V F9

2G7A
2G77
2G75

2G76

2G78

2G79

2G24

2G25

2G26

2G27
RES

RES

RES
RES

RES

RES
RES

RES
56 57

1
2
3
4
54 55
RES
RES FI-RE41S-HF
CTRL-DISP
SDA-DISP 100R
3G32
3G2W FG2H
FG34 52 53
51 2G95 D4 FG1W F9
10p 50 51 SCL-DISP 50
2G92
RES 48 49
100R
100R
3G2Y

RES 3G2Z
FG2G 49
48
2G96 D4 FG1Y D9
10p 2G93 46 47 BACKLIGHT-PWM_BL-VS FG2K
RES
10p 2G94
FG2J
44
42
45
43
BACKLIGHT-BOOST 100R 3G37 RES FG2R
47
46
2G97 D4 FG1Z D9
BACKLIGHT-PWM-ANA-DISP 3G36 100R
45
RES
10p 2G95
FG30
FG31
41
CTRL-DISP FG04
100R RES
3G30 FG2L
44 2G98 D4 FG20 D9
40 43
FG32
FG33
39 CTRL-DISP 3G31 RES 100R
FG2M
42 2G99 D4 FG21 D9
D RES
10p 2G96 RES
38
37 PX1A-
100R RES
FG2E
FG2F
41
40 D 3G2W C8 FG22 E9
36 PX1A+ 39
RES 10p 2G99 PX1B- FG1Y
RES
10p
10p
2G98
2G97
35
34 PX1B+
PX1C- FG20
FG1Z
38
37 3G2Y C8 FG23 E9
33 36
PX3A-
PX3A+
FG1C
FG1D
32 PX1C+ FG21 35 3G2Z D8 FG24 E9
31 34
FG1E
PX3B-
PX3B+ FG1F
30
29
PX1CLK-
PX1CLK+
FG22
FG23
33
32
3G30 D9 FG25 E9
PX3C- FG1G
PX3C+ FG1H
28
27 PX1D-
FG24
FG25
31
30 3G31 D8 FG26 E9
26 PX1D+ 29
PX3CLK-
PX3CLK+
FG11
FG1J
25 PX1E-
PX1E+
FG26
FG27
28 3G32 C8 FG27 E9
E FG1K
24
23 10p 2G28
27
26 E 3G33 C9 FG28 E9
PX3D- 22 25
FG1L FG28 10p 2G29
PX3D+
PX3E- FG1M
21
20
PX2A-
PX2A+ FG29
24
23
3G34 B9 FG29 E9
PX3E+ FG1N PX2B- FG2A
19
18 PX2B+
PX2C- FG2C
FG2B
22
21 3G35 C9 FG2A E9
17 20
PX4A-
PX4A+
FG12
FG13
16
15
PX2C+
FG1R
FG2D
19
18
3G36 D8 FG2B E9
FG14
PX4B-
PX4B+ FG15
14
13
PX2CLK-
PX2CLK+ FG1S
17
16
3G37 D9 FG2C E9
PX4C- FG16
PX4C+ FG17
12
11 PX2D- FG1T
15
14 9G0G G11 FG2D F9
PX2D+ FG1U
F PX4CLK- FG18
FG19
10
9 PX2E-
FG1V
FG1W
13
12 F 9G0K-1 C4 FG2E D9
PX4CLK+ 8 PX2E+ 11

PX4D- FG1A
7
6 FG2P
10
9
9G0K-2 C4 FG2F D9
PX4D+ FG1B
PX4E- FG1Q
5
4
8
7
9G0K-3 C4 FG2G C9
PX4E+ FG1P
3 6
2 +VDISP RES 9G0G FG2N
5 9G0K-4 C4 FG2H C9
1 4
1G50
3
2
FG04 D8 FG2J D5
1 FG11 E4 FG2K D9
TO DISPLAY 1G51
G G FG12 F4 FG2L D10
TO DISPLAY
FG13 F4 FG2M D10
1X05
EMC HOLE
FG14 F4 FG2N G11
FG15 F4 FG2P F11
FG16 F4 FG2R D11
FG17 F4 FG30 D5
H H FG18 F4 FG31 D5
FG19 F4 FG32 D5
FG1A F4 FG33 D5
FG1B F4 FG34 C11
1 2 3 4 5 6 7 8 9 10 11 12 13

2 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 144

AmbiLight CPLD

AmbiLight CPLD
B06C B06C
1G35 G2 2G10 F3 2G13 F7 2G16 F8 2G19 F9 2GA2 B4 2GA5 B3 3G10-3 E6 3G11-2 E3 3G13 E7 3GA1 E6 3GA2-3 G3 3GA5-2 B12 3GA6-1 F13 3GA6-4 F12 6GA0 F12 6GA3 F13 7GA1-2 D13 9GA0 H5 FGA1 B4 FGA4 G4 IGA0 C11 IGA3 C11
1G36 G2 2G11 F3 2G14 F8 2G17 F8 2GA0 B3 2GA3 B3 3G10-1 E6 3G10-4 E7 3G11-4 E4 3G14 E4 3GA2-1 G3 3GA2-4 G3 3GA5-3 B12 3GA6-2 F13 5GA0 A3 6GA1 F12 7GA0 D5 7GA2-1 E12 9GA1 D7 FGA2 G3 FGA5 G5 IGA1 C11
1G37 B13 2G12 F3 2G15 F8 2G18 F9 2GA1 B4 2GA4 G3 3G10-2 E7 3G11-1 E6 3G12 E6 3G15 E2 3GA2-2 G3 3GA5-1 B12 3GA5-4 B12 3GA6-3 F12 5GA1 B2 6GA2 F13 7GA1-1 D13 7GA2-2 E12 FGA0 A5 FGA3 G5 FGA6 G4 IGA2 C11

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A A
DEBUG ONLY
5GA0 FGA0
+3V3 VINT
30R

2GA0

2GA1

2GA2
100n

100n
1u0
1G37
B +3V3 1
2
B
5GA1 FGA1
+3V3 VIO GCK3 3GA5-4 4 5 3
30R GTS1 3GA5-3 3 6 100R 4
GTS2 3GA5-2 2 7 100R 5
2GA3

2GA5

100n
GSR 3GA5-1 1 8 100R 6
1u0

100R
SD51022

IGA0
CPLED1

IGA1
CPLED2
C IGA2
C
CPLED3

VINT VIO IGA3


GCK2
+3V3
7GA0

15
35

26
XC9572XL-10VQG44C0100 3
VCCINT Φ VCCIO AMBI-SPI-CLK-OUT-R
PXCLK54 43 AMBI-SPI-SDI-OUT_G1-R GCK3 5 7GA1-2
IXO1_43|GCK1 BC847BS(COL)
GCK2 44 AMBI-SPI-SDO-OUT-R
IXO1_44|GCK2
GCK3 1 4
IXO1_1|GCK3
+3V3
D PNX-SPI-CS-AMBIn
PNX-SPI-CS-BLn
2
3
IXO1_2 IXO3_5
5
6 9GA1
PNX-SPI-CSBn
BACKLIGHT-PWM 6
D
IXO1_3 IXO3_6
PNX-SPI-SDO 39 7
IXO1_39 IXO3_7
PNX-SPI-SDI 40 8 CPLED1 GTS1 2 7GA1-1
IXO1_40 IXO3_8 BC847BS(COL)
PNX-SPI-CLK 41 IXO3_12 12 BL-SPI-SDO
IXO1_41
42 13 BL-SPI-SDI 1
IXO1_42 IXO3_13
14 BL-SPI-CSn +3V3
IXO3_14
GTS1 36 IXO3_16 16 3GA1 BACKLIGHT-PWM_BL-VS
IXO2_36|GTS1
GTS2 34 18 47R BL-SPI-CLK 3
IXO2_34|GTS2 IXO3_18
GSR 33
IXO2_33|GSR
AMBI-SPI-CS-OUTn_R2-R 19 3 6 AMBI-PROG_B1 GTS2 5 7GA2-2
IXO4_19 BC847BS(COL)
AMBI-PWM-CLK_B2 29 20 3G10-3 100R 2 7 AMBI-BLANK_R1
IXO2_29 IXO4_20
AMBI-SPI-CS-OUTn_R2 2 7 3G14 100R 30 21 1 8 3G10-2 100R AMBI-SPI-CS-EXTLAMPSn 4
IXO2_30 IXO4_21
AMBI-LATCH1_G2 3G11-2 100R 4 5 31 22 3G10-1 100R AMBI-SPI-CLK-OUT +3V3
IXO2_31 IXO4_22
E AMBI-TEMP
CPLED3
3G11-4 100R 32
37
IXO2_32 IXO4_23
23
27 3G12 10R
3G13
4
100R
5
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT 6
E
IXO2_37 IXO4_27
CPLED2 38 28 8 1 3G10-4 100R AMBI-LATCH2_DIS
IXO2_38 IXO4_28
3G11-1 100R GSR 2 7GA2-1
11 BC847BS(COL)
RES

2G11 RES

2G12 RES

RES

2G14 RES

2G15 RES

2G16 RES

2G17 RES

2G18 RES

2G19 RES
TCK
9 1
TDI

5 330R 4

6 330R 3

7 330R 2

8 330R 1
3G15

24
10K

10p

10p

10p

10p

10p

10p

10p

10p

10p

10p

3GA6-4

3GA6-3

3GA6-2

3GA6-1
TDO
2G10

2G13
10
TMS
GND
+3V3
4
17
25

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
F F

6GA0

6GA1

6GA2

6GA3
DEBUG ONLY
1G36 1G35
1 1 3GA2-1 1 8 100R
2 2 3GA2-2 2 7 100R FGA6
3 3 3GA2-3 3 6 100R FGA4
4 4 3GA2-4 4 5 100R FGA5
5 5 FGA2 FGA3
6 6
G 7 8
+3V3
G
100n RES

SD51022
2GA4

BACKLIGHT-PWM 9GA0 BACKLIGHT-PWM_BL-VS

H H

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 145

SPI-Buffer

SPI-Buffer
B06D B06D
1 2 3 4 5 6
2GE0 A2
3GE0-1 B4
3GE0-3 B4
3GE1-3 B4
3GE1-4 B3
3GE2 A4
+3V3
+3V3 3GE3 B4
A A 3GE4 B3
7GE0 B3

3GE2
7GE1

10K
7GE1 A4

2GE0

100n
PDTC114EU
9GE0-1 C3
7GE0 PNX-SPI-CSBn 9GE0-2 C3

20
74LVC245A
3EN1
1 9GE0-3 D3
3EN2
G3
19
IGE0 9GE1 C3
PNX-SPI-CLK 18 2 3
3GE0-3
6 BL-SPI-CLK
9GE2 D3
1
B 17
2
3
47R
1
3GE0-1
8 BL-SPI-SDO
B 9GE3 D3
PNX-SPI-SDO 16 4 3GE1-3 6 3 47R AMBI-SPI-CLK-OUT-R IGE0 B3
15 5 47R RES 5 4 3GE1-4 AMBI-SPI-SDO-OUT-R
AMBI-SPI-SDI-OUT_G1-R 14 6 3GE3 47R RES PNX-SPI-SDI IGE1 D2
BL-SPI-SDI 13 7 3GE4 47R RES
12 8 47R
11 9
10

PNX-SPI-CLK 7 9GE0-2 2 BL-SPI-CLK


C C
PNX-SPI-SDO 6 9GE0-3 3 BL-SPI-SDO

BL-SPI-SDI 9GE1 PNX-SPI-SDI

9GE2
*
5 9GE0-4
PNX-SPI-CS-BLn IGE1
** 4 BL-SPI-CSn

PNX-SPI-CS-AMBIn 9GE3 AMBI-SPI-CS-OUTn_R2-R


D D

Buffer
* Direct
**
1 2 3 4 5 6
2 2009-10-22

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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 146

10-19 B07 820400089602 DVBS FE


DVBS-FE

DVBS-FE
B07A B07A
1 2 3 4 5 6 7 8 9 10 11 12 13
1R00 H5 2R53 B12
1R01 H3 2R54 G7
1R10 G4 2R55 G7
7R01-1
2R00 B3 2R56 G8
A A 2R01 B3 2R61 F7
STV0903BAC
7R01-2
STV0903BAC
Φ
2R02 B4 2R62 H4
+1V-DVBS 15 Φ 1
XTAL 122
XTALI MAIN VS
52 SENSE+1V0-DVBS
2R03 B4 3R00 C9
17 POWER_VIA 4 124 16 3R02 FR00
AGC
NC XTALO AGCRF1
22 6
I2C-ADDRESS : D0 1K0
2R53
2R04 B3 3R01 C9

2R00

2R01

2R02

2R03

2R10
100n

100n

100n
25 10 59 63 47n

10n

10n
DIRCLK 0
28 14 104 64
31
33
GNDA
113
117
NC
103
100
CLKI
CLKI2
1
2
65
67
2R05 B3 3R02 A12
NC CLKOUT27 3

B
36
39
121
125 QM 11
N
D
4
5
68
70
B 2R06 B4 3R03 B12
42 QP 12 I1 71
P 6

+1V-DVBS
45
48
GND_HS
129
CLKOUT
7
73
74
3R03
3R04
47R
47R
TS-DVBS-DATA
TS-DVBS-CLOCK
2R07 C3 3R04 B12
51 130 75 3R05 47R
53 131 IM 8
N
STROUT
DPN
78 3R06 47R
TS-DVBS-SOP
TS-DVBS-VALID 2R08 C3 3R05 B12

2R04

2R05

2R06

2R11

2R12

2R13
100n

100n

100n
57 132 7 Q1 79

10n

10n

10n
VDD1V0 IP P ERROR NC
61
66
133
134 82 NC
2R09 C4 3R06 B12

2R20
69 135 83

6p8
72
77
136
137
60
56
0
CS
84
86
NC
NC 2R10 B4 3R07 D12
1 NC
+1V-DVBS 81
85
138
139 DISECQ-DET RES 2R21 1n0 128
DISEQCIN1
87
89
NC
NC
2R11 B4 3R08-1 G8
C 88 140 F22-DISECQ-TX 20
DISEQCOUT1
90 NC
C 2R12 B4 3R08-2 G8
2R07

2R08

2R09

2R14

2R15
100n

100n

100n
93 141 126 91

10n

10n
NC FSKRX_IN NC
99 142 NC
107 94
FSKRX_OUT NC
102
105
143
144 SCL-SSB
RES 2R22 47p IR04
97
SCL
NC 95
108
NC
NC
2R13 B5 3R08-3 G8
110 145 SDA-SSB 100R 3R01 98 109

IR00
112 146
147 SCLT
RES 2R23 47p 100R 3R00 IR03
19
SDA
111
115
NC
NC 2R14 C4 3R08-4 G8
5R00 SCLT NC
+3V3-DVBS
30R
+3V3-DEMOD +3V3-DEMOD 21
38
VIA 148
149
SDAT 18
SDAT
1 116
119
NC
NC
2R15 C4 3R09 F7
54 150 120 NC
2R16 D2 3R10 E9
2R16

2R46

2R47

2R48

2R49

2R50

2R51

2R52
100n

100n

100n

100n
76 151
22u

10n

10n

10n
80 VDD3V3 152 RESET-DVBS 62 40
IR02 RESETB 0 IR05 3R07

D
92
96
153
154
9R00
RES
58
STDBY
COMP
1
41
120K D 2R17 D3 3R11 D9

3R13
106 155 26 101

10K
FR02 TCK 1 DISECQ-RX

+1V-DVBS 2
156
157
FR03
FR04
23
24
TDI
TDO
2
3
50
49
NC
NC
2R18 E3 3R12 E7
3 VDDA1V0 158 3R11 29 47
159 +3V3-DVBS
10K
FR05
FR06
27
TMS
TRST
4
5
46
NC
NC 2R19 E4 3R13 D9
2R17

100n

5 160 44
6 NC
9 161
GPIO 7
43 NC
2R20 C12 3R14 G3

3R10
13 162 37

1K0
8 NC
114 163 35
118
123
VDDA2V5
164
165
9
10
34
32
NC
NC 2R21 C9 3R15 G3
FR07 11 NC
+2V5-DVBS 127
12
13
30
55
NC
NC
2R22 C9 5R00 D1
E E 2R23 C9 5R01 H1
2R18

2R19

2R24

2R25

2R26
100n

100n

100n

100n

100n

+3V3RF
2R24 E4 5R02 H3
3R12 IR06 2R25 E4 6R00 I3
4R7
2R26 E4 7R01-1 A10
2R31

2R32

2R33

2R34

2R35

2R61
1n0

1n0

1n0

1n0

1n0

10u
2R27 H1 7R01-2 A5
F F 2R28 H2 7R02 F5
2R37
2R29 I3 9R00 D9
7R02
+3V3RF +3V3RF
10p
STV6110AT 6
LNA LT
8 11 14
MIX DIG BB
22 27
VCO
28
SYN
2R31 F6 9R02 G5
3 2R40
3R09
30 VSS 32
2R32 F6 FR00 A12
16M

XTAL_OUT XTAL
1R10

2
XTAL_IN 1K0 100p
31 18 4 5 QP
2R38 4 IP
2R33 F6 FR01 H3
3R14

3R15

19 3 6 3R08-4 100R
10K

10K

Φ
1 IN QM
1 3R08-3 100R
10p XTAL_CMD

SCLT IR07 12
SCL
SATELLITE
TUNER
QP
QN
21
20 2
1
7 3R08-1
8
100R
IP
IM 2R34 F6 FR02 D9
G SDAT IR08 13
SDA
I2C-ADDRESS : C6 RF_OUT
7 NC
3R08-2 100R
G 2R35 F6 FR03 D9
10p

10p

10p

AGC 2 10p
AGC
34
2R37 F4 FR04 D9
2R39

9R02 16 35
10p

2R41

2R54

2R55

2R56

AS
RES 36
23
24 NC VIA
37
38
2R38 G4 FR05 D9
NC
39
1R01
1 2R43
4
40
41
2R39 G4 FR06 D9
5R01 IR01 +3V3RF RF_IN
+3V3-DVBS
30R
2
3
4
5 27p
42
2R40 F7 FR07 E9
GND

H RF LNA LT MIX DIG BB VCO


H 2R41 G7 IR00 D2
2R27

2R28

SYN HS
22u

10n

5R02

5 3 9 10 15 17 25 26 29 33
27n

2R43 H4 IR01 H2
FR01 1R00
2R45 I3 IR02 D9
2R62

0p56

LNB-RF1 310430133871

2R46 D3 IR03 C10


SM15T
6R00

2R29

2R45

100p
1n0

2R47 D3 IR04 C10


1
2
3
4

2R48 D4 IR05 D12


I I 2R49 D4 IR06 E7
2R50 D4 IR07 G3
2R51 D5 IR08 G4
2R52 D5
1 2 3 4 5 6 7 8 9 10 11 12 13
2 2009-10-22

DVBS-FE
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 147

10-20 B08 820400089624 DVBS Supply


DVBS-Supply

DVBS Supply
B08A B08A
1 2 3 4 5 6 7 8 9 10 11 12 13 2T00 A4 3T20 I4
2T01 A4 3T21 B8
2T02 A5 3T23 G8
2T03 B5 3T24 H10
2T04 B7 3T25 I10
5T00
2T05 B8 3T26 I10
IT00
+5V-DVBS
2T06 B5 3T28 I10
A 30R A
7T00-1
1 6 2T07 C5 3T29 G7

2T00

2T01

2T02
ST1S10PH

22u

22u

22u

SW
2 7
IT01 5T01 IT18 FT06
+1V-DVBS
2T08 C7 3T31 G2
+2V5-DVBS INH VIN SW
5 3
3u6 2T09 C6 5T00 A4

RES 1n0
SYNC VFB
2T10 B8 5T01 A7

2T03

2T04

2T05
GND

22u

22u
A P HS
4 8 9
3T00 RES 2T11 D5 5T02 C5
1K0 1% 2T12 D7 5T03 E4
7T00-2
13
IT02 2T10 RES
2T13 E5 5T04 F8
B ST1S10PH 15
4n7 B 2T14 E5 6T00 C4

1%
2T36 IT24

RES 3T01

3T02
10 VIA 12

22K
SENSE+1V0-DVBS
IT20
2T15 E6 6T01 C4

3K3
3T03 4n7
+3V3-DVBS 14 3T21 2T16 E6 6T02 C4

11
10K

2T06

100n
1K0 1% 2T17 E7 6T03 E4
LD3985M25 2T18 E3 6T04 F8
7T01
2T19 E3 6T05 H3
6T01 RES 6T00 RES 6T02 RES IT03 FT07
+5V-DVBS 1
IN OUT
5 +2V5-DVBS 2T20 E7 7T00-1 A6
BAS316 IT19
C
BAS316 BAS316
3
INH BP
4
C 2T21 F4 7T00-2 B6

2T07

100n

2T08

2T39
30R

1u0

1u0
5T02 COM 2T22 F10 7T01 C6

2T09

10n
2T23 F9 7T02 D6

2
2T24 F9 7T03 E6
2T25 F4 7T04-1 G4
2T26 F8 7T04-2 H4
7T02
LD1117DT33 2T27 G8 FT00 E3
FT08
3
IN OUT
2 +3V3-DVBS 2T28 H8 FT04 H9
D D

16V
COM 2T29 H9 FT05 I5

2T11

100n

2T12
2T30 H7 FT06 A9

22u
1

2T31 I4 FT07 C9
2T32 I3 FT08 D9
+24V
2T33 I3 IT00 A5
3T04 IT04 2T13 2T34 I5 IT01 A7
3R3 47n 2T35 G5 IT02 B8
100u 35V

100u 35V
E E 2T36 B8 IT03 C5
2T14

2T15

2T16

2T17
220n

220n
FT00 5T03 IT05 2T37 F9 IT04 E5
+5V-DVBS
33u
2T38 F10 IT05 E4
220u 16V

2T39 C7 IT06 F4
SS24
2T19

6T03

3T05

22R
22u

7T03 2T20 IT10 3T10

14
2T18 TPS54283PWP
IT07 F4
1

PVDD1 2T40 H8
IT06 IT25
2
Φ PVDD2 13
IT26 47n 3R3

3
BOOT1 BOOT2
12
IT09 5T04 2T41 G9 IT08 G5
SW1 SW2 +V-LNB
5
EN1 EN2
6 IT32 33u 2T42 I10 IT09 F7
2T21

7 8

2T22
1n0

100u 25V
FB1 FB2
IT10 E7

SS24
3T11

6T04

2T23

2T24

2T37

2T38
2T43 I10

22R

10u

10u

4u7

4u7
F 9
ILIM2
16
F 3T00 B8 IT11 F8

RES
10 17 RES RES
+24V IT07 SEQ
11 18
BP IT11
19 3T01 B7 IT12 G8
2T25

20
1n0

3T02 B8 IT13 G7

2T26
21

1n0
VIA2 22
3T03 B4 IT14 H7
100K
3T31

3T06

23
10K

24
IT27 25
IT12 3T04 E4 IT15 I4
IT08 26
3T05 E4 IT16 I5

2T27
6 GND GND_HS

1n0
4

15

3T06 G4 IT17 G4
10u

3T07 IT21 2T35


+3V3 2 7T04-1
G 10K
BC847BS(COL)
G 3T07 G3 IT18 A7
3T29

1
1K0

3T08 G3 IT19 C7
3T08

10K

IT17 3T23 IT29 2T41 3T09 I5 IT20 B5


IT13
33K RES 1n0
3T10 E8 IT21 G3
2T28 FT04
+V-LNB
3T11 F8 IT22 H3
3T13 RES

3
22n
3T12
3T12 H8 IT23 H3
3K3

6T05 IT22 3T14 3T13 H7 IT24 B9

2T29
5

4u7
7T04-2

RES
+24V 47K
BC847BS(COL)
BZX384-C 2K2 IT23 5%
3T14 H3 IT25 F5
H H
3T15

3T16

4
3K3

47K

13V IT14 RES


3T15 H7 IT26 F7
5%
2T30 RES
3T17

1K0

RES
3T16 H8 IT27 G5
22n

3T24
SENSE+1V0-DVBS
15K 3T17 H3 IT29 G8
2T40

220p

3T18 I4 IT30 I10


IT15
+5V-DVBS
2T31 RES 3T25
V0-CTRL 3T19 I5 IT32 F7
22n 330K
RES 3T09

3T20 2T42 IT30 3T28


3K3

1X09
3T19 RES
2T32 RES

REF EMC HOLE


2T33 RES

18K RES 10n 100K


5% RES
3T18

I I
3K3

33K
22u

22u

IT16 3T26
5%

RES 2T34

RES 10K
2T43

100n
22n

RES

FT05

1 2 3 4 5 6 7 8 9 10 11 12 13
4 2009-10-22

DVBS-SUPPLY
8204 000 8962

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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 148

DVBS-Supply

DVBS-Supply
B08B B08B
2T50 B4
1 2 3 4 5 6 7 8 9 2T51 B5
2T52 B5
2T53 C7
2T54 C4
2T55 D1
2T56 D1
2T57 D2
2T58 D2
A A 2T59 E4
2T60 C8
2T61 E6
+12V +12V +3V3-DVBS
2T62 D9
3T22 B7
IT50
3T27 E7
3T50 B5
3T51 C4

100u 35V

100R

220R
2T50

2T51

3T50

5T50

3T22
100n

22u
RES RES 3T52 C6
3T53 C7
IT28
3T54 D7
B V0-CTRL
B 3T55 C4
3T56 D4

2T52

220n
3T57 D6
3T58 C8
3T59 D8
3T60 C4
IT60 3T61 C4
3T62 C7
5T52 5T50 B6
7T50-1 IT51 IT52 5T51 D2
220u

19

18
LNBH23Q LNB-RF1 5T52 C7
3T51
Φ

VCC

VCC_L
SCL-SSB IT53 3T52 3T53 6T50 C7

BAT54 COL
C 100R ISEL
28
C 6T51 D7

2T53

6T50
220n
9 22K 15R
3T61 SCL 6T52 D1
SDA-SSB 6 4
SDA LX 6T53 D2
3T60 RES 100R
10
ADDR VORX
21 6T54 E6
10K 3T55 RES IT54 3T62 IT67 2T60 3T58 RES IT55 6T55 D1
+12V LNB-RF1 DISECQ-DET 2T54 RES 29 22 DISECQ-DET
DETIN VOTX 7T50-1 C5
10n IT61 10K IT62 IT66 1R0 10u 2K2 7T50-2 E5

STPS2L30A
3T56 3T57 RES

3T59 RES

2T62 RES
12 11 +3V3-DVBS
DSQIN DSQOUT 7T51 E7

6T51
9T50

2K2

10n
10K IT63 10K
F22-DISECQ-TX RES 9T51 13
EXTM
1 9T50 D4
STPS2L30A

IT65 2 9T51 D4
RS1D

RS1D
6T55

6T52

6T53

14 3
RES TTX 9T52 F6
7
IT28 B6
D IT56 5T51 IT57
30
VCTRL
8
16
D IT50 A5
IT51 C7

3T54 RES
+V-LNB 27 17
VUP NC

150R
IT58 23 IT52 C8
30R
15 24
100u 35V

100u 35V

BYP IT53 C6
2T55

2T56

2T57

2T58
470n

470n

25
RES IT54 C7
26
IT64 IT55 C9
2T59

470n 31

GND_HS
A_GND

P_GND
32
6T54 RES RES IT56 D1
IT68
7T51 IT57 D3
BC817-25W
BAS316 IT58 D5

20

33
IT59 E8

2T61 RES
IT69 IT60 C6

1n0

3T27 RES
E E IT61 D4

22R
IT62 D5
IT63 D5
IT64 D7
IT65 D4
41
42

7T50-2 IT59 IT66 D6


LNBH23Q 9T52 RES DISECQ-RX IT67 C8
VIA IT68 E6
34 39
35 VIA 40 IT69 E7
VIA
36
VIA

F F
37
38

1 2 3 4 5 6 7 8 9

4 2009-10-22

DVBS-SUPPLY
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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 149

10-21 B09 820400089822 DVBS Con.


DVBS Connector Board

DVBS Connector Board


B09A B09A
1 2 3 4 5 6 7 8 9

+3V3
1C85 F4 5C53 F3
1C86 B4 5C54 F4
1F53 D9 9C50 E7
1M09 D5 FC50 C7

3C74

100K
1M59
FC70
AMBI-SPI-CLK-OUT 1
1M20 B9 FC51 C7
A AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1
FC71
FC72
2
3
2C76 A 1M59 A5 FC52 D8
FC87
1M71 E5 FC53 D8
4 3C75 100p
AMBI-PWM-CLK_B2 FC73
5 LIGHT-SENSOR 2C70 B2 FC54 D8
V-AMBI 6 2C93 100R 2C77 2C76 A7 FC55 D8
AMBI-SPI-CS-OUTn_R2 FC74
7
AMBI-LATCH1_G2 FC75
8 47n RES 3C76 100p TO 2C77 A7 FC56 E8
RC
AMBI-PROG_B1 FC76
9 LED PANEL 2C78 B7 FC57 E8
10 IC73 100R 2C78
AMBI-BLANK_R1 FC77
11 FC88
1M20 2C79 B7 FC58 E8
FC78
V-AMBI 12 LED-2
IC74 3C77 100p
FC89
1 2C80 B7 FC59 F7
AMBI-LATCH2_DIS 13 2
AMBI-SPI-CS-EXTLAMPSn FC80
14 100R FC90
3
2C81 B9 FC60 E8
3C70 100R FC79 FC91
AMBI-TEMP 15 4 2C82 C7 FC61 E8
B 16
17
+3V3-STANDBY
2C79 FC93
FC92
5
6
B 2C83 E4 FC62 E3
FC81 FC94 2C84 E4 FC63 E3
18 7
2C70

100n

IC75 +5V
19 LED-1 3C78 100p 8 2C85 F5 FC64 E8
20
21 100R 2C80 2C86 C7 FC70 A5

2C81

100n
FC82
FC83 1C86 22 2C87 D7 FC71 A4
+24V 23 100p
T 2.0A 63V 24 FC95 3C79
2C88 D7 FC72 A5
KEYBOARD
25 2C89 D7 FC73 A4
10R 100p
2C90 E7 FC74 A4
FH12-25S-0.5SH(55) 2C82 2C91 F7 FC75 A5
FC50 3C84 2C92 F7 FC76 B4
C SDA-BL
100R
C 2C93 A6 FC77 B5

2C86

10p
3C70 B2 FC78 B4
3C71 E7 FC79 B4
SCL-BL
FC51 3C85 3C74 A7 FC80 B5
100R 3C75 A7 FC81 B5

2C87

10p
3C76 A7 FC82 B5
3C77 B7 FC83 B4
3C86 3C78 B7 FC87 A7
BL-SPI-CLK
1M09 3C79 C7 FC88 B9
100R

2C88

100p
D * HOTEL TV +24V
1
2 D 3C80 E4 FC89 B9
3 1F53 3C81 E4 FC90 B9
FC52
3C90
4
3C88-1
1 3C82 E4 FC91 B9
+3V3 * 10K
RES 6 5 BL-SPI-SDO 8
100R
1
FC53
2
3 3C83 E4 FC92 B9
* 3C91

2C89
3C84 C7

100p
FAN-CTRL1 RES 502382-0470 FC54 4 FC93 B9
FC55 5
100R
6
3C85 C7 FC94 B9
FC62 3C80
TACH01 FC56 7 3C86 D7 FC95 C7
8 3C87 F7
100R
1M71 2
3C88-2
7 FC57 9
FC96 E4
FC96 BL-SPI-SDI
RES 3C81 3C88-1 D7 FC97 E4
SCL-BL 100R 10
1

2C90

100p
FC58 11 3C88-2 E7 FC98 E5
FC63 3C82 100R FC97 2 FC64
E TACH02
100R
FC98
3
4
FC60
12
13 E 3C88-4 F7 FC99 F5
RES 3C83 3C71
FC61 14 3C90 D3 IC73 B7
2C83

2C84
100p

100p

SDA-BL 1735446-4 BACKLIGHT-PWM-ANA-DISP 15 16


100R
3C91 D4 IC74 B7
100R

9C50
TEMPERATURE 502386-1470 3C92 E4 IC75 B7
FAN-CTRL2 * 3C92

100R
RES
SENSOR 3C93 F3 IC78 F4
+3V3 * 3C93
RES
BL-SPI-CSn 4
3C88-4
5
10K
FAN-DRV FC99 100R

2C91

100p
5C54
2C85

1u0

+3V3
F 30R RES
BACKLIGHT-PWM_BL-VS
FC59 3C87 F
T 1.0A 63V

100R
1C85

2C92

1n0
5C53
+12V IC78
30R RES

1 2 3 4 5 6 7 8 9 2 2009-10-22

DVBS CONNECTOR BOARD


8204 000 8982

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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 150

10-22 B09 820400089812 Non DVBS Con.


Non DVBS Connector Board

Non DVBS Connector Board


B09A B09A
1 2 3 4 5 6 7 8 9 1F53 D9 5T54 F3
1M09 C5 9T50 E7
+3V3
1M20 B9 FC83 B4
1M59 A5 FT50 C7
1M59
1M71 E5 FT51 C7
FT70
1T85 F4 FT52 D8

100K
3T74
AMBI-SPI-CLK-OUT 1
AMBI-SPI-SDO-OUT FT71
2 1T86 B4 FT53 D8
A AMBI-SPI-SDI-OUT_G1 FT72
3
4
2T76 A 2T70 B3 FT54 D8
AMBI-PWM-CLK_B2 FT73 FT87
5 100p
V-AMBI 6 LIGHT-SENSOR
3T75 2T76 A7 FT55 D8
AMBI-SPI-CS-OUTn_R2 FT74
AMBI-LATCH1_G2 FT75
7 100R 2T77 2T77 A7 FT56 E8
8
9 IT73 3T76 100p TO 2T78 B7 FT57 E8
AMBI-PROG_B1 FT76 RC
AMBI-BLANK_R1 FT77
10 LED PANEL 2T79 B7 FT58 E8
11 100R 2T78
1M20
AMBI-LATCH2_DIS FT78
V-AMBI 12 FT88 2T80 B7 FT59 F7
13 IT74 3T77 100p 1
AMBI-SPI-CS-EXTLAMPSn FT80
14
LED-2 FT89
2 2T81 B9 FT60 E8
AMBI-TEMP 3T70 FT79 100R FT90
100R
15
FT91
3 2T82 C7 FT61 E8
16 4
B 17 +3V3-STANDBY FT92
5 B 2T83 E4 FT64 E7
2T70

100n

FT81 2T79 FT93


18 6
19
FT94
7
2T84 E4 FT68 D3
IT75 +5V
20 LED-1 3T78 100p 8 2T85 F5 FT69 E3
21
FC83 1T86
FT82
22 100R 2T80 2T86 C7 FT70 A5

2T81
100n
+24V 23
T 2.0A 63V 24 100p
2T87 D7 FT71 A4
25
KEYBOARD
FT95 3T79 2T88 D7 FT72 A5
10R 100p 2T89 D7 FT73 A4
FH12-25S-0.5SH(55)
2T90 E7 FT74 A4
2T82
FT50 3T84 2T91 F7 FT75 A5
C SDA-BL
100R
C 2T92 F7 FT76 B4

2T86

10p
3T70 B2 FT77 B5
3T71 E7 FT78 B4
1M09 FT51 3T85
SCL-BL 3T74 A6 FT79 B4
1 100R
3T75 A7 FT80 B5

2T87
2

10p
+24V
3
4
3T76 A7 FT81 B5
6 5 3T77 B7 FT82 B5
* HOTEL TV 502382-0470
BL-SPI-CLK
3T86

100R
3T78 B7 FT87 A7
D D

2T88
3T79 C7 FT88 B9

10p
+3V3 * 3T90
RES
1F53 3T80 D4 FT89 B9
10K
FAN-CTRL1 * 3T91

100R
RES
BL-SPI-SDO 8
3T88-1
1
FT52 1
2 3T81 E4 FT90 B9
FT68 3T80 100R FT53 3 3T82 E4 FT91 B9

2T89
FT54 4

10p
TACH01
100R
FT55 5 3T83 E4 FT92 B9
1M71 6
SCL-BL
RES 3T81 FT96 FT56 7
3T84 C7 FT93 B9
1
FT69 3T82 100R FT97 2 3T88-2 FT57
8 3T85 C7 FT94 B9
TACH02 FT98 BL-SPI-SDI 2 7 9
3
100R 4 100R 10 3T86 D7 FT95 C7

2T90
FT58 11

10p
RES 3T83 3T87 F7 FT96 E4
E E
2T83

2T84
100p

100p

SDA-BL 1735446-4 12
100R FT60 13 3T88-1 D7 FT97 E4
TEMPERATURE FT61 14
FAN-CTRL2 * 3T92
RES BACKLIGHT-PWM-ANA-DISP
3T71
FT64 15 16 3T88-2 E7 FT98 E5
100R SENSOR 100R 3T88-4 F7 FT99 F5
* 3T93

9T50
+3V3 RES 502386-1470
10K 3T90 D3 IT73 A7
FAN-DRV FT99
3T91 D4 IT74 B7
3T88-4
4 5
5T54 BL-SPI-CSn 3T92 E4 IT75 B7
2T85

1u0

+3V3 100R
3T93 E3 IT78 F4

2T91

10p
30R RES
5T53 F3
T 1.0A 63V

F F
1T85

FT59 3T87 1X03


BACKLIGHT-PWM_BL-VS REF EMC HOLE
5T53 100R

2T92
IT78

10p
+12V
30R RES

1 2 3 4 5 6 7 8 9
2 2009-10-22

Non DVBS
8204 000 8981
CONNECTOR BOARD

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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 151

10-23 B11 820400090693 TCON LGD


TCON Controller

TCON Controller
B11A B11A
1 2 3 4 5 6 7 8 9 10 11 12 13
1J01 C3 3J41 G9
1J02 G8 3J42 G9
1J99 A13 3J43 H9
FROM PNX8550 7J01-2
TL2429MC
2J01 A1 3J44 H9
LVDS 2J02 A1 3J45 H9
VCORE 3J07 100R 1% PX1A- PX1A- FJ01 3
PX1A+ PX1A+ FJ02 4
M
RA1 2J03 A1 3J46 H9
P
A 3J08 100R 1% PX1B- PX1B- FJ03 5
M
A 2J04 A1 3J47 H5
PX1B+ PX1B+ FJ04 6
P
RB1 2J05 A1 7J01-1 C4
RES 2J0A

RES 2J0E
100n

100n

100n

100n

100n
2J01

2J02

2J03

2J04

2J05

2J06
1u0

1u0

1u0
3J09 100R 1% PX1C- PX1C- FJ05 7 +VDISP 2J06 A1 7J01-2 A10
M
PX1C+ PX1C+ FJ06 8
P
RC1 1J99
2J07 B1 7J01-3 C1
1
3J10 100R 1% PX1D- PX1D- FJ07 11
M 2 2J08 B1 7J01-4 G1
PX1D+ PX1D+ FJ08 12 RD1
P 3 2J09 B1 7J02 G5
4
VCC 3J11 100R 1% FJ09 13
PX1E- PX1E-
FJ10 14
M
RE1
PX1A- 5 2J0A A2 7J03 G3
PX1E+ PX1E+ P 6
PX1A+ 7 2J0B B3 9J01 C1
3J12 100R 1% PX1CLK- PX1CLK- FJ11 9
PX1CLK+ PX1CLK+ FJ12 10
M
RCLK1 108 LMLV5N PX1B-
8 2J0C B3 9J02 C1
P + 9

RES 2J0C

RES 2J0D
RES 2J0B
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
2J07

2J08

2J09

2J10

2J11

2J12

2J13

2J14

2J15

2J16

2J17

2J18

2J19
LLV0 107
2J0D B4 9J03 E4
1u0

1u0

1u0

1u0

1u0

1u0
- LMLV5P 10
B 3J13 100R 1% PX2A- PX2A- FJ13 17
M +
105 LMLV4N
PX1B+ 11
12
B 2J0E A2 9J04 G6
PX2A+ PX2A+ FJ14 18 RA2 LLV1 104 LMLV4P PX1C-
P - 13
14
2J0F E6 FJ01 A9
3J14 100R 1% FJ15 19 103
PX2B-
PX2B+
PX2B-
PX2B+ FJ16 20 M
RB2 LLV2
+
102
LMLV3N
LMLV3P
PX1C+ 15 2J10 B1 FJ02 A9
P - 16
VCC ML_VDD ML_VDD PX1CLK- 17 2J11 B1 FJ03 A9
3J15 100R 1% PX2C- PX2C- FJ17 21 100 LMCLKN
PX2C+ PX2C+ FJ18 22
M
RC2 LLV3
+
-
99 LMCLKP PX1CLK+
18
19
2J12 B1 FJ04 A9
RES 9J01 FJ49 P
3J16 100R 1% PX2D- PX2D- FJ19 25 98 LMLV2N PX1D-
20 2J13 B2 FJ05 A9
M + 21
VCORE PX2D+ PX2D+ FJ20 26
P
RD2 LLV4
-
97 LMLV2P 22 2J14 B2 FJ06 A9
100n

100n

100n
2J20

2J21

2J22

2J23

2J24
1u0

1u0

PX1D+
9J02 3J17 100R 1% PX2E- PX2E- FJ21 27
+
95 LMLV1N
23
24
2J15 B2 FJ07 A9
M
C PX2E+ PX2E+ FJ22 28
P
RE2 LLV5
-
94 LMLV1P PX1E- 25
26
C 2J16 B2 FJ08 A9
3J18 100R 1% PX2CLK- PX2CLK- FJ23 23
M +
93 LMLV0N PX1E+ 27 2J17 B3 FJ09 B9
7J01-3 7J01-1 PX2CLK+ PX2CLK+ FJ24 24 RCLK2 LLV6 92 LMLV0P
TL2429MC
2J33
TL2429MC P -
PX2A-
28
29
2J18 B3 FJ0A D3
VCC
10M

POWER 15p TCON 30 2J19 B3 FJ0B D3


1J01

3J01

1M0

133 64 DPM 3J19 100R 1% PX3A- PX3A- FJ25 31 127 RMLV5N PX2A+
XIN DPM M + 31
62 3V3 136
2J34 PX3A+ PX3A+ FJ26 32
P
RA3 RLV0
-
126 RMLV5P 32 2J20 C1 FJ0C E3
88 144 134 66 GVST PX2B-
XOUT VST|GSP 33
135 147
15p GCLK1|GSP_R
73 GCLK1 3J20 100R 1% PX3B- PX3B- FJ27 33
M +
124 RMLV4N 34
2J21 C2 FJ0D E3
143 152 RESET FJ0A 60 74 GCLK2 PX3B+ PX3B+ FJ28 34 RB3 RLV1 123 RMLV4P PX2B+
148
SDGND
161
RESET GCLK2
75 GCLK3
P - 35 2J22 C2 FJ0E E3
SDVDD GCLK3 36
156 168 DISM FJ0B 166
DISM GCLK4
76 GCLK4 3J21 100R 1% PX3CLK- PX3C- FJ29 35
M +
121 RMLV3N PX2C- 37 2J23 C2 FJ0F E3
160 174 81 GCLK5 PX3CLK+ PX3C+ FJ30 36 RC3 RLV2 120 RMLV3P
GCLK5 P - 38
D 167 BIT_SEL 172
BIT_SEL GCLK6
82 GCLK6 PX2C+ 39 D 2J24 C3 FJ0G E3
173 65 FLK 3J22 100R 1% PX3C- PX3D- FJ31 39 119 RMCLKN
130
FLK1
PX3C+ PX3D+ FJ32 40
M
RD3 RLV3
+
118 RMCLKP PX2CLK-
40 2J25 H4 FJ0H G4
TESTA POL_A P - 41
71
79
63
72
NC 131
TESTB POL
137
3J23 100R 1% FJ33 41 116
42 2J26 H3 FJ10 B9
PX3D- PX3E- M + RMLV2N PX2CLK+ 43
139
IOVDD
80 OPC_EN 171
OPC_EN SOE
138 SOE_A PX3D+ PX3E+ FJ34 42
P
RE3 RLV4
-
115 RMLV2P 44
2J28 G5 FJ11 B9
151 IOGND 140 VCC PX2D-
169 157 REVERSE FJ0C 165 89 3J03 3J24 100R 1% PX3E- PX3CLK- FJ35 37 114 RMLV1N
45 2J31 H6 FJ12 B9
REVERSE R_MLVDS M + 46

33K 1%
170 15K 1% PX3E+ PX3CLK+ FJ36 38
P
RCLK3 RLV5
-
113 RMLV1P PX2D+ 47 2J32 H7 FJ13 B9

3J02
GIP_EN FJ0D 132 154
GIP_EN PWM_TOUT|WPWM NC 48
83
PLLVDD PLLGND
84
PWM_TIN
153
+
111 RMLV0N PX2E- 49
2J33 C3 FJ14 B9
ODC_BYPASS FJ0E 150 3J25 100R 1% PX4A- PX4A- FJ37 45 RLV6 110 RMLV0P
16 15
ODC_BYPASS
162 PX4A+ PX4A+ FJ38 46
M
RA4
-
PX2E+
50 2J34 D3 FJ15 B9
EEP_SIZE LEDON NC P 51
30 29 FJ0F 87
EEP_SIZE 52 3J01 C4 FJ16 B9
E E

RES 2J0F
44 LVDD LGND 43 155 3J26 100R 1% FJ39 47

15p
SCAN_BLK|REFMODE PX4B- PX4B- M PX3A- 53
58 57 SCL-TCON 176
SCL SCAN_BLK2
163 NC PX4B+ PX4B+ FJ40 48
P
RB4
54
3J02 E6 FJ17 C9
ML_VDD SDA-TCON 175 PX3A+
91 1V8 90 I2C_EN FJ0G 149
SDA
142 3J27 100R 1% PX4CLK- PX4C- FJ41 49
55 3J03 D6 FJ18 C9
I2C_EN H_CONV H_CONV M 56
101
109
96
106
WP RES 9J03 164
WP
68 GVDD_EVEN
PX4CLK+ PX4C+ FJ42 50
P
RC4 PX3B- 57 3J04 G7 FJ19 C9
MLVDD MLVSS VDD_EVEN|GOE 58
117 112
OPT_N
141 OPT_N 3J28 100R 1% PX4C- PX4D- FJ43 53
M PX3B+ 59 3J06 G7 FJ20 C9
125 122 67 GVDD_ODD PX4C+ PX4D+ FJ44 54 RD4
VCORE
VDD_ODD|GSC P
PX3C-
60 3J07 A8 FJ21 C9
61
2 1 3J29 100R 1% FJ45 55
59 61
PX4D-
PX4D+
PX4E-
PX4E+ FJ46 56
M
RE4 PX3C+
62 3J08 A8 FJ22 C9
P 63
69 70
64 3J09 A8 FJ23 C9
77 78 3J30 100R 1% PX4E- PX4CLK- FJ47 51 PX3CLK-
85 CVDD CGND 86 PX4E+ PX4CLK+ FJ48 52
M
RCLK4
65 3J10 A8 FJ24 C9
P 66
F 128
145
129
146
PX3CLK+ 67
68
F 3J11 B8 FJ25 C9
158 159 PX3D- 69 3J12 B8 FJ26 D9
GND_HS
177 PX3D+
70
71
3J13 B8 FJ27 D9
PX3E-
72 3J14 B8 FJ28 D9
73
74 3J15 C8 FJ29 D9
LDO BLOCK E2PROM VCC +VDISP ASIC OPTION PX3E+
7J01-4
75
76
3J16 C8 FJ30 D9
TL2429MC VCC PX4A- 77 3J17 C8 FJ31 D9
VIA36 RES 3J39 78
3J18 C8 FJ32 D9
100n
2J28

3J04

178 196 GIP_EN


47K

PX4A+ 79
179 197 1K0 80 3J19 C8 FJ33 D9
G 180
181
198
199 7J03
VCORE 9J04 WP SCL-TCON 1
1J02
RES 3J40 EEP_SIZE
PX4B- 81
82
G 3J20 D8 FJ34 D9
182 200 VCC LD1117ADT18 7J02 SDA-TCON 2 1K0 PX4B+ 83
183 201 M24C32-WDW6 3 3J21 D8 FJ35 E9
8

FJ0H 3J41 84
Φ I2C_EN
3J06

184 202 3 2 VCC


18K

WP 4 PX4C-
185 203
IN OUT
5 1K0
85
86
3J22 D8 FJ36 E9
186 204 COM (4Kx8) 7 7 6 PX4C+
VIA VIA WC RES 3J42 87 3J23 D8 FJ37 E9
2J26

2J25

187 205 EEPROM ODC_BYPASS


10u

10u

FJ4A 88
3J24 E8
3J35

3J36

188 206 1 6 BM05B-SRSS-TBT FJ38 E9


4K7

4K7

PX4CLK-
1

0 SCL 1K0 89
189 207 2
ADR
190 208 3
1
2 SDA
5
3J37
3J43 REVERSE PX4CLK+
90
91
3J25 E8 FJ39 E9
191 209 SCL-TCON 1K0 92 3J26 E8 FJ40 E9
4

192 210 100R PX4D-


RES 3J44 93
100R

3J27 E8
3J47

DISM
193 211
3J38 94 FJ41 E9
H 194
195
212
213 100R
SDA-TCON 1K0
RES 3J45
PX4D+ 95
96
H 3J28 E8 FJ42 E9
OPC_EN PX4E-
97 3J29 F8 FJ43 E9
RES 2J31

RES 2J32
15p

15p

1K0 98
RES 3J46 BIT_SEL
PX4E+ 99 3J30 F8 FJ44 F9
100
1K0
3J35 H6 FJ45 F9
DF18C-100DP-0.5V (51)
3J36 H7 FJ46 F9
3J37 H6 FJ47 F9
3J38 H6 FJ48 F9
3J39 G9 FJ49 C1
3J40 G9 FJ4A H5
1 2 3 4 5 6 7 8 9 10 11 12 13
3 2009-11-12

TCON LGD 2 2009-10-26

8204 000 9069

18770_547_100119.eps
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2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 152

TCON DC/DC

TCON DC/DC
B11B B11B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1JG1 A2 3JE2 C13
1JG2 B2 3JE3 C13
2JD0 F2 3JE4 C14
2JD1 F4 3JE5 B11
2JD2 G4 3JE6 D13
2JD3 F6 3JE7 B8
A A 2JD4 H3 3JE8 C7
DISPLAY INTERFACING - VDISP
1JG1 POWER BLOCK +VDISP +VDISP 2JE0 C12 3JE9 C7
5JF0 6JF0 2JE1 C12 3JEA B8
T 3.0A 32V
22u B340A 2JE2 C13 3JEB E14

1u0
10u
10u
RES 5JG1 RES 1JG2 FJG1 2JE3 C13 3JEC E13

2JEQ
2JER

RES 2JEN
RES 2JEP
2JF6

2JF5

2JF4

2JF3

RES 2JF2

RES 2JF1

RES 2JF0
10u

10u

10u

10u

10u

10u

10u

10u

10u

10u

10u
+VDISP-INT +VDISP
30R T 3.0A 32V 2JE4 C13 3JED E13

2JEK
2JEL

2JEJ
RES 5JG2 FOR DEBUG ONLY
2JE5 C13 3JEE E13
RES 2JG1

2JG2

100n
22u

3JG1 6JG1
VCC
30R
+VDISP
2JEM 3JE5 2JE6 C13 3JEF D9
2K2 LTST-C190KGKT FJG2 5JF1 2JEY 2JE7 C14 3JEG F13
B B

10R 1%
1n0 2R2
2JE8 C14 3JEH F12

5K1 1%

100n
150p
22u 100n

10u
10u
10u
10u
10u
6JE1

3JE7
2JE9 C14 3JEJ D9

B340A

22
23

30
31

32
33
3JEA

6JF1
EN2
7JF1 2JEA C14 3JEK E9

RES 2JFD
RES 2JFC
RES 2JFB
2JFA
2JF9
RES 2JF8
2JF7
HVDD BLOCK +VDISP MAX17113ETL BAV99 COL
VDD 2JEB C14 3JEL E8

IN2_1
IN2_2

PGND1
PGND2

LX1_1
LX1_2
1K0 1%
18
BST SWI
34
FJG3 2JEE C12 3JEN E8

2JEW
3JE8

100n
10R 1%

19 2JEF C12 3JEP F8

150K 1%

150K 1%

100n
1u0
1u0

9K1 1%
LX2_1

10u
10u
10u
10u

10u
10u
10u
2JH0

2JH1

3JH0

2JH2

RES 2JE0

RES 3JE1

3JE0
20 35 2JFP 1u0 2JEG D13 3JER C9
10u

10u

1u0

10u
LX2_2 SWO

3JE4
RES 2JFT 100n RES 3JER 1R0
3 2JFR 100n 2JEH D11 3JET C11

RES 2JEA
RES 2JEB
1K0 1%

RES 2JE2
RES 2JE3
2JE4

2JE5
2JE6
2JE7
2JE8

RES 2JE9
RES 2JH8 GND2
9JE6
FB1
36 2JEJ B12 3JEU E7

RES 3JE9
21 37 3JET 10K 2JEF 1n5
C C

15K 1%

75K 1%
7JH1
1u0 H_VDD 17
OUT COMP 2JEK B12 3JEW E8
FB2

RES 2JE1

3JE3

3JE2
TPS62110RSA RES 2JEE 1n5 2JEL B12 3JG1 B3

10u
2
3

180K 1%

150K 1%

22p
10u
10u
1u0
VIN Φ VINA 24
VIN AGND2
40
2JEM B11 3JH0 C3
5JH1

3JH4

RES 3JH5
6u8

2JH3 FJE1
STEP-DOWN VL THR
1 VDD_FB
2JEN B11 3JH1 D1
2JH4
2JH5
2JH6
2JH7
1u0
CONVERTER 2JEU 1u0 28
VL CTL
11
14 25 6 VCC 2JEP B11 3JH2 D1
RES 3JH1 FSEL DRN
DPM 7 2JEQ B10 3JH3 D1
SW NC MODE
47K 1% 4 15 REF 15 5
EN REF GON 2JER B10 3JH4 C3

3JE6
+VDISP

10K
FJH1
7 10 HVDD_FB
2JET D9 3JH5 C3

360R 1%
LBI FB
13
56K 1%

75K 1%

AGND1
2JEU C9 3JH6 D3

3JEF
VDD +VDISP 5 13 38 RESET
SYNC PG 2JET PGOOD
3JH6

3JH7

27 39 2JEH 150p 3JH7 D3


2JEW C7
D DEL2 CRST
D
47K 1%

6 6JE2
LBO 100n
2JEY B9 3JH8 E14

2JEG
3JHA

3JH2

20K

1u0
EN2

360R 1%
2JEZ
18 16 4
DEL1 SRC 2JEZ D9 3JH9 E13

RES 3JEJ
19 BAV99 COL
100n
VIA 20 EN2 2JF0 B10 3JHA D1
9K1 1%

21 EN1 26 2
EN1 DRVP VGH 2JF1 B10 3JHB D1
3JHB

3JH3

cJD1
7K5

68K 1%
PGND GND AGND GND_HS 3JEU 29 2JF2 B9 5JF0 A11
DPM EN2

3JH9

3JEC

RES 3JEB
2JFE

3JH8
9JE4
2JFF

10K
1
16

11
12

17

8 42

9K1

9K1
1u0

4u7
100R 2JF3 B9 5JF1 B9

1K0 1%
NC DLP VIA1

3JEW
43
VIA2 RES 2JFG
44 2JF4 B9 5JG1 A2

RES
-T
GND_HS
2JFJ VIA3

CPGND

BAV99 COL
12 45
2JF5 B9 5JG2 B2

RES 6JF2
6JF4 DRVN VIA4 470n

FBN
9JE7 VCC

FBP

150K 1%
100n
BAV99 COL 2JF6 B9 5JH1 C3
E E

3JED
VGL 9JE3 9JE5
2JF7 B9 6JD0 F4

3K6 1%
FJD1 RES 3JEK 2JF8 B8 6JD1 F6

14

41

10
LEVEL SHIFTER BLOCK VGH

9
FJE2

3JEN

2JFL
2JFK 1u0 VGH_FB

10u
6JE1 B13
10R 1%

10R 1%

360R 1%

10R 1%

10R 1%

VCC
1R0 2JF9 B8

27K 1% 150K 1%

10K 1%
RES 3JD5

2JFA B8 6JE2 D13


3JD2

3JD3

3JD6

3JD7

3JEL

3JEE
VDD
2JFB B8 6JF0 A12
4K7 1%

RES 2JFH
6JD0 FJE3
2JFC B8 6JF1 B9

2JFN
3JD1

VGL_FB

BAV99 COL
VDD

1u0
6JF3
470n
BZX384-C9V1 RES 6JD1 2JFD B8 6JF2 E12

3JEP
RES
2JFE E13 6JF3 F12
2JD1

3JD0 10R 1% FLK_IN


1u0

FLK BZX384-C9V1
2JFF E13 6JF4 E9
2JD3

1u0

REF
F F

100R 1%

100R 1%
2JFG E12 6JG1 B4
RES 2JD0

100n

7JD1

2JFM

3JEG
3JEH
220n
MAX17119 VDD
2JFH F12 7JD1 F5
GCLK6_1 9
1 1
13 CLK6 2JFJ E9 7JF1 B10
GCLK5_1 8 14 CLK5
VGL 9JD0 VGI_P GCLK4_1 7
2 2
15 CLK4 VGL_FB VGH_FB 2JFK E9 7JH1 C2
3 3
GCLK3_1 6
4 4
16 CLK3 2JFL E8 9JD0 F2
VGH RES 9JD1 GCLK2_1 5 17 CLK2
GCLK1_1 4
5 A Y 5
18 CLK1
2JFM F8 9JD1 G2
6 6
GVST_1 3
7 7
19 VST 2JFN F13 9JD2 G2
VGL RES 9JD2 VGI_N GVDD_EVEN_1 2 20 VDD_EVEN
GVDD_ODD_1 1
8 8
21 VDD_ODD 2JFP C12 9JD3 G2
9 9
VGH 9JD3 2JFR C12 9JD4 G2
28 22 DI_SCHG
G RES 9JD4
VSENSE YDCHG
G 2JFT C8 9JD5 G2
VGL VGL_1 VCC 10
1 1
25 ITEM NO 32 INCH 37 INCH 42 INCH 2JG1 B1 9JD6 H2
12 GON 26 3JE0 143K 137K 150K
DI_SCHG RES 9JD5 11
2 FLK 2
27 FLK_IN 3JED 174K 196K 150K 2JG2 B3 9JD7 H2
100R 1%

GOFF 3
3J EC 33K 68K 6 8K 2JH0 C2 9JD8 H2
3JEP 51K 18K 27K
3JD8

2JD2

24 34
1u0

RE
35 3JEL 270K 140K 150K 2JH1 C2 9JD9 H2
GVST 9JD6 GVST_1 30 36 3JH4 180K 390K 180K 2JH2 C3 9JDA H2
VIA
31 37 3JH5 RES 330K RES
GVDD_ODD 9JD7 GVDD_ODD_1 32 VIA 38 3JH6 47K 56K 56K 2JH3 C1 9JDB H2
3K0 1%

33 3JH7 82K 75K 75K 2JH4 C4 9JDC H2


10K 1%
3JDA
RES 2JD4

3JD9

GVDD_EVEN 9JD8 GVDD_EVEN_1


10u

GND VGL_HS 2JH5 C4 9JDD I2


GCLK6_1 2JH6 C4 9JDE I2
23

29

GCLK6 9JD9
H 9JDA GCLK5_1 3JD4 FJD2 H 2JH7 C4 9JE3 E8
GCLK5 VGL
10R 1% 2JH8 C2 9JE4 E13
GCLK4 9JDB GCLK4_1
3JD0 F2 9JE5 E9
GCLK3 9JDC GCLK3_1 3JD1 F2 9JE6 C9
GCLK2 9JDD GCLK2_1 3JD2 E4 9JE7 E8
3JD3 E5 FJD1 E6
GCLK1 9JDE GCLK1_1
3JD4 H6 FJD2 H6
3JD5 E5 FJE1 C14
3JD6 E5 FJE2 E14
I I 3JD7 E5 FJE3 F7
3JD8 G4 FJG1 B3
3JD9 H4 FJG2 B8
3JDA H4 FJG3 C13
3JE0 C13 FJH1 D4
3JE1 C13 cJD1 D3
1 2 3 4 5 6 7 8 9 10 11 12 13 14

3 2009-11-12

TCON LGD 2 2009-10-26

8204 000 9069

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2010-Feb-19 back to
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Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 153

Mini LVDS

Mini LVDS
B11C B11C
1 2 3 4 5 6 7 8 9 10 11 12
1JA1 G1 FJAG D2
1JA2 G3 FJAH D1
1JB1 E5 FJAJ D1
2JA0 B1 FJAK D1
A A 2JA1 B1 FJAL D1
2JA2 B1 FJAM D1
2JA3 B2 FJAN E1
VDD VCC VDD VCC 2JA4 B3 FJAP E1
PGMA BLOCK GPIO 2JA5 B3 FJAR E1
VCC VDD 2JA6 B4 FJAT E1
2JA0

2JA1

2JA2

2JA3

2JA4

2JA5

2JA6

2JA7
100n

100n

100n

100n
10u

10n

10u

10n
2JA7 B4 FJAU E1
B B 2JA8 D2 FJAW E1

2JC0

3JC0

3JC1
100n

20R

20R
FJA0 FJBL
VCC 2JA9 E4 FJAY E1
62 61 62 61 P_VDD
FJCJ 2JAA G2 FJAZ E1
60 60
Z_OUT
59
FJA1
59 GMA1 2JAB H2 FJB1 E1

10K

10K
FJA2 CLK1 GMA3
58 58
2JC0 B6 FJB2 E1

2JC1

2JC2

2JC3
100n

100n
FJA3 RES 9JBF

10u
57 CLK2 57 GMA4 7JC1 BYPASS_MODE CTRL-DISP

3JC5

3JC6
FJA4 CLK3 GMA6 MAX9668ETP
56 56
55
FJA5 CLK4 55 GMA7 2JC1 C7 FJB3 E1

16
FJA6 CLK5 GMA9

7
54 54
53
FJA7 CLK6
VGI_N
53 GMA10
VCOM_SDA
DVDD AVDD AMP
AVDD
2JC2 C8 FJB4 E1
FJA8 GMA12 1 10 GMA3
52 52 SDA 1
51
FJA9 VGI_P
51 GMA13 VCOM_SCL 20
SCL 2
11 GMA4 2JC3 C8 FJB5 E1
C 50
FJAA
FJAB
VDD_ODD
VDD_EVEN
50 GMA15
GMA16
2
A0 3
12
13
GMA6
GMA7
C 2JC4 C6 FJB6 F1
49 49

15p

15p
VGL_1 4
FJAC GMA18 22 GMA 14 GMA12
48
47
FJAD VST
48
47
23
5
6
15 GMA13
3JC4
2JC5 C6 FJB7 F1
OPT_N 24 18 GMA15 VCOM_FBO
46 46 7 3JA1 G2 FJB8 F1

RES 2JC4

RES 2JC5
FJAE VCOMLFB H_CONV_1 25 19 GMA16
45 45 8 1K0 1%
FJAF VCOML GVST_1 26
44
43
44
43 POL-TCON 27
VIA
5 VCOM VCOM 9JC0 3JB1 F6 FJB9 F1
VCOM VCOM_FBO
28 6
42 42 SOE
29
VCOM_FB 3JC0 B7 FJBA F1
41 41 3JC2
H_VDD
40
FJAG
2JA8 10u
40
FJBM
FJBN
RMLV5N
RMLV5P
30
NC
9
17
VCOMLFB VCOML 9JC1
3JC1 B7 FJBB F1
39 39 150R 1%
38 38
FJBP
FJBR
RMLV4N
RMLV4P
GND
HS
AGND
AMP RES 3JC3
VCOMRFB VCOMR 9JC2
3JC2 D8 FJBC F1
37 37
D D 3JC3 D8 FJBD F1

21

4
FJBT RMLV3N 1K0 1%
36 36
FJBU RMLV3P
35 35
34
FJAH
FJAJ
LMLV5N 34
FJBW
FJBY
RMCLKN 3JC4 C9 FJBE F1
33 LMLV5P 33 RMCLKP
32
FJAK LMLV4N 32
FJBZ RMLV2N 3JC5 C6 FJBF F1
FJAL LMLV4P FJC0 RMLV2P
31
30
FJAM LMLV3N
31
30
FJC1 RMLV1N 3JC6 C6 FJBG F1
FJAN LMLV3P FJC2 RMLV1P
29 29
7JB1 G6 FJBH F1
28
FJAP
FJAR
LMCLKN
LMCLKP
28
FJC3
FJC4
RMLV0N
RMLV0P I2C SWITCH (VGA VCOM) I2C SWITCH (SSB-NVM)
27
26
FJAT LMLV2N
27
26
7JB3 H6 FJBJ F1
FJAU LMLV2P
25
24
FJAW LMLV1N
25
24
7JC1 C6 FJBK G1
FJAY
23 LMLV1P 23 FJCK 9JA1 H2 FJBL B3
E 22
FJAZ LMLV0N 22
H_VDD SCL-DISP RES 9JBA SCL-TCON E
21
FJB1 LMLV0P 21
2JA9 10u
9JA2 H2 FJBM D4
20 20 FJCL
19
FJB2
FJB3
SOE
POL-TCON
19
1JB1
1 FJC9 VCOM_SDA VCOM_SDA 9JB6 SDA-DISP
SDA-DISP RES 9JBB SDA-TCON 9JB3 F6 FJBN D4
18 18
17
FJB4
FJB5
GVST_1
H_CONV_1
17
FJC5
FJC6
VCOMR
VCOMRFB
2
3
FJCA VCOM_SCL VCOM_SCL 9JB7 SCL-DISP 9JB5 F6 FJBP D4
16 16 FJCG
15
FJB6 OPT_N
15
4
5 RES 9JB3
WP 9JB6 E8 FJBR D4
14 14 VST
13
FJB7 GMA18 13
VGL_1
VDD_EVEN
6 9JB7 E8 FJBT D4
FJB8 GMA16 7 8 VCC
12 12
11
FJB9 GMA15 11
VDD_ODD 9JBA E10 FJBU D4
FJBA GMA13 VGI_P 502382-0670
10
FJBB
10
VGI_N 3JB1 9JBB E10 FJBW D4
10K
9 GMA12 9
F 8
7
FJBC
FJBD
GMA10
GMA9
8
7
CLK6
CLK5 FJCB BYPASS_MODE
F 9JBF C11 FJBY D4
FJBE GMA7 CLK4
6
5
FJBF GMA6
6
5 CLK3 9JC0 D9 FJBZ D4
RES 9JB5

FJBG
4
FJBH
GMA4
GMA3
4 CLK2
CLK1
9JC1 D9 FJC0 D4
3 3
FJBJ Z_OUT
2 GMA1 2 9JC2 D9 FJC1 D4
1 FJBK 1 FJC8
1JA1 1JA2
FJA0 B1 FJC2 E4
196119-60041 196119-60041
VCC
FJA1 B2 FJC3 E4
RES
FJA2 B2 FJC4 E4
G POL_A 3JA1
POL-TCON
7JB1
BSH111 G FJA3 C2 FJC5 E4
10R FJA4 C2 FJC6 E4
2JAA

VCOM_SDA
15p

VGA-SDA-EDID-TCON
FJCC
FJA5 C2 FJC8 G3
VCC FJA6 C2 FJC9 E6
SOE_A 9JA1 SOE
RES FJA7 C2 FJCA E6
2JAB

7JB3
15p

BSH111 FJA8 C2 FJCB F6


VGA-SCL-EDID-TCON VCOM_SCL FJA9 C2 FJCC G6
H_CONV H_CONV_1
9JA2
FJCE FJAA C2 FJCE H6
H H FJAB C2 FJCG E7
FJAC C2 FJCJ B8
FJAD C2 FJCK E11
FJAE C2 FJCL E11
FJAF C2
1 2 3 4 5 6 7 8 9 10 11 12

3 2009-11-12

TCON LGD 2 2009-10-26

8204 000 9069

18770_549_100119.eps
100119

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 154

Connectors

Connectors
B11D B11D
1 2 3 4 5 6 7 8 9
+3V3 1F53 D8 FJ89 B8
1J85 D2 FJ90 B8
1M20 B8 FJ91 B8
1M71 C1 FJ92 B8

100K
3J74
1P12 B3 FJ93 B8
3J75 1X03 E8 FJ94 B8
A Dummy testlands for common jig LIGHT-SENSOR
100R
A 1X05 E8 FJ96 D1

100p
2J76
1X08 E9 FJ97 D1
FJZA FJZL FJZY FJYJ FJY2 FJYR
FJZB FJZM FJZZ FJYK FJY3 FJYT 2J76 A7 FJ98 D1
FJZC FJZN FJYA FJYL FJY4 FJYU
3J76
2J77 B7 FJ99 D1
FJZD FJZP FJYB FJYM FJY5 FJYW RC 2J78 B7
FJZE FJZQ FJYC FJYN FJY6 FJY7
FJY1 B1
100R LED PANEL 2J79 B8 FJY2 A2

100p
RES 2J95

2J77
FJZF FJZR FJYD FJYP FJY9 FJY8

47n
FJZG FJZT FJYE FJYQ FJZ1 1M20 2J80 C7 FJY3 A2
FJZH FJZU FJYF FJYV FJZ2 FJ88
1 2J81 B8 FJY4 A2
FJZJ FJZV FJYG FJYZ FJ89
2 2J82 C7
FJZK FJZW FJYH FJY1
3J77
FJ90
3
FJY5 A2
LED-2 FJ91
4 2J83 D1 FJY6 B2
B 100R +3V3-STANDBY FJ92
5 B 2J84 D1 FJY7 B3

100p
2J78
FJ93
6 2J85 D1
FJ94
7
FJY8 B3
FJ5A LIGHT STRIP +5V FJ51
8 2J86 D7 FJY9 B2
FJ5B 1P12
FJ5C
FJ50 3J89
LED-1 LED-1
3J78
2041145-8 2J87 D7 FJYA A1
1
2J88 D7 FJYB A1

100p

100n
2J79

2J81
FJ5D 100R
2 +5V 100R

100p
2J80
FJ5F 2J89 E7
3 FJYC B1

100n
2J93
4 2J90 E7 FJYD B1

100p
2J94
5 6
3J79
2J91 F7 FJYE B1
502382-0470 KEYBOARD 2J92 F7 FJYF B1
10R
2J93 C3 FJYG B1

100p
2J82
C C 2J94 C4
2J95 B6
FJYH B1
FJYJ A1
3J74 A6 FJYK A1
TEMPERATURE 3J75 A6
3J84 FJYL A1
SENSOR 3J80 100R TACH01 SDA-BL
1M71 3J76 A6 FJYM A1
100R
RES 3J81 3J77 B6 FJYN B1

2J86
FJ96 100R

10p
1 SCL-BL
FJ98 2D DIMMING 3J78 B6
2 3J82 100R 1F53
FJYP B1
FJ97 TACH02
3
FJ99 3J79 C6 FJYQ B1
4 RES 3J83 3J85 1
100R SDA-BL SCL-BL FJ52
2
3J80 C2 FJYR A3
100p

100p
2J84

2J83

2041145-4 FJ53
100R 3 3J81 C2 FJYT A3

2J87
FJ54

10p
4 3J82 D2 FJYU A3
D FJ55
5
6
D 3J83 D2 FJYV B1
FJ56
1J85 3J86 7 3J84 C6 FJYW A3
FAN-DRV BL-SPI-CLK 8
5J54 FJ57 3J85 D6 FJYZ B1
T 1.0A 63V RES 100R 9

100p
2J88
+3V3 10 3J86 D6 FJZ1 B3
2J85

FJ58
1u0

30R 11 3J87 F6 FJZ2 B3


5J53 12
RES
+12V FJ60
13
3J88-1 E6 FJZA A1
3J88-2
BL-SPI-SDO 2 7 3J88-2 E6
30R
15 16
14 FJZB A1
100R 3J88-4 E6 FJZC A1

100p
2J89
502386-1470 3J89 B4 FJZD A1
5J53 E3 FJZE B1
E BL-SPI-SDI 4
3J88-4
5 E 5J54 D3 FJZF B1
100R FJ50 B3 FJZG B1

100p
2J90
OVAL SCREW HOLE FJ51 B8 FJZH B1
ROUND SCREW HOLE 4mm ROUND SCREW HOLE 4.5mm
1X03 1X05 1X08
FJ52 D8 FJZJ B1
3J88-1 REF EMC HOLE EMC HOLE EMC HOLE FJ53 D8 FJZK B1
BL-SPI-CSn 1 8
FJ54 D8 FJZL A1
100R
FJ55 D8 FJZM A1

100p
2J91
FJ56 D8 FJZN A1
FJ57 D8 FJZP A1
3J87
BACKLIGHT-PWM_BL-VS FJ58 D8 FJZQ B1
F 100R F FJ5A B1 FJZR B1

2J92

1n0
FJ5B B1 FJZT B1
FJ5C B1 FJZU B1
FJ5D B1 FJZV B1
FJ5F C1 FJZW B1
FJ60 E8 FJZY A1
FJ88 B8 FJZZ A1
1 2 3 4 5 6 7 8 9

3 2009-11-12

TCON LGD 2 2009-10-26

8204 000 9069

18770_550_100119.eps
100119

2010-Feb-19 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 155

10-24 B11 820400090704 TCON LGD


TCON Controller

TCON Controller
B11A B11A
1 2 3 4 5 6 7 8 9 10 11 12 13
1J01 C3 3J41 G9
1J02 G8 3J42 G9
1J99 A13 3J43 H9
2J01 A1 3J44 H9
7J01-2
FROM PNX8550 TL2429MC 2J02 A1 3J45 H9
VCORE 3J07 100R 1% PX1A- PX1A- FJ01 3 LVDS 2J03 A1 3J46 H9
M
PX1A+ PX1A+ FJ02 4
P
RA1 2J04 A1 3J47 H5
A 3J08 100R 1% PX1B- PX1B- FJ03 5
M
A 2J05 A1 7J01-1 C4
PX1B+ PX1B+ FJ04 6 RB1
P 2J06 A1 7J01-2 A10
RES 2J0A

RES 2J0E
100n

100n

100n

100n

100n
2J01

2J02

2J03

2J04

2J05

2J06
1u0

1u0

1u0
3J09 100R 1% PX1C- PX1C- FJ05
FJ06
7
8
M
RC1
+VDISP
1J99
2J07 B1 7J01-3 C1
PX1C+ PX1C+ P
1
2J08 B1 7J01-4 G1
3J10 100R 1% PX1D- PX1D- FJ07 11
PX1D+ PX1D+ FJ08 12
M
RD1
2 2J09 B1 7J02 G5
P 3
VCC 3J11 100R 1% FJ09 13
4 2J0A A2 7J03 G3
PX1E- PX1E- M PX1A- 5
PX1E+ PX1E+ FJ10 14
P
RE1
6
2J0B B3 9J01 C1
PX1A+
3J12 100R 1% PX1CLK- PX1CLK- FJ11 9
7 2J0C B3 9J02 C1
M 8
PX1CLK+ PX1CLK+ FJ12 10
P
RCLK1
+
108 LMLV5N PX1B- 9 2J0D B4 9J03 E4

RES 2J0C

RES 2J0D
RES 2J0B
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
2J07

2J08

2J09

2J10

2J11

2J12

2J13

2J14

2J15

2J16

2J17

2J18

2J19
LLV0 107
1u0

1u0

1u0

1u0

1u0

1u0
- LMLV5P 10
B PX1B+ 11 B 2J0E A2 9J04 G6
3J13 100R 1% PX2A- PX2A- FJ13 17 105 LMLV4N
PX2A+ PX2A+ FJ14 18 M
RA2 LLV1
+
104 LMLV4P PX1C-
12 2J0F E6 FJ01 A9
P - 13
3J14 100R 1% FJ15 19 103
14 2J10 B1 FJ02 A9
PX2B- PX2B- + LMLV3N PX1C+ 15
M
PX2B+ PX2B+ FJ16 20
P
RB2 LLV2
-
102 LMLV3P 16
2J11 B1 FJ03 A9
VCC ML_VDD ML_VDD PX1CLK-
3J15 100R 1% PX2C- PX2C- FJ17 21 100 LMCLKN
17 2J12 B1 FJ04 A9
M + 18
RES 9J01 FJ49
PX2C+ PX2C+ FJ18 22
P
RC2 LLV3
-
99 LMCLKP PX1CLK+ 19 2J13 B2 FJ05 A9
20
3J16 100R 1% PX2D- PX2D- FJ19 25
M +
98 LMLV2N PX1D- 21 2J14 B2 FJ06 A9
VCORE PX2D+ PX2D+ FJ20 26 RD2 LLV4 97 LMLV2P
P - 22 2J15 B2 FJ07 A9
100n

100n

100n
2J20

2J21

2J22

2J23

2J24
1u0

1u0

PX1D+ 23
9J02 3J17 100R 1% FJ21 27 95
PX2E- PX2E-
M + LMLV1N 24 2J16 B2 FJ08 A9
C PX2E+ PX2E+ FJ22 28
P
RE2 LLV5
-
94 LMLV1P PX1E- 25
26
C 2J17 B3 FJ09 B9
3J18 100R 1% PX2CLK- PX2CLK- FJ23 23 93 LMLV0N PX1E+
7J01-3 2J33 7J01-1 PX2CLK+ PX2CLK+ FJ24 24 M
RCLK2 LLV6
+
-
92 LMLV0P
27
28
2J18 B3 FJ0A D3
TL2429MC TL2429MC P
VCC
PX2A- 29 2J19 B3 FJ0B D3
10M

POWER 15p TCON 30


2J20 C1 FJ0C E3
1J01

3J01

1M0

133 64 DPM 3J19 100R 1% PX3A- PX3A- FJ25 31 127 RMLV5N PX2A+
XIN DPM M + 31
62 3V3 136 PX3A+ PX3A+ FJ26 32 RA3 RLV0 126 RMLV5P
88 144
2J34
134
XOUT VST|GSP
66 GVST
P -
PX2B-
32
33
2J21 C2 FJ0D E3
135 147 73 3J20 100R 1% FJ27 33 124
143 152 RESET
15p
FJ0A 60
GCLK1|GSP_R
74
GCLK1
GCLK2
PX3B-
PX3B+
PX3B-
PX3B+ FJ28 34
M
RB3 RLV1
+
123
RMLV4N
RMLV4P PX2B+
34 2J22 C2 FJ0E E3
SDGND RESET GCLK2 P - 35
148
SDVDD
161
GCLK3
75 GCLK3 36 2J23 C2 FJ0F E3
156 168 DISM FJ0B 166 76 GCLK4 3J21 100R 1% PX3CLK- PX3C- FJ29 35 121 RMLV3N PX2C-
160 174
DISM GCLK4
GCLK5
81 GCLK5 PX3CLK+ PX3C+ FJ30 36
M
P
RC3 RLV2
+
-
120 RMLV3P
37
38
2J24 C3 FJ0G E3
D 167
173
BIT_SEL 172
BIT_SEL GCLK6
FLK1
82
65
GCLK6
FLK 3J22 100R 1% PX3C- PX3D- FJ31 39
M +
119 RMCLKN
PX2C+ 39
40
D 2J25 H4 FJ0H G4
130
TESTA POL_A
PX3C+ PX3D+ FJ32 40
P
RD3 RLV3
-
118 RMCLKP PX2CLK- 41 2J26 H3 FJ10 B9
71 63 NC 131 137
79 72
TESTB POL
3J23 100R 1% PX3D- PX3E- FJ33 41
M +
116 RMLV2N PX2CLK+
42
43
2J28 G5 FJ11 B9
139 80 OPC_EN 171 138 SOE_A PX3D+ PX3E+ FJ34 42 RE3 RLV4 115 RMLV2P
151
IOVDD
IOGND 140
OPC_EN SOE
VCC
P -
PX2D-
44 2J31 H6 FJ12 B9
3J03 45
169 157 REVERSE FJ0C 165
REVERSE R_MLVDS
89 3J24 100R 1% PX3E- PX3CLK- FJ35 37
M +
114 RMLV1N 46 2J32 H7 FJ13 B9

33K 1%
170 15K 1% PX3E+ PX3CLK+ FJ36 38 RCLK3 RLV5 113 RMLV1P PX2D+
P - 47
2J33 C3 FJ14 B9

3J02
GIP_EN FJ0D 132 154
GIP_EN PWM_TOUT|WPWM NC 48
83 84 153 111 RMLV0N PX2E-
PLLVDD PLLGND ODC_BYPASS FJ0E 150
PWM_TIN
3J25 100R 1% PX4A- PX4A- FJ37 45 RLV6
+
110 RMLV0P
49 2J34 D3 FJ15 B9
ODC_BYPASS M - 50
16 15
EEP_SIZE LEDON
162
NC
PX4A+ PX4A+ FJ38 46
P
RA4 PX2E+ 51 3J01 C4 FJ16 B9
30 29 FJ0F 87
EEP_SIZE 52
E E 3J02 E6 FJ17 C9

RES 2J0F
44 LVDD LGND 43 155 3J26 100R 1% FJ39 47

15p
SCAN_BLK|REFMODE PX4B- PX4B- M PX3A- 53
58 57 SCL-TCON 176 163 NC PX4B+ PX4B+ FJ40 48 RB4
ML_VDD SDA-TCON 175
SCL SCAN_BLK2 P
PX3A+
54 3J03 D6 FJ18 C9
SDA 55
91
101
1V8 90
96
I2C_EN FJ0G
RES 9J03
149
164
I2C_EN H_CONV
142
H_CONV
3J27 100R 1% PX4CLK- PX4C- FJ41
FJ42
49
50
M
RC4
56 3J04 G7 FJ19 C9
WP WP PX4CLK+ PX4C+ P PX3B- 57
109
MLVDD MLVSS
106
VDD_EVEN|GOE
68 GVDD_EVEN
58
3J06 G7 FJ20 C9
117 112 141 OPT_N 3J28 100R 1% PX4C- PX4D- FJ43 53 PX3B+
125 122
OPT_N
67 GVDD_ODD PX4C+ PX4D+ FJ44 54
M
RD4
59 3J07 A8 FJ21 C9
VDD_ODD|GSC P 60
VCORE
2 1 3J29 100R 1% FJ45 55
PX3C- 61 3J08 A8 FJ22 C9
PX4D- PX4E- M 62
59 61 PX4D+ PX4E+ FJ46 56
P
RE4 PX3C+ 63
3J09 A8 FJ23 C9
69 70
77 78 3J30 100R 1% PX4E- PX4CLK- FJ47 51 PX3CLK-
64 3J10 A8 FJ24 C9
M 65
85 CVDD CGND 86 PX4E+ PX4CLK+ FJ48 52
P
RCLK4
66 3J11 B8 FJ25 C9
F 128
145
129
146
PX3CLK+ 67
68
F 3J12 B8 FJ26 D9
158 159 PX3D- 69 3J13 B8 FJ27 D9
70
GND_HS
177 PX3D+ 71 3J14 B8 FJ28 D9
72
PX3E- 73
3J15 C8 FJ29 D9
LDO BLOCK E2PROM VCC +VDISP ASIC OPTION PX3E+
74 3J16 C8 FJ30 D9
75
7J01-4
TL2429MC VCC
76 3J17 C8 FJ31 D9
PX4A- 77
VIA36 RES 3J39 78
3J18 C8 FJ32 D9
100n
2J28

3J04

178 196 GIP_EN


47K

PX4A+
179 197 1K0
79 3J19 C8 FJ33 D9
80
G 180
181
198
199 7J03
VCORE 9J04 WP SCL-TCON 1
1J02
RES 3J40 EEP_SIZE
PX4B- 81
82
G 3J20 D8 FJ34 D9
182 200 VCC LD1117ADT18 7J02 SDA-TCON 2 1K0 PX4B+ 83 3J21 D8 FJ35 E9
183 201 M24C32-WDW6 3
8

FJ0H 3J41 84 3J22 D8 FJ36 E9


Φ I2C_EN
3J06

184 202 3 2 VCC


18K

IN OUT WP 4 PX4C- 85
185 203
186 204 COM (4K×8) 7
5
7 6
1K0
PX4C+
86 3J23 D8 FJ37 E9
VIA VIA WC RES 3J42 87
3J24 E8 FJ38 E9
2J26

2J25

187 205 EEPROM ODC_BYPASS


10u

10u

FJ4A 88
3J35

3J36

188 206 1 6 BM05B-SRSS-TBT


4K7

4K7

PX4CLK-
1

189 207 2
0
1 ADR
SCL 1K0 89
90
3J25 E8 FJ39 E9
190 208 3 5 3J43 REVERSE
191 209
2 SDA 3J37

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