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6.3.1 Device technology

Radio Frequency (RF) building block performance generally degrades with increasing frequency. The power capability of power amplifiers for a given integrated
circuit technology roughly degrades by 15 dB per decade, as shown in Figure 6.2. There is a fundamental cause for this degradation; increased power
capability and increased frequency capability are conflicting requirements as observed from the so-called Johnson limit [14]. In short, higher operational
frequencies require smaller geometries, which subsequently result in lower operational power in order to prevent dielectric breakdown from the increased field
strengths. Moore’s Law does not favor power capability performance. A remedy is however found in the choice of integrated circuit material. Millimeter wave
integrated circuits have traditionally been manufactured using so called III-V materials, i.e. a combination of elements from groups III and V of the periodic table,
such as Gallium Arsenide (GaAs) and Gallium Nitride (GaN). Integrated circuit technologies based on III-V materials are substantially more expensive than
conventional silicon-based technologies and they cannot handle the integration complexity of e.g. digital circuits or radio modems for cellular handsets.
Nevertheless, GaN-based technologies are now maturing rapidly and deliver power levels an order of magnitude higher compared to conventional technologies.
Thus, there is a strong interest in new building practices where different technologies can be mixed (heterogeneous integration) in a cost-efficient way to exploit
their respective strengths. Such building practices are also well aligned with integration needs expected for cost-efficient implementation of beamforming
architectures.

Figure 6.2 Power capability of various power amplifiers in different technologies versus frequency.

Integrated Local Oscillator (LO) phase noise is another key parameter that worsens with frequency and ultimately limits the attainable Error Vector
Magnitude (EVM). The Phase Locked Loop (PLL) used to generate the LO signal has a Voltage Controlled Oscillator (VCO) that dominates power consumption
and phase noise. The VCO performance is commonly captured through a Figure-of-Merit (FoM) allowing for a comparison of different VCO implementations
and is defined by

FoM=PNVCO(df)−20log10(fodf)+10log10(PDC1mW).
(6.1)
Here PNVCO(df) is the phase noise of the VCO in dBc/Hz at a frequency offset df with oscillation frequency fo (both in Hz) and power consumption PDC in mW.
One noticeable result of this expression is that both phase noise and power consumption in linear power are proportional to fo2. While the FoM definition may
seem frequency agnostic there is an additional penalty associated with higher frequencies as shown in Figure 6.3 where FoM of recently published VCO
designs are compared. Thus, stepping up from the low-GHz regime of today’s cellular systems to the mmW regime while preserving the same level of
integrated phase noise obviously calls for a re-evaluation of how the LO generation should be implemented. One mean of suppressing VCO phase noise is to
increase the bandwidth of the PLL. This effectively yields an LO phase noise characteristic that to a larger extent tracks the phase noise of the crystal oscillator
(XO) serving as reference for the PLL and thus push requirements on the XO instead. Also, since the XO phase noise is amplified as 20log10(fo/fXO) when
referred to the LO signal the XO frequency fXO, commonly in the low tens of MHz today, would need to be increased to 200 MHz–500 MHz. Although it is
possible to implement crystals for this frequency range they do exhibit significantly higher tolerances and drift that in turn may affect terminal-base station
synchronization time and complexity of tracking crystal drift in terminals.
 Figure 6.3 VCO FoM versus frequency for recently published VCOs. The dashed line indicates state-of-the-art performance.

The larger bandwidths anticipated with mmW communication will also challenge the data conversion interfaces between analog and digital domains in both
receivers and transmitters. This is particularly true for Analog-to-Digital Converters (ADCs). Similar to VCOs there are FoM expressions to capture merits of
ADC designs, e.g. the Walden FoM defined by FoM=PDC/(2ENOBfS) with power consumption PDC in W, the Effective Number of Bits for the ADC denoted by
ENOB, and sampling frequency fS in Hz. Figure 6.4 plots the Walden FoM for a large number of published ADCs [15] against the Nyquist sampling frequency
fsnyq for each design. The Walden FoM can be interpreted as energy per conversion step, and the plot clearly demonstrates a penalty in conversion beyond a
few hundred MHz of sampling rate, roughly amounting to 10 times increase per decade. Although this FoM envelope (dashed line in plot) is expected to be
slowly pushed toward higher frequencies by continued development of integrated circuit technology, RF bandwidths in the GHz range are still expected to give
poor power efficiency in the analog-to-digital conversion.

Figure 6.4 The Walden FoM representing the energy per conversion step is plotted against Nyquist sampling frequency for large number of published ADCs. The FoM
envelope (dashed) represents the achievable lower limit using technology from around 2015.

Larger signal bandwidths also impact the complexity and power consumption of the digital circuitry. While Moore’s Law has enabled a virtually exponential
complexity growth for decades, in recent years concerns have gradually been raised on the longevity of this technology evolution. The problem lies in that pure
scaling of geometric features as the engine for this progress is quickly approaching its limits. Solutions to this problem considered include the introduction of III-
V materials, new device structure (FinFET, nanowire transistors, etc.), and 3D integration. However, none of these will serve as a vehicle for continued
exponential improvements. Another problem is that the cost per digital transistor or function has been seen to flatten out or even increase as CMOS technology
feature size goes below 28 nm. Nevertheless, a few more technology cycles, with a corresponding reduction of digital power consumption, are expected before
2020.
There are many more building blocks and associated limitations beyond the ones mentioned above, but those treated are viewed as the most challenging,
and are worthy of further study.