designfeature By Alan Elbanhawy, Fairchild Semiconductor Corp

AS POWER-SUPPLY SIZE AND PERFORMANCE DEMANDS

INCREASE, SELECTING THE RIGHT SWITCHING DEVICES
BECOMES MORE COMPLEX. A STRAIGHTFORWARD METHOD
SIMPLIFIES THE SELECTION PROCESS, SPEEDS YOUR DEVEL-
OPMENT, AND HELPS YOU TO OPTIMIZE YOUR DESIGN.

A simple guide to selecting

power MOSFETs
iven the wide selection of MOSFETs available of 1.5V, resulting in a duty cycle D for Q1 of

G now and the shrinking real estate allotted for 1.5/1250.125 and 12D for the synchronous recti-
motherboard power supplies, it’s increasingly fier Q2. Switching losses dominate the power dissi-
important to use a dependable, consistent method pation in Q1, owing to its relatively small duty cycle
for selecting the right MOSFET. Such a method can compared with that of Q2. Q1’s voltage excursion is
speed development cycles while optimizing applica- the source voltage. Although Q2 must also stand off
tion-specific designs. the full supply voltage, at the beginning of its switch-
PC-motherboard and power-supply designers, ing interval, the body diode clamps the filter induc-
who frequently go through the power-MOSFET se- tor to ground, so Q2’s excursion is limited to a diode
lection process, can benefit from an automated drop. The small duty cycle and large excursion put
process that uses a spreadsheet. This common tool demands on Q1’s rise- and fall-time performance.
can significantly reduce the selection time while af- Conduction losses, which are a function of RON,
fording the designer an intimate, step-by-step look dominate Q2’s power dissipation. Minimizing this
at the selection process. Compared with algorithmic ohmic term requires a device with the lowest on-re-
programming languages, implementing a selection sistance to handle the load current based on cost ex-
method in a spreadsheet provides for greater inter- pectations and efficiency requirements.
action, easy fine-tuning, and simple provisions for
building and maintaining a parts database.
To limit the scope of this discussion, consider a
MOSFET-selection method for the synchronous
buck-converter topology, which suits dc/dc con-
Q1
verters for PC motherboards and telecommunica-
tions applications. The search for the right MOSFET
VP1 L
for a specific application involves minimizing the
losses and understanding of how these losses are de-
pendent on the switching frequency, current, duty
cycle, and the switching rise and fall times. This in-
formation guides the selection tool development.
Q2 C RL
Once you choose a topology, you can base the
MOSFET selection on its position in the circuit and VP2
a few device parameters, such as breakdown voltage,
current-carrying capability, RON, and the RON
temperature coefficient. The goal is to mini-
Figure 1
mize conduction and switching and to
choose a device with adequate thermal properties.
Examining a typical buck converter reveals how The buck-converter topology uses two n-channel MOSFETs.
device requirements vary significantly depending on Q1 is the switching or control MOSFET, and Q2 is the syn-
circuit position (Figure 1). This circuit takes power chronous rectifier. L and C comprise the output filter, and RL
from a 12V source and provides an output voltage is the load resistance.
www.ednmag.com November 22, 2001 | edn 87
 designfeature Selecting power MOSFETs

The spreadsheet includes calculations 16

of static and dynamic losses, the latter of
which is the sum of switching and gate-
drive losses. To facilitate the dynamic-
12
loss calculations, you need to refer to rep-
resentative waveforms (Figure 2). Prior
to switching, the MOSFET’s power dissi-
pation derives from conduction losses. 8
The area under the blue triangle
depicts the dynamic loss during Figure 2
the switching transition time, which oc- 4
curs twice per cycle. The total dynamic
loss, therefore, is proportional to the
switching frequency.
The conduction loss is proportional to 0

the MOS device’s on-state channel re- 93.400US 93.420US 93.440US 93.460US 93.480US 93.500US 93.520US
ID(M1) V(M1:d,M1:S) ID(M1)*V(M1:d,M1:S)/8
sistance:
TIME
PC (Q1) = I2D1R ON1D, Switching Q1 results in characteristic waveforms for ID (green) and VDS (red). The product of these
and two waveforms gives the instantaneous power dissipation, PD, (blue).
PC (Q2 ) = ID
2
2R ON 2 (11D),
for either position. Q1’s power dissipa- the junction-to-case resistance of the
where ID is the drain current, RON is the tion is given by: FET’s package and the heat-sink thermal
channel resistance at the manufacturer’s resistance. There’s also a small case-to-
specified nominal ambient temperature, P(Q1) = I2RMS R ON1D + heat-sink term, which is often negligi-
(1)
and D is the duty cycle of Q1.  1  ble—particularly when you use modern
Charging and discharging the gate ca- f QG1VG1 + (t r + t f )IRMS VS  . thermal interface materials. The heat sink
pacitance contributes to the switching  2  can be an explicit mechanical device or
losses. This loss also depends on the In Equation 1, the first term reflects a pc-board trace with adequate surface
switching frequency: the conduction loss, and the second term area (Figure 3).
accounts for the dynamic and gate loss- Although these equations are simple
PG = VG2 CGS f , es. IRMS is the drain current; RON is the enough to allow a quick check of a given
channel resistance; D is the duty cycle; f MOSFET’s suitability in a specific appli-
where VG is the gate-drive voltage, CGS is is the switching frequency; tr and tf are the cation, the strong dependency of RON on
the gate-source capacitance, and f is the switching rise and fall times, respective- the junction temperature somewhat
switching frequency. ly; and VS is the input source voltage. complicates the calculation. A tempera-
Similarly, Q2’s power dissipation is giv- ture rise of about 808C causes a 40% in-
THE UPS AND DOWNS OF MOSFET SELECTION en by: crease in the value of RON. You need to in-
The requirements for the control P(Q2 ) = I2RMS R ON 2 (11D) + clude this behavior in the analysis of the
switch, Q1, and the synchronous rectifi- conduction losses to calculate the actual
 1 
er, Q2, differ. Current, voltage, and pow- f QG2 VG2 + (t r + t f )IRMS VD  . temperature rise.
er-dissipation ratings are key parameters  2  If you include the RON’s temperature
that determine the suitability of a device As in the previous case, the first term coefficient in Equation 1, you get:
is the conduction loss, and the second
P(Q1 ) = I2RMS R ON1(1 + δ∆ T )D + PD (Q1),
TRACE THERMAL RESISTANCE term is the switching loss. Note that D is
60
Q1’s duty cycle. The last term, VD, is the and
55
body-diode forward voltage. You P(Q2 ) = I2RMSR ON1(1 + δ∆ T )(11D) +
50 Figure 3 can reduce this loss and improve the
45 circuit’s switching dynamics by connect- PD (Q2 ),
8C/W
40 ing a Schottky diode across Q2. where d is the temperature coefficient of
35 With the power dissipation calculated RON in 8C-1, and PD is the dynamic loss
30 for the two devices, you can calculate the term, which is independent of RON.
25
temperature rise from the thermal re- When you substitute these variables
20
sistances of the package and heat sink as: into Equation 2 and solve for the devices’
0 0.5 1 1.5 2 2.5 DTs, you find that:
SQUARE INCH, 2-OZ COPPER ∆ T = R ΘP, (2)
You can express the thermal resistance of a 2- where DT is the temperature rise over am- R Θ[I2RMSR ON1D + PD (Q1)] (3)
∆ T (Q1) = ,
oz copper pc-board trace in degrees Celsius per bient in degrees Celsius, P is the device’s 1 − R Θ I2RMSδR ON1D
watt, as a function of the trace area. This thick- total power dissipation, and RQ is the to-
ness of copper is typical of most pc boards. tal thermal resistance taken as the sum of and
88 edn | November 22, 2001 www.ednmag.com
 designfeature Selecting power MOSFETs
∆ T (Q2 ) =
R Θ[I2RMSR ON1(1 − D) + PD (Q2 )]
. gle-layer pc board with 2-oz copper, ver-
1 − R Θ I2RMS δR ON1(1 − D)
Equation 4 provides the junction-
temperature rise as a function of the load
current and a specific set of MOSFET pa-
rameters. A junction temperature of
about 1058C is usually a good first cut for
commercial applications.
CALCULATING THE DYNAMIC LOSSES
The rise and fall times depend on char-
acteristics of both the MOSFET and your
gate-drive circuit. The gate charge, QG, is
the product of the gate capacitance and
the drive voltage, usually given at 4.5V.
The gate capacitance combines with the
gate drive’s output impedance to limit the
gate rise and fall times:
 1t 
VG = VP  11e R PC G  ,
 
 
 V 
∆t = 1R PCG ln  11 G  ,
 VP 
and
QG  V 
t r = t f = 1R P ln  11 G  .
VP  VP 
In these equations,VG is the equivalent
gate voltage, VP is the gate-drive pulse
amplitude, RP is the gate-drive output im-
pedance, and CG is the gate capacitance.
The MOSFET is fully on when VG
reaches 99% of VP. If you substitute this
relationship back into Equation 5, the
rise and fall times reduce to:
Q sheet this way, you can perform a “what-
t r = t f ≈ 4 .6 R P G .
VP
You can now calculate the total dy-
namic loss for each device:
 1  of the conduction and switching-loss
PD (Q1) = f QG1VG1 + (t r + t f )IRMS VS ,
 2 
and
 1
PD (Q2 ) = f QG2 VG2 + (t r + t f )IRMS VD  ,
 2
where VG is the gate drive for the refer-
enced device.
COMPLETING THE DESIGN
Determine the thermal resistance of
the heat sink from the manufacturer’s
90 edn | November 22, 2001
data sheet or from the dimensions of the
pc-board trace. Figure 3 shows the pc-
(4) board-trace thermal resistance of a sin-
sus a square copper area with the
MOSFET located in its center. Depend-
ing on the available pc-board area, the
copper can act as a heat sink for the
MOSFET. It is worth noting that for small
devices, increasing the area beyond the 2
square inches will not appreciably lower
the thermal resistance.
In a spreadsheet, compile a database of
MOSFETs suitable for your application.
For the synchronous rectifier, Q2, the
MOSFET must meet the voltage and cur-
rent requirements of the application. It
must also have a sufficiently low RON, so
that the conduction loss is small enough
to meet the efficiency target. For this
MOSFET, the gate charge plays a second-
ary role in power dissipation.
For the control device, Q1, the dy-
namic or switching losses are the pre-
dominant factor, and conduction losses
play a secondary role. The MOSFET
should meet the voltage and current
specification with as low a gate charge as
possible to keep the dynamic losses
small. Secondarily, seek a device with a
(5) moderate RON.
Solve equations 3 and 4 for the tem-
perature rise for all the MOSFETs in the
database. Then you can select the MOS-
FET that meets your temperature-rise,
package, and price requirements. A
spreadsheet sheet that solves equations
3 and 4 for a selection of MOSFETs al-
lows the simultaneous evaluation of
several MOSFETs. By using a spread-
if ” analysis to select the optimum MOS-
FETs for the application. You can adapt
this basic method to other topologies so
long as you’ve gained an understanding
requirements for each device in your
design.k
 Author’s bio graphy
Alan Elbanhawy is senior staff engineer at
 Fairchild Semiconductor International.
He has more than 30 years experience in
power-supply design and R&D manage-
ment, covering aerospace, military, com-
mercial, and industrial applications. He
holds a bachelor of science in electrical
engineering.
www.ednmag.com