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Comparator-Based Analog-to-Digital Converters

Jieh-Tsorng Wu

April 22, 2016

ES
National Chiao-Tung University
A

1896
Department of Electronics Engineering
Flash Quantization Architecture

VR (1) VR (2) VR ( 2N −1)


VRB VRT

Vi

1 2 2N −2 2N −1

N
( 2 −1 ) − to − N Encoder

N
Do

• Resolution is mainly determined by matching of the resistor string and the offsets of
the comparators.

Cmp-Based ADCs 11-2 Data-Conversion ICs; Jieh-Tsorng Wu


Comparator Typical Architecture
Preamplifier Latch

Vi1 Vo1 Vi Vo
A Latch

VOSA VOSL
Vi2 Vo2

• The equivalent input offset is

VOSL σ 2(VOSL)
VOS = VOSA + σ 2(VOS ) = σ 2(VOSA) +
A A2

T
− τc
• The probability of metastability is PM = (1/A) × (VD /VA) × e r .

• The preamplifier also provides: (1) input common mode rejection; (2) kick-back noise
reduction; (3) analog signal processing (offset cancellation, averaging).

Cmp-Based ADCs 11-3 Data-Conversion ICs; Jieh-Tsorng Wu


Offset of a Source-Coupled Pair
Id1 Id2 Id1 Id2

Vi1 M1 M2 Vi1 M1 M2

Vi2 Vi2
VOS

M1 M2 M1 M2

2 2 2
!
Vov σ (∆β) 1 Vov

σ 2(VOS ) = σ 2(∆Vt ) + × = A2V + · A2β
2 β2 W ·L t 4
2 2 2
W AVt σ (∆β) Aβ
β = µCox σ 2(∆Vt ) = =
L W ·L β2 W ·L

Cmp-Based ADCs 11-4 Data-Conversion ICs; Jieh-Tsorng Wu


Speed-Power-Accuracy Trade-off of MOS Comparators

For a MOST pair, mismatches and input-referred offset are modeled as

2 2 2 2
!
AVt0 σ (∆β) Aβ 1 Vov
σ 2(∆Vt ) = = ⇒ σ 2(VOS ) = A2V + · A2β
W ·L β2 W ·L W ·L t 4

For a comparator

2
A2Vt · A2β
2 Vov
gm 2I/Vov 1 σ (VOS ) + 4
Speed ∝ ≈ ∝ ≈
Cox (2/3) · W L · Cox 2 2 2
Accuracy VDD W L · VDD
2
Speed × Accuracy 1 VDD
Power ∝ I · VDD ⇒ ∝ ×
Power

2
Vov Vov
Cox · AV + 4 · A2β
2
t

• K. Uyttenhove and M. Steyaert, “Speed-power-accuracy tradeoff in high-speed CMOS


ADCs,” TCAS-II, 2002/4, pp. 280–286.

Cmp-Based ADCs 11-5 Data-Conversion ICs; Jieh-Tsorng Wu


Switched-Capacitor Offset Storage
Output Offset Storage (OOS)
V V
2 c o
V
i Latch V’
S1 o
A C Q
S2 o C
1 S3 L
V OS V OSL
1a

Input Offset Storage (IOS)


1a
Q
V S3
c V
2 o
V V’
i Latch o
S1 Ci
S2 A
C
1 L
V OS V OSL

• Require preamplifier settling for offset storage.

Cmp-Based ADCs 11-6 Data-Conversion ICs; Jieh-Tsorng Wu


Preamplifier Array Offset Averaging
VDD VDD VDD VDD

R0 R0 R0 R0 R0 R0 R0 R0
R1 R1 R1 R1

R1 R1 R1 R1

Vi VR (−1) Vi VR (0) Vi VR (1) Vi VR (2)

• Random offsets of the MOST preamplifiers are averaged by the R1 resistors.

• Reference: H. Pan and A. Abidi, “Spatial Filtering in Flash A/D Converters,” TCAS-II
2003/8, pp. 424–436.

Cmp-Based ADCs 11-7 Data-Conversion ICs; Jieh-Tsorng Wu


Spatial Filtering — Impulse Response

Ii (x)

Ii (−1) Ii (0) Ii (+1) VM


Vi VR (x)
VM
Vo (−1) Vo (0) Vo (+1)

R1 R1 R1 R1 h(x)
Io (−1) Io (0) Io (+1)
R0 R0 R0

x
WH WH

(
Gm · [Vi − VR (x)] if |Vi − VR (x)| ≤ VM VM
Ii (x) = VR (x) = ∆V · x WM =
±Gm · VM if |Vi − VR (x)| > VM ∆V
+WH
Io(x)

X
Impulse Response = h(x) ≡ ⇒ Io(x) = Ii (x − y)h(y)
Ii (0) Ii (y)=0,y6=0 y=−WH

• WH is defined as the span of a current input that it has significant influence.

Cmp-Based ADCs 11-8 Data-Conversion ICs; Jieh-Tsorng Wu


Spatial Filtering — Output Response

Consider current inputs with offsets, i.e.,


(
Gm · Vi − VR (x) − VOS (x) if |Vi − VR (x) − VOS (x)| ≤ VM
 
Ii (x) =
±Gm · VM if |Vi − VR (x) − VOS (x)| > VM

Let VR (x) = ∆V · x and h(−x) = h(x), the output current Io(x) can be expressed as

+WH +WH
Io(x) X X
= [Vi − VR (x)] h(y) − VOS (x − y)h(y) if WM ≥ WH
Gm y=−WH y=−WH

+WM +WM
X X
= [Vi − VR (x)] h(y) − VOS (x − y)h(y) if WM ≤ WH
y=−WM y=−WM

P+WH
• Note that y=−WH
h(y) = 1.

Cmp-Based ADCs 11-9 Data-Conversion ICs; Jieh-Tsorng Wu


Spatial Filtering — Gain and Offset

The preamp array’s voltage gain offset can be expressed as

+Wn
X
Av = GmR0 × h(y) Wn = min (WM , WH )
y=−Wn

P+Wn
• Since y=−W h(y) < 1, the loss of output current to the averaging network reduce the
n
preamp’s voltage gain. Increase R0 can recover gain but also decrease bandwidth.

The preamp array’s input-referred offset is


P+Wn
y=−Wn
VOS (x − y)h(y)
i
VOS (x) = P+Wn Wn = min (WM , WH )
y=−Wn
h(y)

i
• In addition, VOS (x) is also affected by mismatches among the tail currents of the
preamps within the range of x ± WH .

Cmp-Based ADCs 11-10 Data-Conversion ICs; Jieh-Tsorng Wu


Offset Averaging by Spatial Filtering

Assume VOS (x) for all x are independent Gaussian variables with a mean of 0 and a
i
variance of σ(VOS ). The variance of VOS (x) can be expressed as

   P 1/2
i +Wn 2
σ VOS  y=−Wn (y) 
h
 = i2  = RINL = INL Reduction Factor

σ VOS +Wn
 hP
y=−W
h(y)
n

i i i
The DNL is ∆VOS (x) = VOS (x) − VOS (x + 1) is also a Gaussian variables. Its reduction
factor can be expressed as

   1/2
i +Wn 2
[h(y) 1)]
P
σ ∆VOS − h(y −
1 y=−Wn
 = √ ×
 
RDNL ≡ 
i2

σ ∆VOS 2 +Wn
hP 
h(y)
y=−Wn

Cmp-Based ADCs 11-11 Data-Conversion ICs; Jieh-Tsorng Wu


Spatial Filtering Using Resistor Strings

The impulse response of a R-string of infinite length is

R
s
1 R1

1 1
R
2 b · R1
|x| 0
h(x) = h(0) · b b=1+ − 1+ −1 h(0) =
2 R0 2 R0 1 − b2

0.8 P+∞
• x=−∞ h(x) = 1.
0.6
• If R0 → ∞, we have R1/R0 → 0 and
b

0.4
s
R1
0.2 b → 1 h(0) → WH → ∞
R0
0
0 0.2 0.4 0.6 0.8 1
R1 / R0

Cmp-Based ADCs 11-12 Data-Conversion ICs; Jieh-Tsorng Wu


Offset Averaging Using Resistor Strings

0.5
0.4
RINL

0.3
0.2
0.1
0

0.5
Wn = 4
0.4
Wn = 8
RDNL

0.3 Wn = 16
0.2
0.1
0
0.01 0.1 1
R1 / R0

Cmp-Based ADCs 11-13 Data-Conversion ICs; Jieh-Tsorng Wu


Spatial Filtering Using Current Summation
VDD

R0 R0

Vo (x)

Vi VR (x−2) Vi VR (x−1) Vi VR (x) Vi VR (x+1) Vi VR (x+2)

G’m G’m G’m G’m G’m

0 Gm
Gm =
2WH + 1
(
1/(2WH + 1) if |x| ≤ WH
Let WH ≤ WM ⇒ h(x) =
0 if |x| > WH

Cmp-Based ADCs 11-14 Data-Conversion ICs; Jieh-Tsorng Wu


Offset Averaging Using Current Summation

The output can be expressed as

+WH
Vo(x) 1 X
= [Vi − VR (x)] − VOS (x − y)
Gm R 0 2WH + 1 y=−W
H

Voltage Gain = Av = GmR0

The resulting INL and DNL reduction factors are

 1/2
P+Wn 2
 y=−Wn h (y)  1
RINL = 
i2  =p
2WH + 1
 hP+W
n
y=−W
h(y)
n

 1/2
P+Wn 2
1 y=−Wn
[h(y) − h(y − 1)]  1 1
= √ × =√ ×

RDNL 
2 2WH + 1
i2
2 +Wn
 hP 
y=−W
h(y)
n

Cmp-Based ADCs 11-15 Data-Conversion ICs; Jieh-Tsorng Wu


Edge Effect and Termination
P+WH
The current outputs are Io(x) = I (x
y=−WH i
− y)h(y). Toward to edges of a R-String,
i
both h(x) and range of convolution varies, causing systematic offset in VOS .

Dummy Stages and Req Termination


WD1 WFS WD1

Req Req

Req Req
R1 R1
R0 R0
Req Req

q
R1 + R12 + 4R1R0
Req = R1 + R0 k Req ⇒ Req =
2
WD1 ≥ WH

Cmp-Based ADCs 11-16 Data-Conversion ICs; Jieh-Tsorng Wu


Differential Cross-Connection Termination

WD2 WFS WD2

R1 / 2 R1 / 2

R1 / 2 R1 / 2

WD2 ≥ min(WH , WM )

• The two resistor strings form a resistor ring.

Cmp-Based ADCs 11-17 Data-Conversion ICs; Jieh-Tsorng Wu


Optimal Spatial Filtering

2WD
WT = Total Number of Preamps WH = WM = WD WT = WF S + 2WD k≡
WT
WF S
VF S = (VRT − VRB ) × = VR × (1 − k)
WT
AT = Total Device Area = WT × W L

Considering offsets,

AVt 1 AVt
i
= σ VOS × RINL = √ =p AD = AT × k
 
σ VOS ×p
WL ηWD ηAD
V 1 V q p
FS R
4σ VOS ≤
i
2 ≤ ·
N

⇒ · ηAT · k(1 − k)
2 N 4 AVt

• For a given VR voltage range and a AT area, the maximum 2N is achieved if k ∼ 1/3.

• For (1/2) < k < (1/6), k(1 − k) varies only 12%.

Cmp-Based ADCs 11-18 Data-Conversion ICs; Jieh-Tsorng Wu


Optimal Design of Resistor-String Spatial Filtering

1. Define the full-scaled input range VF S , the reference voltage range, VR . We have

VR − VF S VF S VR VR − VF S
k= ∆V = WT = 2WD = = k · WT
VF S 2N ∆V ∆V

Want k = (1/6) ∼ (1/2).


2. Design the preamps with a VM such that

VM
WM = WM & WD = k · WT /2
∆V

Choose R1 and preamp’s tail current, IS , to meet the voltage gain and bandwidth requirement.
3. Add WD dummy stages. Use differential cross-connection termination or Req termination.
4. Add lateral averaging resistors, R1 . Choose the R1 resistance such that WH = WD .
5. Simulate the preamp array to determine its voltage gain, bandwidth, and the systematic INL due to the
edge effect. Adjust R1 to meet the INL specification. After that, if the voltage gain or the bandwidth
worsen than those of a single isolated preamp by more than 10%, increase R1 .
6. Scale the entire preamp array to tradeoff the preamp array’s total input capacitance and its INL due to
VOS (x).

Cmp-Based ADCs 11-19 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi)

• M. Choi and A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35-µm CMOS,” JSSC
2001/12, pp. 1847–1858.

Cmp-Based ADCs 11-20 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi)

• Fabricated in a 0.35 µm CMOS technology.

• Maximum conversion rate is 1.3 GS/s.

• Power dissipation is 545 mW with VDD = 3.3 V. Logic and clock consume 50% of the
total power.

• Input range is 1.6 Vp−p differential.

• ADC design parameters: N = 6, WF S = 2N − 1 = 63, 2WD = 18, WT = 81, k = 0.286.

• Preamplifier design parameters: W = 20 µm, L = 0.4 µm, WM = 9, σ VOS = 7.5 mV.




• Resistive averaging network: R1/R0 = 0.1. RINL ≈ 0.3.

Cmp-Based ADCs 11-21 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi) — Track-and-Hold

• Distortion Sources: charge injection of switches, source follower nonlinearity, signal-


dependent input capacitance of the quantizers.

Cmp-Based ADCs 11-22 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi) — Preamplifier

Cmp-Based ADCs 11-23 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi) — First Stage Comparator

• Dynamic offset reduction by resistive averaging.

Cmp-Based ADCs 11-24 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi) — Second Stage Comparator

Cmp-Based ADCs 11-25 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi) — Monte Carlo Simulation

• Latch dynamic offset is largest.

Cmp-Based ADCs 11-26 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Choi) — Clock Generator

Cmp-Based ADCs 11-27 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Deguchi) — Architecture

• Reference: K. Deguchi, et. al., “A 6-bit 3.5-GS/s 98-mW Flash ADC,” Symposium on
VLSI Circuits, 2007, pp. 64–65.

Cmp-Based ADCs 11-28 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Deguchi) — Preamplifier

Cmp-Based ADCs 11-29 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Deguchi) — Averaging and Interpolation

• Both source-coupled pair mismatch and tail current source mismatch are considered.

Cmp-Based ADCs 11-30 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Deguchi) — Chip and Performance Summary

Cmp-Based ADCs 11-31 Data-Conversion ICs; Jieh-Tsorng Wu


Offset-Trimmable Regenerative Latch
VDD

CK M5 M6 CK
M10 M8 M9 M11

Vo2 Vo1

M3 I1 M4

C1
I1 Vi1 M1 M2 Vi2 I2
C2

VSS CK VSS
M7

VSS

• Offset is trimmed by varying C1 and C2.

Cmp-Based ADCs 11-32 Data-Conversion ICs; Jieh-Tsorng Wu


Offset-Trimmable Regenerative Latch
VDD

CK M5 M6 CK
M10 M8 M9 M11

Va2 Va1

M3 M4

Da2 Da1 Db1 Db2

Vi1 M1A M2A M1B M2B VC1

Vi2 VB VC2

CK

VSS VSS

Cmp-Based ADCs 11-33 Data-Conversion ICs; Jieh-Tsorng Wu


Comparator Offset Calibration

V CM
V OS
CK
CAL
CAL
V i1
Dc 0 t
V i2
CAL V OS
CAL

V CM Up/Down
Counter

• During Calibration, Vi = Vi 1 − Vi 2 = 0.

Cmp-Based ADCs 11-34 Data-Conversion ICs; Jieh-Tsorng Wu


Random-Chopping Latch (RCL) with Digital Offset Calibration
q[k] q[k]
Latch

Vi[k] D c[k]

VR D c[k]

CHP1 CHP2
VOS [k]
RCL
Calibration q[k]
Processor ACC AAR
(CP)
Σ Σ D e[k]
T[k] S[k] U[k]

• Reference: C-C Huang and J-T Wu, “A Background Comparator Calibration


Technique for Flash Analog-to-Digital Converters,” IEEE TCAS-I, 2005/09, pp. 1732-
1740.

Cmp-Based ADCs 11-35 Data-Conversion ICs; Jieh-Tsorng Wu


Accumulation-and-Rest (AAR) Operation

ACC0 BPD ACC


U[k] R[k] S[k] T[k] VOS [k]
Σ R[k] NC ? Σ RCL

Reset VOS

AAR
R[k]
NC

0 k

NC

VOS [k]

0 k

Cmp-Based ADCs 11-36 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC (Huang)
VR,63 VR,2 VR,1
VRT VRB

M1 Vi[k]
s(t)

RCL q [k] RCL q [k] RCL q [k]


φ 2 2 1

CP D c,63[k] CP D c,2[k] CP D c,1[k]

TCED

D e,63[k] D e,2[k] D e,1[k]

Encoder s[k]

Cmp-Based ADCs 11-37 Data-Conversion ICs; Jieh-Tsorng Wu


Latch Circuit Schematic (Huang)
q[k+1] CK q[k]

V1 V3p V4p
Vi[k] D c[k]
2 2 Latch Latch Latch
2 2 1 2 3
VR D c[k]
V2 V3n V4n
CHP1 CHP2
VDD

CK M9 M11 CK 16
M15 M13 M14 M16

Tfa Tfb
Vo1 Vo2

M10 M12 M17 M18

Va1
Va2 4

M19 M20
V1p M5 M6 V2p V2n M7 M8 V1n Tca Tcb

VB M21
M1 M3
CK M22
M2 M4

Cmp-Based ADCs 11-38 Data-Conversion ICs; Jieh-Tsorng Wu


A 6-Bit Flash ADC Chip (Huang)

Technology 65nm CMOS


Resolution 6 bits
Max. Sampling Rate 2 GHz
Supply Voltage 1.5 V
Diff. Input Range 0.8 Vpp
Input Loading 225 fF
SNDR (fi n=200 MHz) 30.8 dB
SFDR (fi n=200 GHz) 36.4 dB
Power Consumption 54 mW
2
Active Area 0.21 × 0.66 mm
• Reference: C-C Huang, C-Y Wang, and J-T Wu, “A
CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital
Background Calibration Techniques,” IEEE JSSC, 2011/4,
pp. 848-858.

Cmp-Based ADCs 11-39 Data-Conversion ICs; Jieh-Tsorng Wu


Subranging Flash Quantization Architecture
A1 A2

G1

M− sub da L−
Aj (D1)
ADC DAC ADC

VRB1 VRT1 VRB2 VRT2


D1 D2
G1 = 1
A1

M− L−
ADC ADC

VRB1 VRT1 VRB2 VRT2


D1 D2
da da
Aj (D1) Aj (D1)

Cmp-Based ADCs 11-40 Data-Conversion ICs; Jieh-Tsorng Wu


Subranging Operation
A1
L−
da D2
D1 A1 ( D1) ADC
M− sub
ADC DAC

ad da
A1 A1 D1 A1 ( D1) L−ADC Refs

da
2 A (+2)
ad
A (3)
da
1 A (+1)
ad
A (2)
da
0 0 A (0)
ad Input
A (1)
Over−Range
da
1 A (−1)
ad
A (0)
da
2 A (−2)

Cmp-Based ADCs 11-41 Data-Conversion ICs; Jieh-Tsorng Wu


Subranging Flash Quantization Architecture

• If G1 = 1, i.e., no amplification, the MDAC can be eliminated by switching the L-ADC’s


references instead.

• Both M-ADC and L-ADC are comparator banks.

• The L-ADC’s input range, VRB2 to VRT 2, must cover the of entire sub-range, including
margins for over-range.

• The resolution of the entire ADC is determined by the accuracy of the L-ADC and the
references.

• The accuracy of the M-ADC is irrelevant as long as the over-range margins of the
L-ADC is large enough.
da da da
• Let A1 (D1) = ∆A1 × D1 and A2 (D2) = ∆A2 × D2 + A1 (D1). Then

∆A1
 
A1 = Ada (D2) + Q1 = ∆A2 × D2 + ∆A1 × D1 + Q1 = ∆A2 · D + D2 + Q1
2 ∆A2 1

Cmp-Based ADCs 11-42 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS Subranging Flash ADC (Dingwall)

Vi 1
1
VR
2
1
1

2
VK VK 1
1

M−ADC
Comparator Bank
3 1 3 1 3 1 3 1

1 1 1 1
L−ADC
Comparator Bank

Cmp-Based ADCs 11-43 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS Subranging Flash ADC (Dingwall)

• Two-Stage quantized-feedforward architecture.


– The first-stage M-ADC has 2M − 1 comparators, and G1 = 1.
– The second-stage L-ADC has 2L − 1 comparators.
– For minimal design, Do has N = M + L bits.

• The S/H and the subtraction function is embedded in every comparator. Require no
additional subtracter or DAC.

• Comparators in both M-ADC and L-ADC need to have N-bit accuracy.

• The input range of the L-ADC can be extended to prevent over-ranging. The accuracy
requirement for the M-ADC can then be relaxed.

• Reference: A. Dingwall and V. Zazzu, “An 8-MHz CMOS subranging 8-bit A/D
converter,” JSSC 1985/12, pp. 1138–1143.

Cmp-Based ADCs 11-44 Data-Conversion ICs; Jieh-Tsorng Wu


Interpolation to Reduce Multiplexer Complexity

Vi 1
1
VR
2
1
1

2
VK VK 1
1

M−ADC
Comparator Bank
3 1 3 1

1 1
L−ADC
Comparator Bank

Cmp-Based ADCs 11-45 Data-Conversion ICs; Jieh-Tsorng Wu


Resistive Interpolation
Vi VR (x−3) Vi VR (x−1) Vi VR (x+1) Vi VR (x+3)

R1 R1 R1 R1 R1 R1 R1 R1

R1 R1 R1 R1 R1 R1 R1 R1

V o (x−3) V o (x−2) V o (x−1) V o (x) V o (x+1) V o (x+2) V o (x+3)

• Total area of transistors doesn’t change much if voltage gain and offset are
maintained.

• Bandwidth of the output network is reduced.

• Interpolation reduce the number of required preamplifiers, the number of required


reference voltages, and the number of switches in the subranging flash quantization
architecture. The decrease in layout complexity and capacitive loading for the
previous stage helps to achieve small die area and low-power operation.

Cmp-Based ADCs 11-46 Data-Conversion ICs; Jieh-Tsorng Wu


Current-Summation Interpolation
2VM V o (x) /R0
VDD VDD

Io (x−1) Io (x+1)
R0 R0 R0 R0

Vi
V o (x)

Vi Vi
VR (x−1) Vi VR (x+1)
VR (x−1) VR (x+1)
2 V

• Require VM > ∆V .

Cmp-Based ADCs 11-47 Data-Conversion ICs; Jieh-Tsorng Wu


Capacitive Interpolation and Averaging

1d
V1 C During φ2 phase,
2
V2
Vo A 
1d A Vo = × −(V1 − V2) − (V3 − V4)

V3 2
2 1
V4 C • No Vm requirement for the amplifiers.

V1
V3 Vo3 Vo3
V5

V3
Vo4 Vo4
V5

V3
V5 Vo5 Vo5
V7

Interpolation Interpolation and Averaging

Cmp-Based ADCs 11-48 Data-Conversion ICs; Jieh-Tsorng Wu


A 8-Bit Subranging ADC (Mulder)

• Performance set only by T/H, Rl ad , MUX, and FADC.

2
• J. Mulder, et. al., “A 21-mW 8-b 125-MSample/s ADC in 0.09-mm 0.13-µm CMOS,”
JSSC 2004/12, pp. 2116–2125.

Cmp-Based ADCs 11-49 Data-Conversion ICs; Jieh-Tsorng Wu


A 8-Bit Subranging ADC (Mulder) — CADC

Architecture
Preamplifier

Cmp-Based ADCs 11-50 Data-Conversion ICs; Jieh-Tsorng Wu


A 8-Bit Subranging ADC (Mulder) — FADC

• Pipeline operation.

• The M5-M6 cross-coupled


switches reduce the settling
time at A’s input when φ2 is
high.

Cmp-Based ADCs 11-51 Data-Conversion ICs; Jieh-Tsorng Wu


A 8-Bit Subranging ADC (Mulder) — Cascaded Averaging

Cmp-Based ADCs 11-52 Data-Conversion ICs; Jieh-Tsorng Wu


A 8-Bit Subranging ADC (Mulder) — MUX

VX (+16)
VR (+128) Vo (+16)
VX (−16)

VX (i ) = VR (16 · DC + i )
VX (+1)
VR (+1) Vo (+1)
DC ∈ {0, ±1, · · · , ±7}
VX (−1)

VX (0) • 257 references.


VR (0) MUX Vo (0)
VX (0)
• 33 comparators.
VX (−1)
VR (−1) Vo (−1)
VX (+1) • 16 subranges.

• 33 × 16 × 2 = 1056
VX (−16) MUX switches.
VR (+128) Vo (−16)
VX (+16)

Cmp-Based ADCs 11-53 Data-Conversion ICs; Jieh-Tsorng Wu


A 8-Bit Subranging ADC (Mulder) — Cascaded Interpolation
Amp A (9) Amp B (17) Amp C (17) Latches (33)
VX (+16) Va (+16) Vb (+16) Vc (+16)
VR (+128) Vo (+16)

Capacitive 2X interpolation and 2X Averaging


VX (−16)

Current−Summation 2X Inerpolation
Vb (+6) Vc (+6)
Vo (+6)
VX (+4) Va (+4) Vb (+4) Vc (+4)

Capacitive 2X Averaging
VR (+4) Vo (+4)
VX (−4) Vb (+2) Vc (+2)
Vo (+2)
VX (0) Va (0) Vb (0) Vc (0)
VR (0) MUX Vo (0)
VX (0) Vb (−2) Vc (−2)
Vo (−2)
VX (−4) Va (−4) Vb (−4) Vc (−4)
VR (−4) Vo (−4)
VX (+4) Vb (−6) Vc (−6)
Vo (−6)

VX (−16) Va (−16) Vb (−16) Vc (−16)


VR (+128) Vo (−16)
VX (+16)

• 65 references. 9 × 16 × 2 = 288 MUX switches.

Cmp-Based ADCs 11-54 Data-Conversion ICs; Jieh-Tsorng Wu


A 8-Bit Subranging ADC (Mulder) — Reference Ladder Interpolation
VX (+16) Va (+16)
VR (+128)
VX (−16) 2d
Vi C
1d
VX (+16)
Va (+4) 2d Va (+4)
VR (+16) Vi
1d 2
VX (0) C
VX (0) Va (0)
VR (0) MUX
VX (0) 2d
Vi C
Va (−4) 1d 2
VR (−16) VX (0)
2d Va (+4)
Vi
1d
VX (0) C
VX (−16) Va (−16)
VR (+128)
VX (+16)

• 17 references. 3 × 16 × 2 = 96 MUX switches.

• There is a ±2 LSB common-mode variation at the preamplifier’s input.

Cmp-Based ADCs 11-55 Data-Conversion ICs; Jieh-Tsorng Wu


A 10-Bit Subranging ADC (Brandt)

Cmp-Based ADCs 11-56 Data-Conversion ICs; Jieh-Tsorng Wu


A 10-Bit Subranging ADC (Brandt) — Comparator Bank

Cmp-Based ADCs 11-57 Data-Conversion ICs; Jieh-Tsorng Wu


A 10-Bit Subranging ADC (Brandt)

• Two-stage quantized-feedforward differential architecture.

• The voltage ranges are Ci n+ − Ci n− = [−2 ↔ +2] and Fi n+ − Fi n− = [0 ↔ +2].

• The absolute-value processing reduces the number of switches in the AMUXs by half.
In addition, the settling time of the AMUX outputs is also reduced due to the reduction
in output voltage swing and output capacitive loading.

• The interpolation scheme can reduce the number of “taps” from the reference ladder
and reduce the number of preamplifiers. It also attenuates front-end sources of DNL,
such as mismatches in the input sampling switches and resistor mismatch in the
reference ladder.

• Reference: B. Brandt and J. Lutsky, “A 75-mW, 10-b, 20-MSPS CMOS subranging


ADC with 9.5 effective bits at Nyquist,” JSSC 1999/12, pp. 1788–1795.

Cmp-Based ADCs 11-58 Data-Conversion ICs; Jieh-Tsorng Wu


Folder
VDD VDD VDD

R0 R0 R0 R0 R0 R0

Vo

Vi Vi Vi

VR (x−1) VR (x) VR (x+1)

Vo

0 Vi

• A folder is a zero-crossing multiplexer. Only for odd number of differential pairs.

• The accuracy of zero crossings is affected by the VOS of the differential pairs and
mismatches among tail currents.

Cmp-Based ADCs 11-59 Data-Conversion ICs; Jieh-Tsorng Wu


Signal Folding for Multiplexing of Zero Crossings
0 1 2 3 4 5 6 7 8
VRB VRT
Vi
0 3 6 1 4 7 2 5 8

V0 V1 V2

Circular−to−Binary Encoder Do

Dc
V0 V1 V2 Circular Code
000
0
100
1
110
2
111
3
011
4
001
5
000
6
100
7
110
8
Vi 111

Cmp-Based ADCs 11-60 Data-Conversion ICs; Jieh-Tsorng Wu


Folding Flash Quantization Architecture

Vi 2L
Folder

D1 D2
M− L−
ADC VRB VRT ADC

VRB VRT
M

D2

Vi

M−ADC Zero Crossings

Cmp-Based ADCs 11-61 Data-Conversion ICs; Jieh-Tsorng Wu


Folding Flash Quantization Architecture

• It is a also a subranging quantization process.

• The folder can generate its own output, and don’t have to wait for the result from the
M-ADC as in the case of subranging flash ADCs.

• A proper design of M-ADC’s zero crossings and digital output encoding can tolerate
±∆M /2 input offset of M-ADC’s comparators.

• The folder and the M-ADC usually share the same R-string for reference voltage
generation.

• The gain factor of the folders reduces the accuracy requirement for the L-ADC.

• The resolution of the entire ADC is mainly determined by the accuracy of the zero
crossings generated by folders.

Cmp-Based ADCs 11-62 Data-Conversion ICs; Jieh-Tsorng Wu


Cascaded Folding

0 1 2 3 4 5 6 7 8

0 3 6 1 4 7 2 5 8

Cmp-Based ADCs 11-63 Data-Conversion ICs; Jieh-Tsorng Wu


Cascaded Folding

• Too many folding in one stage makes signal amplification difficult.

• Require odd number of single-stage folding to maintain continuity.

• Identical folder can be used for all cascaded stages.

• Total number of zero crossings in not binary.

• Pipeline operation can be realized by using distributed interstage sample-and-hold


circuit.
– Longer time for settling per folder stage.
– The SHA’s accuracy spec. is lessened by the voltage gain of the preceding folder.

• Folding does not reduce the number of required preamplifiers.

Cmp-Based ADCs 11-64 Data-Conversion ICs; Jieh-Tsorng Wu


Cascaded Folding and R-Strings for Interpolation/Averaging

Input and Reference R−String

0 3 6 1 4 7 2 5 8

0 1 2 3 4 5 6 7 8

0 3 6 1 4 7 2 5 8

Interpolation and Averaging

• Interpolation reduce the total number of preamplifiers.

Cmp-Based ADCs 11-65 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS 10-Bit Folding ADC (Bult)

• Reference: K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS
2
ADC in 1-mm ,” JSSC 1997/12, pp. 1887–1895.

Cmp-Based ADCs 11-66 Data-Conversion ICs; Jieh-Tsorng Wu


High-Ro Transconductor

VDD

M3 M5 M6 M4

1
Ad m = gm1 ·
Vo gm3 − gm5
M1 M2
gm1 1
Acm = ·
Vi
1 + 2gm1ro7 gm3 + gm5

VBN M7

VSS

• Additional common-mode feedback is not required.

Cmp-Based ADCs 11-67 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS 13-Bit Pipelined Folding ADC (Choe)

Cmp-Based ADCs 11-68 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS 13-Bit Pipelined Folding ADC (Choe)

• The pipelined folding and interpolation scheme can achieve high degree of folding
without sacrificing the conversion speed.

• The front-end contains two SHAs and an analog MUX for 4-bit subranging operation.

• Each pipelined stage contains 7 folding amplifiers with a folding degree of 3, followed
by a 3x interpolator with 21 analog outputs.

• Input subranging reduces the number of folding amplifiers which need trimming.

• During normal A/D operation, one folding amplifier at a time is taken off-line for offset
trimming. Its corresponding output is filled in by the following interpolator.

• The folding amplifier’s offset voltage is measured by using a first-order delta-sigma


modulator followed by a digital accumulator.

• Reference: M. Choe, et. al., “A 13-b 40-Msamples/s CMOS pipelined folding ADC
with background offset trimming,”, JSSC 2000/12, pp. 1781–1790.

Cmp-Based ADCs 11-69 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS 1.6-GS/s 8-Bit Folding ADC (Taft)

Cmp-Based ADCs 11-70 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS 1.6-GS/s 8-Bit Folding ADC (Taft)

Differential-Difference Preamplifier

Cmp-Based ADCs 11-71 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS 1.6-GS/s 8-Bit Folding ADC (Taft)

3X Folder

Cmp-Based ADCs 11-72 Data-Conversion ICs; Jieh-Tsorng Wu


A CMOS 1.6-GS/s 8-Bit Folding ADC (Taft)

• Two-channel time-interleaved ADC.

• R. C. Taft, et. al., “A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26
ENOB at Nyquist frequency,” JSSC 2004/12, pp. 2107–2115.

Cmp-Based ADCs 11-73 Data-Conversion ICs; Jieh-Tsorng Wu


A 10-Bit Subranging ADC
D2 Do
Fine
V1
ADC 6 10

63 VRF

Encoder
Coarse
MUX
ADC
D1

5
31 VRC 1023
VRT VRB

• Require a complex 1023-to-63 analog multiplexer (MUX), which hinders operating


speed.

Cmp-Based ADCs 11-74 Data-Conversion ICs; Jieh-Tsorng Wu


A 10-Bit Two-Step ADC
Residue Amplifier

V2 D2 Do
Fine
V1 A
ADC 6 10

Encoder
Vda

Coarse
MUX
ADC
D1

5
31 VRC 32 63 VRF
VRT VRB

• Require a residue amplifier.

Cmp-Based ADCs 11-75 Data-Conversion ICs; Jieh-Tsorng Wu


Two-Step Operation
A2
L−
A1
Asg ADC
G2
D1
M− sub da
A1 ( D1)
ADC DAC

ad da L−ADC
A1 A1 D1 A1 ( D1) Asg A2
Refs
da
2 A (+2)
ad
A (3)
da
1 A (+1)
ad
A (2)
da
0 0 A (0) 0 0
ad
A (1)
da
1 A (−1)
ad
A (0)
da
2 A (−2)

Cmp-Based ADCs 11-76 Data-Conversion ICs; Jieh-Tsorng Wu


A Switched-Capacitor (SC) 100-MS/s 10-Bit Two-Step ADC (Chung)
Residue Amplifier
φ1 Calibration
φ1 Processor
V1 Cs c
D2 D2 Do
Fine
DCP
V2 ADC 6 6 10

φ2

Encoder
Vda q
D1
Coarse
RDAC q
ADC
D1

5
33 VRC 96 65 VRF
VDD VSS

φ1
φ2

• Reference: Y-H Chung and J-T Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE JSSC,
2010/11, pp. 2217-2226,

Cmp-Based ADCs 11-77 Data-Conversion ICs; Jieh-Tsorng Wu


A SC 100-MS/s 10-Bit Two-Step ADC (Chung) — Coarse Comparator

φ1 φ1a φc
VDD
V1 Vcm
S1 C1 S3 Va
φc M9 M10 φc
φ2 Dc
VRC [n] Vc
S2 Dc,p Dc,n
Vcm Vos Latch

Ip M11 M12
up φ1a
1
Dc
φ1
dn Va,p M1 M2 Va,n Vcm M5 M6 Vc
0 φ2
C2 VDD M3 VDD M7
In φc
φc M4 φc M8

VSS VSS
Offset−Calibration Charge Pump

• Latch comparator with offset-calibration charge pump.

Cmp-Based ADCs 11-78 Data-Conversion ICs; Jieh-Tsorng Wu


A SC 100-MS/s 10-Bit Two-Step ADC (Chung) — Residue Amplifier
VDD

Vb1 M5

R1 R2
V2,p M3 M4 V2,n
Vb2
φ1 φ1a φ1a φ1
V1,p V1,n
S1 Cs1 S5 S6 Cs2 S2
M1 M2
φ2 φ2
Vda,p Vda,n
S3 V2,p S4
Vb3 M0a M0b CMFB
V2,n
VSS VSS

• Open-loop amplification. Use digital calibration to correct nonlinearity.

Cmp-Based ADCs 11-79 Data-Conversion ICs; Jieh-Tsorng Wu


A SC 100-MS/s 10-Bit Two-Step ADC (Chung) — Chip

CMOS Technology 90nm


Supply Voltage (V) 1.0
Resolution (bit) 10
Sampling Rate (MHz) 100
Input Range (Vpp differential) 2.0
Input Loading (pF) 1.2
DNL (LSB) +0.6/−0.5
INL (LSB) +0.9/−0.9
SNDR (dB) (Fi n=1 MHz) 58
SNDR (dB) (Fi n=50 MHz) 53.7
SFDR (dB) (Fi n=1 MHz) 75
SFDR (dB) (Fi n=50 MHz) 64
Power Consumption (mW) 6
FOM1 (fJ/conv.-step) 92
FOM2 (fJ·V/conv.-step) 100
2
Active Area (mm ) 0.36

Cmp-Based ADCs 11-80 Data-Conversion ICs; Jieh-Tsorng Wu