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© Synopsys 2013 1
CONFIDENTIAL INFORMATION
The following material is being disclosed to you pursuant to a non-
disclosure agreement between you or your employer and
Synopsys. Information disclosed in this presentation shall be used
only as permitted under such an agreement.
LEGAL NOTICE
Information contained in this presentation reflects Synopsys plans
as of the date of this presentation. Such plans are subject to
completion and are subject to change. Products may be offered
and purchased only pursuant to an authorized quote and purchase
order. Synopsys is not obligated to develop the software with the
features and functionality discussed in the materials.
© Synopsys 2013 2
Topics
New enable_primetime_icc_consistency_settings command
Tcl 8.5 version support
Changes in CRPR default
Transition calculation variable changes
64-bit SPEF node number support
Precedence rule for max_capacitance constraints
Clock exclusivity relationship for signal integrity analysis
Interclock hold checking for unexpandable clocks
© Synopsys 2013 3
Variable and Timing Consistency
PrimeTime and IC Compiler
• PrimeTime and IC Compiler have new capabilities to align variables for
consistency
• Two new commands facilitate correlation between PrimeTime and IC
Compiler
• Focus is postroute design correlation
© Synopsys 2013 4
Definition of Variables
• Flow variables
– Special variables that enable a particular flow
– Common in both tools
– By default, enable_primetime_icc_consistency_settings does
not change flow variables to the recommended value (unless you use the
–all option)
– Example: AOCV and signal integrity
• Feature-gap variables
– Special variables that are unique to each tool
– By default, enable_primetime_icc_consistency_settings does
not change feature-gap variables to the recommended value (unless you
use the –all option)
– Example: PrimeTime timing_all_clocks_propagated variable
© Synopsys 2013 5
New enable_primetime_icc_consistency_settings
Command
© Synopsys 2013 6
Example in PrimeTime
enable_primetime_icc_consistency_settings
Variable changed Original Value
Changed
pt_shell> enable_primetime_icc_consistency_settings to Value
set rc_degrade_min_slew_when_rd_less_than_rnet false
# rc_degrade_min_slew_when_rd_less_than_rnet changed to true
set timing_clock_gating_propagate_enable true
# timing_clock_gating_propagate_enable changed to false
1
pt_shell> printvar rc_degrade_min_slew_when_rd_less_than_rnet
rc_degrade_min_slew_when_rd_less_than_rnet = “true”
© Synopsys 2013 8
Variable Default Changes for CRPR
– I-2013.12 default
timing_remove_clock_reconvergence_pessimism = "true"
© Synopsys 2013 9
New Variable for Transition Calculation
© Synopsys 2013 10
64-Bit SPEF Node Number Support
Previous releases
• Supported only 32-bit SPEF node numbers
• 64-bit SPEF node numbers resulted in errors
• Error: Semantic error near '2148932200':
expected pos_integer in node name at line
4827 in file ‘TOP.spef'. (SPFP-116)
I-2013.12
• 64-bit versions of PrimeTime support 64-bit SPEF node
numbers
• 32-bit versions of PrimeTime support 32-bit SPEF node
numbers
© Synopsys 2013 11
Precedence Rule for max_capacitance
Constraints
• New variable in I-2013.12 release
– set timing_enable_max_cap_precedence false
© Synopsys 2013 12
Clock Exclusivity Relationship for
Signal Integrity Analysis
• A clock exclusivity relationship on a master clock does
not automatically propagate to their generated clocks
– If CLKA is physically exclusive to CLKB, then the paths between
CLKA and generated clocks of CLKB are not considered
physically exclusive.
– PrimeTime SI crosstalk delay and noise analysis also does not
consider CLKA and generated clock of CLKB as physically
exclusive
© Synopsys 2013 13
Interclock Hold Checking for
Unexpandable Clocks
ClkA
Hold check between Hold check between
correct edges incorrect edges
ClkB
Common base period when
expansion limits reached
© Synopsys 2013 14