1] What is MBIST & its need?

BIST is a structured DFT technique that places a device’s testing function within the device
itself. BIST structures can test various types of circuitry, from random logic to regular
structures such as memory devices.
As deep submicron ASIC and IC technology evolves, these devices contain greater numbers
of embedded memories. Consequently, the industry requires an automated test strategy for
these memories. Classic DFT and ATPG approaches can neither support memory test nor
provide a complete solution to the challenges of systems-on-silicon. The types of faults that
occur in memory structures differ from those in standard logic design. Memory based address
faults, stuck-at faults, transition faults, and coupling faults within the cell array require
different fault models and algorithms than those supported by scan techniques.

By building self-test logic into the design itself, MBIST provides a solution to many of these
test problems. MBIST creates an on-chip BIST structure that generates and applies patterns
and compares chip responses. Self-testing provides a number of benefits. First, placing the
test circuitry on the chip reduces external tester time and expense. Second, it minimizes the
difficulty of testing embedded circuitry by providing system-level control signals that run,
and report the status of, the test operation. Third, the on-chip circuitry generates the test
stimulus, thus eliminating or reducing expensive test pattern generation time. This, in turn,
eliminates or reduces the amount of required external test data storage. Also, the silicon area
overhead for the BIST structure is relatively small compared to the size of these deep
submicron devices.

2] Types of memories?
1) SRAM
2) ROM
3) DRAM
4) EEPROM
3] How do you group the memories?
We group memories according to-
1) Size of the memory
2) Frequency of the memory

4] How do you decide the number of controllers?

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Numbers of controllers depends on the how many memories is in the given logic, if there is
more than one memory we have to check the size of both memory is same or not.
1) If there is only one memory we use only one controller for them.
2) If there is more than one memory we check the sizes of memory, if the sizes of both
memory are same we can use a single controller for them (parallel testing). If the sizes
of both memories are different, it depends on designer to place a single or different
controller for both memories.
3) Example – suppose one memory depth is 10 and other memory depth is 100, we can
use one controller for both memories, that controller generate 100 pattern (for checking
max memory depth) and run for both memories, but for first memory [10 depth] 90
pattern is useless, which is a wastage of money and time. So for betterment we use two
controllers- one generate 10 patterns and other 100 patterns for both 10 and 100 depth
memories respectively.
4) Routing issue- suppose system has two memories both are of same size, but both are
far from each other, we can’t use same controller for them because it creates routing
problem, so in this case we use separate controller for them.
5) Frequency – if the memories are of same size but working on different frequencies for
that we need separate controllers.

5] MBIST hook-up with Memory, Collar logic and Functional logic

6] How does the controller work? Explain with diagram?

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To test for memory-specific faults, memory BIST implements a finite state machine that
implements algorithms to generate stimulus to test the memory. This is referred to as the
BIST controller and typically contains a comparator that compares the memory’s actual
response with the known good circuit response.

The BIST controller supplies two output signals to inform the system of the test process
status: a test completes (tst_done) signal and a pass/fail (fail_h) flag. The tst_done signal is
asserted when testing has finished. The fail_h flag is asserted, and remains asserted for the
remainder of the test, if the test process found any system failures.

MBIST provides the ability to add this diagnostic functionality to the BIST controller so that
the failing data is scanned out of the device on every miscompare, with a minimal impact on
silicon area and routing overhead. The architecture generated by MBIST diagnostic capability
includes the use of the BIST controller’s hold capability (hold_l) as well as generating an
additional input port (debugz) and output port (scan_out).

BIST Controller Inputs

This section describes each of the BIST controller inputs and their functions.
-System addresses (sys_addr) — The system address inputs to the memory array.
-System data inputs (sys_di) —The system data inputs to the memory array.
-System write enables (sys_wen) — The system write enables that control memory read/write
operations.
-Reset (rst_l) — An active-low signal that resets the finite state machine.
-Clock (clk) — The clock for the finite BIST controller.
-Hold (hold_l) — An optional active-low signal that forces the BIST controller to stop
processing and maintain its current state.
-Test (test_h) — An active-high signal that enables the BIST controller. When test_h is high,
self-test is in progress.
-Diagnostic Mode (debugz) — (Debug only) The diagnostic mode enable signal. When
debugz is low, the BIST controller performs the default memory tests. When debugz is high,
the diagnostic mode is enabled. Works with hold_l and scan_out.

BIST Controller Outputs

This section describes each of the BIST controller outputs and their functions.
-Write enable (wen) — The output that drives the write enable of the memory(s) under test.
Other available control signals include output enable, read enable, chip enable, and clock.
-Test Done (tst_done) — When high, indicates completion of the self-test operation.
-Fail (fail_h) — The pass/fail flag for the BIST controller.
-Data Outputs (DI_n) — The memory data inputs.
-Address Outputs (AO_n) — The memory input addresses.
-Scan Output (scan_out) — (Debug only) The scan output port for diagnosing serially
scanned out failing data. Works with hold_l and debugz.
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7] Understanding different Memory Faults and Algorithms to cover them?
Memories fail in a number of different ways. The three main parts, address decode logic,
memory cell array, and read/write logic, can each have flaws that cause the device to fail.
Memory testing, while similar to random logic testing, focuses on testing for these memory-
specific failures.
The basic types of memory faults include stuck-at, transition, coupling, and Neighbourhood
pattern sensitive.

Stuck-at Faults
A memory fails if one of its control signals or memory cells remains stuck at a particular
value. Stuck-at faults model this behaviour, where a signal or cell appears to be tied to power
(stuck-at-1) or ground (stuck-at-0).
To detect stuck-at faults, you must place the value opposite to that of the stuck-at fault at the
fault location. To detect all stuck-at-1 faults, you must place 0s at all fault locations. To detect
all stuck-at-0 faults, you must place 1s at all fault locations.
Transition Faults
A memory fails if one of its control signals or memory cells cannot make the transition from
either 0 to 1 or 1 to 0. Figure shows a cell that might behave normally when a test writes and
then reads a 1. It may even transition properly from 1 to 0. However, when undergoing
a 0->1 transition, the cell could remain at 0—exhibiting stuck-at-0 behaviour from that point
on. However, a stuck-at-0 test might not detect this fault if the cell was at 1 originally.

To detect all transition faults in the memory array, a test must write a 1, followed by a 0, and
then read (detects up transition). The test must then write a 0, followed by a 1 and then read
(detects down transition).

Coupling Faults
Memories also fail when a write operation in one cell influences the value in another cell.
Coupling faults model this behavior. Coupling faults fall into several categories: inversion,
idempotent, bridging, and state. Inversion coupling faults, commonly referred to as CFins,
occur when one cell’s transition causes inversion of another cell’s value. For example, a 0->1
transition in cell_n causes the value in cell_m to invert its state.

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Idempotent coupling faults, commonly referred to as CFids, occur when one cell’s transition
forces a particular value onto another cell. For example, a 0->1 transition in cell_n causes the
value of cell_m to change to 1 if the previous value was 0. However, if the previous value
was 1, the cell remains a 1.

Bridge coupling faults (BFs) occur when a short, or bridge, exists between two or more cells
or signals. In this case, a particular logic value triggers the faulty behavior, rather than a
transition.
State coupling faults, abbreviated as SCFs, occur when a certain state in one cell causes
another specific state in another cell. For example, a 0 value in cell i causes a 1 value in cell j.
Neighbourhood Pattern Sensitive Faults
Another way in which memory cells can fail involves a write operation on a group of
surrounding cells that affects the values of one or more neighboring cells.

Memory BIST Algorithms

There are memory test algorithms known to detect the majority of commonly occurring faults
in memories.

March C
First presented at the ITC in 1982, the March C algorithm, and its modifications, is now the
most popular algorithm for memory testing.
This algorithm, which consists of 11 operations (11n), writes and reads words of 0s, followed
by writing/reading words of 1s, in both descending and ascending address spaces
Specifically, the algorithm consists of the following steps:

1. Write 0s to all locations starting at the lowest address (initialization).

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2. Read 0 at lowest address, write 1 at lowest address, repeating this series of operations until
reaching the highest address.
3. Read 1 at lowest address, write 0 at lowest address, repeating this series of operations until
reaching the highest address.
4. Read 0 from the lowest address to the highest address.
5. Read 0 at highest address, write 1 at highest address, repeating this series of operations
until reaching the lowest address.
6. Read 1 at highest address, write 0 at highest address, repeating this series of operations
until reaching the lowest address.

The March C Algorithm detects the following faults:

stuck-at
transition
coupling - unlinked idempotent and inversion, and other coupling faults on bit-oriented
addresses

7) How do you corrupt the memories? What is memory diagnosis ?

The BIST controller supplies two output signals to inform the system of the test process
status: a test complete (tst_done) signal and a pass/fail (fail_h) flag. The tst_done signal is
asserted when testing has finished. The fail_h flag is asserted, and remains asserted for the
remainder of the test, if the test process found any system failures.
Although the indication of a failure is enough to indicate a faulty memory and ensure that the
part is rejected, it is often necessary to diagnose the failures to identify the cause of the
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failures. In this case, data is needed to indicate exactly which patterns caused the miscompare
along with the functionality to diagnose the data to identify the faults present in the
memories.
MBISTArchitect provides the ability to add this diagnostic functionality to the BIST
controller so that the failing data is scanned out of the device on every miscompare, with a
minimal impact on silicon area and routing overhead. The architecture generated by
MBISTArchitect’s diagnostic capability includes the use of the BIST controller’s hold
capability (hold_l) as well as generating an additional input port (debugz) and output port
(scan_out).

By default, MBIST Architect will indicate a failure to ensure that the part is rejected,
however, it is often necessary to diagnose the failures to identify the cause of the failures. In
this case, data is needed to indicate exactly which patterns caused the miscompare, and this
data can be processed to identify the faults present in the memories.
In order to extract the failing data, the BIST controller requires the controller’s hold
capability as well as additional functionality to download the failing data on every occurrence
of a miscompare. MBISTArchitect provides the ability to add this functionality to the BIST
controller so that the failing data is scanned out of the device on every miscompare, with a
minimal impact on silicon area and routing overhead.
When the debug diagnostics is used, the BIST controller operates in one of two modes
controlled by debugz. The modes and operation of the fail_h and scan_out ports is as
follows:
Diagnostic Mode (debugz) — (Debug only) The diagnostic mode enable signal. When
debugz is low, the BIST controller performs the default memory tests. When debugz is high,
the diagnostic mode is enabled. Works with hold_l and scan_out.

Normal Mode (debugz = ‘0’)

When debugz is set to ‘0’, the BIST controller performs the default test. In this mode, the
scan_out port is set to ‘0’, as no fail data is downloaded. The fail_h port is asserted on the
first failure and remains high for the remainder of the test.

Debug Mode (debugz = ‘1’)

When debugz is set to ‘1’, the diagnostic mode is enabled. In this mode, a miscompare will
suspend the operation of the BIST controller, and the failing data will be serially scanned out
of the controller through scan_out .Once the failing data has been scanned out, the BIST
controller will resume the test. The scan out operation will repeat on every occurrence of a
miscompare.

8) Diff between RAM & ROM BIST

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RAM fail in a number of different ways. The three main parts, address decode Logic,
memory cell array, and read/write logic.
While BIST for Ram will write, read, compare or compress the read data, in RAM we don’t
know what data will be inside the memory cell, what maybe the address, we generate the test
patterns and apply to the memory under test then compare the output result with the result of
a known good memory. For rest information check answer no.6.
The MBIST for ROM will only read and compress the read data into a signature [MISR].
The signature for ROM is precalculated using the data stored in the ROM.

9) What is area overhead because of MBIST ?

Obviously area increases because for MBIST we have to add controller logic,which is made
up of different gates, sometimes we add compressor logic too which occupy more area.