Chapter 9

Asynchronous Sequential Circuits

9.1 Introduction
Sequential circuits consist of a combinational circuit to which storage elements are
connected to form a feedback path. Sequential circuits are specified by a time sequence of inputs,
outputs and internal states. Two types of sequential circuits are synchronous and asynchronous.
Synchronous sequential circuit discussed in the last two chapters.

Figure 9.1

Synchronous sequential circuits are synchronized by clock pulses. Clock pulses mean
periodic train of pulses. So synchronous sequential circuits output will be determined at either
positive edge of clock pulses or negative edge of clock pulses. Without giving the clock pulses
even if we change the inputs to the synchronous sequential circuit, there will not be any change
in the outputs of the circuit. But synchronous sequential circuits are much easy to design.

Figure 9.2

In asynchronous sequential circuit the outputs can change at any instant of time as soon
as changing the inputs. There is no need of clock pulses in asynchronous sequential circuits.
There is no need of memory elements to store the previous outputs. The propagation delays in
the logic gates are used and the outputs are fed back to inputs. But the design process of
asynchronous sequential circuits will be harder compared to synchronous sequential circuits
design because of timing problems.
 Figure 9.3

Why should we go for designing asynchronous sequential circuit while designing

synchronous sequential circuit is much easier than? Because we have several advantages in the
asynchronous sequential circuits design rather than synchronous sequential circuits. They are
Asynchronous sequential circuit is faster than synchronous sequential circuit. So when
speed of operation is important we have to choose asynchronous design. Because
asynchronous circuits respond quickly without waiting for clock pulses.
Asynchronous sequential circuits are simpler than synchronous sequential circuits.
Because only few components required in asynchronous sequential circuits. The
propagation delay of logic gates can be used as memory and no need to use memory
elements.
Asynchronous sequential circuits may be used where the inputs are changing independent
of clock pulses.
Asynchronous sequential circuits may be used in systems which use independent clock
not depending upon the clock signal of other systems.

We will define the terms used in asynchronous sequential circuits which will be useful
while analyzing and designing asynchronous sequential circuits. As like in the combinational
circuits, we can have n number of inputs and m number of outputs ie., we can have any number
of inputs and outputs. As we have already said there is no need to use separate memory element
in asynchronous sequential circuits. The gate delay can be used as storage process which can be
fed back to inputs. There are k numbers of secondary variables (denoted by small y in the figure)
which are similar to current state in the synchronous sequential circuit design. Also there are k
numbers of excitation variables (denoted by big Y) which are similar to next state in the
synchronous sequential circuit design. When the circuit is in stable state, the secondary and
excitation variables will be equal. When you change the inputs, due to propagation delay of gates
it may take some delay to change the output. The change in the output may change t he excitation
variable value. At this time the value in the excitation variable and secondary variable may be
different. This is called as unstable state. So change in the secondary variable again may change
the output and excitation variable. This process continues for a while and whenever the
excitation variables and secondary variables are getting the same value, the circuits take the
stable state.
There are some conditions while operating the asynchronous sequential circuits. Only one
input can be changed at a time. No more than one input variables changed simultaneously. There
should be time between two input changes so that the asynchronous sequential circuits to take
stable states. This is called as fundamental mode operations of the circuit.

9.2 Analysis procedure

Analysis procedure means given the circuit in hand, we have to say the function of the
circuits. The procedure is same as we have discussed in the analysis of combinational circuits in
chapter4. But here we have to include the secondary and excitation variables in the analysis
process. First we review the analysis procedure once, and then by taking examples we will
discuss the analysis process.
Take the circuit to be analyzed and mark all the input and output variables by assigning
some label.
Find out the feedback paths. Feedback means the outputs which are fed back as inputs to
the circuit. Note that feedback path need not be taken as the output.
Assign label to the feedback path. The output is marked by Y (big Y) which is excitation
variable. In the feedback path the same line, the input is marked by y (small y) which is
secondary variable.
Write Boolean function for each and every output and excitation variable as a function of
inputs and secondary variable.
Draw the map for each Y and output. Combine all the Ys and output in a single map.
Circle those values of Y which are equal to the value of y in the same row. The circled
ones are stable states. From stable states we can say the function of the circuit.
Example: Analyze the following asynchronous sequential circuit.

Figure 9.4

By looking the circuit we can say that there is only one input in the circuit and there is no
output in the circuit. There are two feedback paths in the circuit. Mark the input as x and in the
feedback path the output lines are marked with Y1 and Y2 as excitation variable. The feedback
inputs are marked with y1 and y2 which are secondary variables.

Figure 9.5

Let us write the Boolean functions for the excitation variables Y1 and Y2 as a function of
the input x and secondary variables y1, y2.
Y1 = xy1 + x’y2.
Y2 = x’y2 + xy1’
Draw the map for each and every excitation variable and the output. But here we have
only excitation variables Y1 and Y2. So draw map for Y1 and Y2 separately.
 Figure 9.6

Combine the maps for excitation variables and the output and draw the transition table.
But in this example we have only excitation variables Y1 and Y2. So combine these two maps
and draw the table called as transition table.

Figure 9.7

Circle the stable states where the secondary variables and excitation variables have the
same value in a single row.

Figure 9.8
 As there are two secondary and excitation variables, there are four possible states 00, 01,
10, 11. The states can be assigned by label like 00 → a, 01 → b, 11→c, 10→d. After assigning
label to the state, redraw the above table which is called as flow table.

Figure 9.9

This flow table can also be called as primitive flow table as each row contains only one
stable state. Using transition table or flow table, we can draw state table as follow.
Table 9.1

Next State
Present State
x= 0 x=1

0 0 0 0 0 1

0 1 1 1 0 1

1 0 0 0 1 0

1 1 1 1 1 0
 Table 9.2

Next State
Present State
x= 0 x=1

a a b

b c b

d a d

c c d

9.3 Circuits with Latches

Usually the asynchronous sequential circuit is using one or more feedback loops. There
are no real delay elements in the asynchronous sequential circuit. It is more convenient to
employ memory element in the asynchronous sequential circuit. By using physical memory
elements in the asynchronous sequential circuit we can produce orderly pattern in the logic
diagram.
SR latch can be used as memory element in the design of asynchronous sequential circuit.
SR latch itself is an asynchronous sequential circuit. Let us analyze SR latch in this section.
SR Latch with NOR gates:

Figure 9.10

The circuit shows the SR latch diagram as we have discussed in the chapter 7. Let us
assume R and S are inputs to this asynchronous sequential circuit and there is a feedback path
connecting the output to the input Q = Y. So Y = Q is excitation variable here and q = y is
secondary variable. Using these notations let us redraw the circuit. Note that we have omitted Q’
as it is just complemented version of Q.
 Figure 9.11

To analyze this asynchronous sequential circuit, follow the analysis procedure of

asynchronous sequential circuit just discussed in this chapter. We find the one feedback path in
this circuit, the inputs are labeled with R, S and excitation variable with Y, secondary variable
with y. Now write the Boolean function for excitation variable Y.

Y = ((S+y)’ + R)’ = (S’y’+R)’ = (S’y’)’R’ = (S+y)R’ = SR’+yR’

Using this Boolean function, draw the transition table for the SR latch circuit.

Figure 9.12

From the transition table we can see that when SR = 00, the excitation variable will be in
the stable state. The output stays in the previous output either 0 or 1. If SR = 01, the output will
be 0, regardless of previous output. If SR = 11, the output will be 0 again regardless of previous
output. If SR = 10, then the output will be 1 either previous output 0 or 1.
 Table 9.3

Inputs
Present State S Input R Next State
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

SR Latch with NAND gates:

Figure 9.13

The circuit shows the SR latch diagram as we have discussed in the chapter 7. Let us
assume R and S are inputs to this asynchronous sequential circuit and there is a feedback path
connecting the output to the input Q = Y. So Y = Q is excitation variable here and q = y is
secondary variable. Using these notations let us redraw the circuit. Note that we have omitted Q’
as it is just complemented version of Q.

Figure 9.14
 We find the one feedback path in this circuit, the inputs are labeled with R, S and
excitation variable with Y, secondary variab le with y. Now write the Boolean function for
excitation variable Y.
Y = ((Ry)’.S)’ = (Ry + S’)
Using this Boolean function, draw the transition table for the SR latch circuit.

Figure 9.15

Here we remember that SR latch using NAND gates is called as S’R’ latch. So if SR = 00
means S’R’ = 11. So for S’R’ = 11, the output will be 1 regardless of previous outputs. if SR =
01 which means S’R’ = 10. So for S’R’ = 10, the output is 1 either previo us output is 1 or 0. If
SR = 11, then S’R’ = 00, so there is no change in the previous output. If SR = 10, then S’R’ = 01
which produces the output 0 either the previous output is 1 or 0.

9.4 Reduction of State and Flow tables

Two states are equivalent if they have the same output and go to the same next state for
each possible input. Such states can be considered as equal states and the state table can be
reduced by merging the states.
For example, consider the following state table.
Table 9.4

Next State Output

Present
State X=0 X=1 X=0 X=1

a c b 0 1

b d a 0 1

c a d 1 0

d b d 1 0
 State reduction procedure is similar in both synchronous and asynchronous sequential
circuits design. There are two methods in the state reduction procedure. They are called as
implication table and compatible pairs.
Implication table
For completely specified table, the implication method can be used to reduce the state
table. Let us take an example for implication method.
Table 9.5

Next State Output

Present
State
x=0 x=1 x=0 x=1

a d b 0 0
b e a 0 0
c g f 0 1
d a d 1 0
e a d 1 0
f c b 0 0
g a e 1 0
Step1: Build implication chart. Put tick in the nodes which are absolutely equal. For example
state d and e are equal. Delete the nodes which are definitely unequal. For example state a and
state c are definitely not going to be equal because both states getting different output.
Table 9.6

c × ×

d × × ×

e × × × √

f × × ×

g × × × ×

a b c d e f
Step2: Check the blank nodes. Write the condition(s) for that node to be equal. For example (a,b)
will be equal if (d,e) are equal. (a,f) will be equal if (c,d) are equal.

Table 9.7

b d,e

c × ×

d × × ×

e × × × √

f c,d e,c × × ×
a,b

g × × × d,e d,e ×

a b c d e f

Step3: In the first step we come to know that d,e are only equal node. By putting the equal states
d,e we get the following implications.

Table 9.8

b d,e √

c × ×

d × × ×

e × × × √

f c,d × e,c × × × ×
a,b

g × × × d,e√ d,e√ ×

a b c d e f

There are four nodes which have been ticked. They are (a,b), (d,e), (d,g),(e,g). From the
last three pair of equal states (d,e), (d,g), (e,g) we can say that the states d, e, g are equal.
 Figure 9.16

From the closure conditions it is known that (d,e,g) are equal. There is an implied state
(a,b). So the reduced state table is given as
Table 9.9

Next State Output

Present
State
x=0 x=1 x=0 x=1

a d a 0 0
c d f 0 1
d a d 1 0
f c a 0 0

9.5 Design procedure

Designing asynchronous sequential circuit is just reverse process of analysis procedure.
Given the specifications required, we have to design the circuit satisfying the specifications using
the following design procedure.
Obtain the primitive flow table from the given design specifications. Or
sometimes we may be given state table or state diagram. If so then we have to
convert it into primitive flow table.
Reduce the primitive flow table if possible by merging the rows which are equal
in the primitive flow table.
Assign the binary state variable to each row of the reduced primitive flow table to
obtain the transition table.
Assign the output values to the dashes (which will be taken as don’t care
conditions) associated with the unstable states to obtain the output map.
 Simplify the Boolean functions of the excitation variable and output using map
procedure.
Draw the logic diagram using simplified Boolean functions.
Let us take some examples to understand the design of asynchronous sequential circuit
design.
Example: Design of gated latch.
Specifications: Design a gated latch circuit which have two inputs G and D and one output Q.
The output Q retains its previous value if the input G = 0 regardless of the input D. The output Q
will follow the input D if the gated input G = 1.
Using the given specifications first draw the state table.
Table 9.10

Input Output
State Comments
D G Q

a 0 1 0 Q = D because G = 1

b 1 1 1 Q = D because G = 1

c 0 0 0 After states a or d

d 1 0 0 After state c only because DG = 01 cannot be

changed to 10 in fundamental mode operation

e 1 0 1 After states b or f

f 0 0 1 After state e only because DG = 11 cannot be

changed to 00 in fundamental mode operation

Obtain the flow table by listing all possible states. Put dash for the inputs which cannot
be switched over simultaneously in the fundamental mode operation. For example in state “a”
the inputs are 01 which cannot be changed to 10. So put dash for the inputs 10. Likewise for all
states fill dash with impossible inputs.
Also put dash for the unstable outputs. Remaining states can be filled by looking the state
table.
 Figure 9.17

Two or more rows can be merged into one row if there are equal states and output in
every column. For example the states a, c, d and b, e, f are separated from the flow table and
given below.

Figure 9.18

We can say that the states a, c and d are equal by looking each and every column of the
flow table. In the similar manner the states b, e and f are equal states as all the columns in the
flow tables are equal. Note that dash indicates don’t care conditions which could be taken as any
state or output. By merging equal states redraw the flow table.

Figure 9.19

Now we can replace the states c and by a. As well we can replace the states e and f by b.
 Figure 9.20

Next step assign binary value to each and every states. As we have two states here, 0 can
be assigned to state a and 1 can be assigned to state b.

Figure 9.21

Now reduce the table by using K-map procedure.

Figure 9.22

Write the simplified Boolean function for excitation variable Y and output Q.
Y = DG + yG’ Q = DG + yG’
The output and excitation variables are same. Draw the logic diagram for this Boolean
function.
 Figure 9.23

Example: Design a negative edge triggered T flip flop.

Specifications of T flip flop: We have two inputs for T flip flop. One is T(toggle) input and
another is C(clock) input. The circuit has one output Q, which is toggled between two states if
the input T = 1. Otherwise the output will remain in the previous state.
Table 9.11

Input Output
State Comments
T C Q

a 1 1 0 Initial output is 0

b 1 0 1 After state a

c 1 1 1 Initial output is 1

d 1 0 0 After state c

e 0 0 0 After state d or f

f 0 1 0 After state e or f

g 0 0 1 After state b or h

h 0 1 1 After state g or c

From the state table, build the flow table as we have discussed in the last example.
 Figure 9.24

Now we have to reduce the flow table by using implication table and compatible pairs.
Table 9.12

Using implication table we know that (a, f), (b, g), (b, h), (c, h), (d, e), (d, f), (e, f), (g, h)
are equal states.
 Figure 9.25

There are two compatible pairs (b, g, h) and (d, e, f). So the reduced states are (a, f),
(b, g, h), (c, h), (d, e, f). So the reduced flow table is given as

Figure 9.26

Assign binary values to each state. After reducing the flow table we have only four states.
Therefore binary values a = 00, b = 01, c = 11 and d = 10 assigned.

Figure 9.27
 Reduce the Boolean functions for excitation variables Y1Y2 and output Q using K -map
procedure.

Figure 9.28

The reduced Boolean functions are Y1 = y2TC + y1T’C + y1TC’ + y2’T’C’

Y2 = y2T’ + y2C + y1’TC’
Q = y2
Draw the negative edge triggered T flip flop circuits using the above Boolean functions.
 Figure 9.29

9.6 Race Free State assignment

Race Conditions
When one input of the asynchronous sequential circuit changes, two or more binary state
variables may change value. If unequal delay is encountered between the binary states, then we
cannot predict the state sequence. This is called as race conditions. Races ca n be divided into
critical and non-critical races.
Non-critical races

Figure 9.30

In the transition table shown, we have two total stable states. 000 is one total stable state
along with the input x = 0. 111 is another total stable state along with the input x = 1. Initially
assume the circuit is in the total stable state 000. If the input x is changed from 0 to 1, then the
state should change from 00 to 11. Because of unequal delay between two binary states, 00 to 11
transition may occur in two ways. If y2 is faster than y1, then 00 will change to 01 first and then
01 to 11. Or if y1 is faster than y2, then 00 will change to 10 first and then 10 to 11. From this
transition diagram, however the final output will end at the stable state 11 even if the
intermediate transition goes to 10 or 01. These types of races are called as non-critical races.
Let us see another example for non-critical race.

Figure 9.31

In this example, total stable states are 000 and 011. Initially assume the circuit is in total
stable state 000. If the input changes from 0 to 1, then y1 y2 should go to 11 and from 11, it goes
to stable state 01. If unequal delay encounters, then one possibility is 00 changed to 01. Then it
will stay in the 01 i.e. final stable state also. Another possibility is 00 changed to 10. In this 10
→11 → 01 transition occurs.
Critical races

Figure 9.32

Two examples are shown for critical races. In critical race the final stable state is
different stable state depending upon the order in which the state variable changes.
Cycle

Figure 9.33

Races can be avoided by making proper binary assignment to state variables. The state
variables must be assigned binary numbers in such a way that only one state variable can change
at any one time when state transition occurs in flow table. Figure shows the cycles where only
one binary value changes at any one transition. But care must be taken so that a cycle must
terminate with stable state. In the last transition table, if the input changes from 0 to 1, then state
will go to 01→11→10→01→11. So the circuit goes to unstable state permanently.
9.7 Hazards
Unwanted switching appears at the output of a circuit due to different propagation delay
in different paths of the circuit is called as hazards. Hazards may cause the circuit to malfunction.
Because of hazards problem, the circuit may produce temporary false output values in
combinational circuits. In asynchronous sequential circuit, the hazards may cause to wrong
transition state. In synchronous sequential circuit, hazards make no effect in the output.
Types of Hazards
There are three types of hazards may occur in the combinational circuits and
asynchronous sequential circuit. They are (i) Static-1 hazard (ii) Static-0 hazard (iii) Dynamic
hazard.

Figure 9.34

Static-1 hazard
The output of the combinational or asynchronous sequential circuit momentarily goes to
0, and then come back to its normal state i.e. 1. This is called as static-1 hazard.
Static-0 hazard
The output of the combinational or asynchronous sequential circuit momentarily goes to
1, and then come back to its normal state i.e. 0. This is called as static-0 hazard.
Dynamic hazard
Dynamic hazard is the problem occurred in combinational or asynchronous sequential
circuit, where the output changes momentarily three or more times, while the output changes
from 0 to1 or 1 to 0.
Essential Hazard
Besides static and dynamic hazards, another type of hazard in asynchronous circuits is
called essential hazard. Essential hazard is caused by unequal delays along two or more paths
originated from same input. Static and dynamic hazard can be corrected by adding redundant
gates in the circuit, but whereas essential hazard cannot be corrected by adding redundant gates.
Essential hazard can be corrected by only adjusting the amount of delay in affected path.
Example: Circuits with hazards

Figure 9.35

The above circuit has hazards problem. We have three inputs x1 , x2 , x3 and one output Y
in this circuit. Initially assume the inputs x1 , x2 , x3 all are equal to 1. So what will be the output
from the circuit? The output Y will be 1. If the input x2 changes from 1→0, the output of NOT
gate will change from 0→1. But because of propagation delay of NOT gate, for some moment,
the output of both AND gates will be 0. So the output of the circuit Y will be 0 for a moment.
This output lasts for the period which is equal to the propagation delay of NOT gate. After that
the output comes back to 1. So this circuit has hazard problems.

Hazard free circuit

To eliminate the hazard problem in the above circuit, let us examine the map of the
circuit. The Boolean function of the circuit is
Y = x1 x2 +x2 ’x3

Figure 9.36

From the K-map, we can find that there is no link between two minterms. Because of that
only hazard problem exist in the circuit. So hazard problem will occur in the circuit while the
input changes from one group (minterm) to another group (minterm). For example the input x1 ,
x2 , x3 changes from 111 to 101.
To eliminate the hazard from the circuit, we have to enclose the two minterms by putting
an additional minterm.
 Figure 9.37

So the Boolean function of the hazard free circuit will be Y = x1 x2 +x2 ’x3 + x1 x3 .

Figure 9.38

9.8 ASM Chart

In many cases just drawing a state diagram includes certain assumptions that are not true
in general. An algorithmic state machine (ASM) diagram offers several advantages over state
diagrams:

For larger state diagrams, often are easier to interpret.

conditions for a proper state diagram are automatically satisfied
may be easily converted to other forms

A key point to remember about ASM charts is that given a state, they do not list all the
possible inputs and outputs.

The ASM Diagram Block

An ASM chart has an entry point and is constructed with blocks. A block is constructed
with the following type of symbols.
 Table 9.13

One state box. The state box has a name and lists outputs
that are asserted when the system is in that state. These
outputs are called synchronous or Moore type outputs.

Optional decision box. A decision box may be

conditioned on a signal or a test of some kind.

Optional conditional output box. Such an output box

indicates outputs that are conditionally asserted. These
outputs are called asynchronous or Mealy outputs.

There is no rule saying that outputs are exclusively inside an a conditional output box or
in a state box. An output written inside a state box is simply independent of the input, while in
that state.

The idea is that flow passes from ASM block to ASM block, the decisision boxes decide
the next state and conditional output. Consider the following example of an ASM diagram
block. When state S0 is entered, output Z5 is always asserted. Z1_n however is asserted only if
X2 is also high. Otherwise Z2 is asserted.

Figure 9.39

The drawing of ASM charts must follow certain necessary rules:

The entrance paths to an ASM block lead to only one state box
Of 'N' possible exit paths, for each possible valid input combination, only one exit path
can be followed, that is there is only one valid next state.
No feedback internal to a state box is allowed. The following diagram indicates valid and
invalid cases.
 Incorrect Correct

Parallel vs. Serial

We can bend the rules, several internal paths can be active, provided that they lead to a
single exit path. Regardless of parallel or serial form, all tests are performed
concurrently. Usually we have a preference for the serial form. The following two examples are
equivalent.

Parallel Form
Serial Form

Sequence Detector Example

The use of ASM charts is a trade-off. While the mechanics of ASM charts do reduce
clutter in significant designs, its better to use an ordinary state diagrams for simple state
machines. Here is an example Moore type state machine with input X and output Z. Once the
flag sequence is received, the output is asserted for one clock cycle.
 Figure 9.40

The corresponding ASM chart is to the right. Note that unlike the state diagram which
illustrates the output value for each arc, the ASM chart indicates when the output Z only when it
is asserted.

Figure 9.41

The following timing diagram illustrates the detection of the desired sequence. Here it is
assumed that the state is updated with a rising clock edge. The key concept to observe is that
regardless of the input, the output can only be asserted for one entire clock cycle.
 Figure 9.42

Timing diagram

Event Tables

Simply stated, timing diagrams are prone to a particular problem for the reader, in that
there can be too much to see. Timing diagrams clearly expresses time relationships and
delay. However, in synchonous sequential logic, all registers are updated at the rising edge of
the system clock. The clock period is just set to an arbitrarily value. Provided that the input
setup-and-hold requirements are satisfied, the details of the timing diagram are distracting.

The goal of an event table is that given a scenario, to neatly summarize the resultant
behavior of synchronous sequential logic. In writing an event table, capitol T refers to the
system clock period and nT means n times the system clock period. For asynchronous input
changes, the time is given, assuming that the system output reacts instantaneously. For
synchronous signals, the + symbol means a moment suitably after the given time, for the system
to become settled. The - symbol however, means a moment suitably before the given time,
satisfying the necessary setup time.

To reduce the clutter, be sure to fill in those signals that change state or are updated. The
following event table summarizes the behavior in the above timing diagram. An empty entry
will be interpreted to mean no-change to the corresponding signal during the corresponding
clock cycle.
 Table 9.14

Time Reset X State Z

0T 1 0 M0 0
0.4T 0
1T+ M1
1.3T 1
2T+ M2
2.6T 0
3T+ M3 1
3.6T 1
4T+ M2 0
4.4T 0

Asynchronous and Synchronous Output Example

The following is an example of an ASM chart with inputs X1 and X2, and outputs Z1 and
Z2. In state S0 the outputs are immediately dependent on the input. In state S1, output Z1 is
always asserted. In state S2, output Z1 is dependent on input X1 but Z2 is not asserted.

Figure 9.43

The following is the corresponding state diagram. The legend indicates how the input
and output are associated with each arc. The 'd' symbol, which refers here to the don't-care
condition helps to reduce the clutter. While the state diagram and ASM chart here are similar in
complexity, state diagrams quickly become messy.
 Figure 9.44

Clock Enable

Simply stated, a clock enable indicates when a state machine must pay attention to the
system clock. The figure below has a clock signal and a clock enable, note that this clock enable
is asserted for one clock period at a time. The clock enable concept is powerful as it allows a
device to effectively be clocked at a rate slower than the system clock, while remaining entirely
synchronous with the rest of the system. In this case the effective clock rate is one-third that of
the system clock.

Figure 9.45

Clock and enable

In the spirit of reducing clutter, a clock enable can be written next to a state box. When
not asserted, the device remains in its current state. The following figures are
equivalent. Further, it is assumed that devices controlled by such a state, as directly or indirectly
enabled by the clock enable as well.

Figure 9.46
9.9 Summary
In this chapter we have started our discussion with introducing the asynchronous
sequential circuit. In asynchronous sequential circuit there is no need to use of separate memory
elements. Instead the propagation delay can be utilized to design the asynchronous sequential
circuit.
Asynchronous sequential circuit can be operated in two modes namely funda mental mode
and pulse mode. Fundamental mode is the mode in which only one input must be changed at a
time also before changing the next input proper time should be given so that the circuit enters
into stable state.
We have defined the terms used in the asynchronous sequential circuits like secondary
variable (present state), excitation variable (next state), transition table, flow table, primitive flow
table. Primitive flow table is the flow table where exactly one stable state for each and every
row. We have analyzed the asynchronous sequential circuit and circuit with latches. Then we
have discussed the methods used for reduction of flow table. Reduction of flow table can be
achieved by using the implication table and compatible pairs. We have designed few
asynchronous sequential circuits for clarifying the design procedure of synchronous sequential
circuits.
We have learned what races are and how races can be avoided by using cycles. Races can
be divided into critical and non-critical races depending upon the final state the circuit reaches.
Then we have discussed the problems of hazards and hazard free circuits are designed. At last we
have defined the term ASM chart and its use in the design of logic circuits.

Review Questions
1. Explain the difference between asynchronous and synchronous sequential circuits.
2. Define fundamental mode operation of asynchronous sequential circuits.
3. Explain the difference between stable and unstable state.
4. What is the difference between internal state and total state?
5. An asynchronous sequential circuit is described by the following excitation and output
functions. Y = x1 x2 ’ + (x1 + x2 ’)y and output z = y. Draw the logic diagram of the circuit.
Derive transition table and output map.
6. An asynchronous sequential circuit is described by the following excitation and output
functions. Y1 = x1 x2 + x1 y2 ’ + x2 ’y1 , Y2 = x2 + x1 y1 ’y2 + x1 ’y1 and output z = x2 + y. Draw
the logic diagram of the circuit. Derive transition table and output map.
7. It is necessary to design an asynchronous sequential circuit with two inputs, xl andx2 , and
one output, z. Initially, both inputs and output are equal to 0. When xl or x2 becomes 1, Z
 becomes 1. When the second input also becomes 1, the output changes to 0. The output
stays at 0 until the circuit goes back to the initial state.

(a) Obtain a primitive flow table for the circuit and show that it can be reduced to the
flow table shown in figure.
(b) Complete the design of the circuit.
8. Draw the logic diagram of the product of sums expression: Y = (x1 + x2 ’) (x2 + x3 ). Show
that there is a static O-hazard when Xl and X3 are equal to 0 and X2 goes from 0 to 1.
Find a way to remove the hazard by adding one more OR gate.