Академический Документы
Профессиональный Документы
Культура Документы
Sensor actuators,
Input Processing Output
signals,
control
ADC Testing
Part 7 in a series of tutorials in
instrumentation and measurement
nalog-to-digital converters (ADCs) are test- The following sections address general test setups,
Notes:
COMINT: communications intelligence SIGINT = signal intelligence
DNL: differential nonlinearity SINAD: signal-to-noise and distortion ratio
ENOB: effective number of bits THD: total harmonic distortion
ELINT: electronic intelligence IMD: intermodulation distortion
NPR: noise power ratio SFDR: spurious free dynamic range
INL: integral nonlinearity DP: differential phase error
DG: differential gain error
In this setup, the test signal is generated digitally then Common Static Test Methods
converted to analog. You must quantify the performance Static parameters describe the ADCs fundamental perfor-
of the digital-to-analog converter (DAC) and filter to mance with essentially nonvarying or slowly varying input
assess (or remove) its impact on the measured perfor- signals. The ADC’s static performance is often regarded as a
mance of the ADC under test. baseline since the ADC’s performance tends to degrade as
the input signal’s frequency increases.
Step Waveform Test Setup
You can use the step waveform test setup, shown in
Figure 3, for testing with precision step signals that are
not digitally generated. Precision pulses and step signals
ADC Versus Waveform Recorder—
can be used to measure both time domain parameters
What’s the Difference?
here are two IEEE standards, IEEE Standard for
(such as impulse response, transition duration, over-
shoot, and settling time) and frequency domain parame-
T Terminology and Test Methods for Analog-to-
Digital Converters (IEEE Std 1241-2000) and IEEE
ters (such as frequency response amplitude and phase,
Standard for Digitizing Waveform Recorders (IEEE
bandwidth, and gain flatness). If the optional pulse repe-
Std 1057-1994), that cover very similar material. In
tition generator is phase locked to the sampling clock,
fact, all of the figures of merit introduced in the
then you can use equivalent time sampling and simplify
previous article (i.e., Part 6 in this series of tutorials
certain data analysis tasks. You must pay careful atten-
[3]) are essentially identical in the two standards,
tion to the phase linearity of any filters placed in the
and the test methods are the same at the highest
pulse or step signal path.
level. So why are there two standards? A digital
waveform recorder is a complete instrument, such
Feedback Loop Test Setup (Servo Test)
as a digital oscilloscope, that uses one or more
A widely used test method for determining transition lev-
ADCs as an important element, whereas an ADC is
els is based on a feedback loop. In this method, you apply
a single component. Most of the tests in this article
an input to the ADC, trigger the converter, and compare
are easier to perform on a waveform recorder than
the results of the conversion to a desired value. If the
on an ADC, because much of the test setup (e.g.,
ADC output is below the desired value, the input is raised
power supplies, buffer amplifiers, clocks, and
by a fixed amount. If the ADC output is equal to or above
memory) is built into the waveform recorder but
the desired value, the input is lowered by a fixed amount.
has to be supplied by the tester when testing an
You repeat this process until the ADC input has settled to
ADC. So the test setups in the waveform recorder
a stable average value that can be measured by the volt-
standard are generally less complex than those in
meter. After the loop has settled, the input value can
this article and in the ADC standard.
either be measured or, if the input source is well calibrat-
Information about both of these standards
ed, computed from its transfer function. Figure 4 illus-
and other activities of the IEEE Instrumentation
trates a block diagram for the Servo Test. In this diagram,
and Measurement Society’s TC-10 can be found
a DAC generates the feedback signal, but other implemen-
at http://grouper.ieee.org/groups/1057/.
tations are possible, including the classic analog one,
which is shown in Figure 5.
Clock Generator
(Frequency Filter Required
Generator) Optional
Sine Wave
ADC
Generator Latch/ Buffer
∑ Filter Under Computer
(Frequency Demux Memory
Test
Synthesizer)
Programable
Delay
Signal
Generator
(Frequency
Synthesizer)
ADC
Control and Latch/ Buffer
DAC Filter Under Computer
Local Memory Demux Memory
Test
Clock Generator
Filter
(Frequency Generator)
ADC
Latch/ Buffer
Pulse Generator Filter Under Computer
Demux Memory
Test
The offset V OS can be computed from The values of the two end-point transitions can be com-
puted from the following expressions:
V OS = T1 − G · T[1]. (3)
N VP −VM
The values of G and V os , which cause 2k=1−1 ε[k]2 to be a T[1] = VM + Hc [0] (7)
S
minimum, are the independently based gain and offset. VP −VM
T[2N − 1] = VM + Hc [2N − 2]. (8)
The INL can be determined after the gain and offset have S
been determined by
The parameters A and C can then be computed from the end
ε[k]
INL[k] = . (4) point values with the following expressions:
FSR
T[k + 1] − T[k] The gain and the offset of the ADC under test based on the end-
DNL[k] = −1 . (5)
Q points can be computed once the values of T[k] are known.
The independently based gain and offsets are computed
Determining Transition Levels T[k]— with a least mean squares algorithm, which is described in
Ramp-Based Method IEEE Std 1241-2000.
Apply a ramp to the ADC under
test. The ramp should start at a
known voltage VM, which is Clock
less than V min . The ramp should k
Word
terminate at a voltage VP, which ADC
Reference
Comparator Code
is greater than V max . An example Under A B
kin
of such an input is shown in Test
A<B
Figure 7. Voltmeter
Triggers are applied to the
ADC while the slow ramp is mov- Trig 1
N1 N2
ing from its initial position to its
final position. The total number of
triggers needed should be enough
to trigger the ADC many times at SUB N1 ADD N2
DAC
each step. A count is kept of the
Adder
number of times each code of the
NDAC
ADC is observed. The resultant
histogram of the code hits is
Fig. 4. Feedback loop test setup.
stored in the array H[k], where
0 ≤ k ≤ 2N − 1. The array of the
threshold values can be computed from the histogram with Potential Problems—Ramp-Based Method
There are several concerns that may arise when the ramp-
T[k] = C + A · Hc [k − 1] for k = 1, 2, . . . , (2N − 1), (6) based method is used.
◗ The linearity of the applied ramp directly affects the
where A is a gain factor and C is an offset factor; accuracy of the INL data.
j ◗ The precision of the starting level and the stopping level
Hc [ j] = H[i] , of the ramp (VM and VP) will directly influence the
i=0 gain and offset calculations.
where H[i], is the number of histogram samples received in ◗ The presence of ADC input noise will affect the accura-
code bin i; and cy of the measurement. Generally, the uncertainty of the
2
N
−1 evaluation of the code transition levels will vary as the
S= H[i] = Hc [2N − 1], square root of the number of conversions that occur at
i=0 each code. This topic is discussed in greater detail in
where S is the total number of samples taken. IEEE Std 1241-2000.
each record of sine wave data, compute the DFT. You use
|Xavm ( fi)|
the K sets of data to compute an averaged magnitude spec- SFDR = 20 log10 . (13)
max fsp , fh |Xavm ( fsp )|, |Xavm ( fh )|
trum of the DFT bins at each basis frequency fm.
At this point, identify the set of frequencies fh that cor-
respond to the chosen set of harmonics of the input test You must specify the amplitude and frequency of the input
frequency. For a test tone at frequency fi, the harmonics and the sample frequency for which SFDR measurement(s)
are aliased so that fh lies between zero and the sampling are made.
frequency fs. The input frequency and each harmonic map
into two different frequencies in the DFT, one correspond- Signal-to-Noise-and-
ing to positive frequencies and one to negative frequen- Distortion Ratio Estimation
cies. The choice of harmonic components included in the You again use the sine wave test setup to estimate the signal-
set should be done including the harmonics with a signifi- to-noise-and-distortion ratio (SINAD) of an ADC. Therefore,
cant portion of the distortion energy and excluding DFT apply a sine wave of specified frequency and amplitude to
bins whose energy content is dominated by random noise. the ADC input. A large signal (approaching full scale) is pre-
The tradeoff suggested in IEEE Std 1241-2000 to estimate ferred. Almost any error source in the sine wave input, other
THD includes in the set the lowest nine harmonics, second than gain accuracy and dc offset, can affect the test result. So,
through tenth, inclusive, of the input sine wave. Finally, we recommend that you use a sine wave source with good
compute the THD: short-term stability and that the sine wave input be highly
1
(Xavm ( fh ))2
M h
THD = , (11) Vmax
VP
Arms
1 2 2
Arms = Xavm ( fi) + Xavm ( fs − fi) (12)
M
Vmin
VM
is the rms of the output fundamental component at the
signal test frequency, fi = Jfs/M. Triggers
Spurious-Free-Dynamic-Range Estimation
To estimate the spurious free dynamic range (SFDR) of an Fig. 7. Ramp waveform applied to ADC for evaluating transition levels.
ADC, the procedure for THD is
used, considering also a set of
spurious frequencies fsp. A spuri-
ous frequency is the frequency of Plot of INL of 9-bit ADC
0.8
a persistent spectral output com-
ponent that is neither the funda- 0.6
mental nor a harmonic distortion
component. You determine the set 0.4
by inspection of the ADC output
Error(LSB)
Bandwidth Estimation
M−1
1
rms noise = Eavm ( fm )2, (15) To estimate the bandwidth of an ADC, use the sine wave test
M m=0 setup and add an ac voltmeter. Use a large signal sine wave
(the signal must span at least 90% of the full-scale range of
where Eavm is the residual spectrum of Xavm . the ADC under test), unless the small-signal bandwidth is to
be determined. When small-signal bandwidth is to be deter- high enough to make aliasing errors negligible. The fref is
mined, the peak-to-peak input amplitude used is less than chosen from the DFT bins. It must be one within the pass
one-tenth of full scale. band such that the dynamic gain is at or near the peak gain
The input sine wave source should produce sinusoids of of the pass band.
high spectral purity (i.e., harmonic distortion lower than You analyze the DFT bins to find the upper and, if appli-
that of the ADC under test) and should have stable output cable, the lower frequency samples closest to the reference
during the measurement time. The tested input frequencies frequency at which the gain is 3 dB below the reference gain.
should not be subharmonics of the ADC sampling rate The bandwidth is the difference between these upper and
since such frequencies can produce incorrect results in this lower −3 dB sample frequencies (or, if a lower −3-dB fre-
test. An input frequency at which the ADC’s dynamic gain quency does not exist, the bandwidth is simply the upper
is equal to or near its peak value in the pass band is select- −3-dB frequency value). To improve the bandwidth esti-
ed as a reference frequency. After connecting the sine gen- mate, interpolate between the frequency samples above and
erator to the ADC input, you set its frequency to the below −3 dB in amplitude to better estimate the actual −3-
reference frequency fref and acquire a sufficient number of dB frequency.
data records from the ADC output to determine the maxi- The disadvantages of this test are high noise at higher
mum peak-to-peak range of the signal using a three- frequencies and aliasing and first-differencing errors result-
parameter or four-parameter sine fit. The input amplitude ing from the frequency response estimation. The results of
measurement must be done with care if high accuracy is using the step response method are invalid in the presence
required. If the measured input amplitude parameter is the of slew rate induced errors.
rms amplitude, Arms , you must convert it to peak-to-peak
√
amplitude by multiplying it by 2 2. Divide the peak-to- Gain Error Estimation
peak ADC output amplitude by the measured peak-to- To estimate the gain error of an ADC, the sine wave based
peak input amplitude to determine the reference gain. If methods or the differentiated step response method can be
the chosen fref is zero, the reference gain is the static gain. used. Gain error, also known as gain flatness, is the differ-
Alternatively, to determine the static gain, you can use a ence between the dynamic gain, G(f), of the ADC at a
precision dc signal source to provide a constant input sig- given frequency and its gain at a specified reference fre-
nal. The dc gain is approximated by the constant output quency, divided by its gain at the reference frequency. The
signal level minus the measured static dc offset divided by dynamic gain of the ADC under test at a frequency f is the
the input dc level. magnitude of the frequency response at that frequency.
Once the reference gain is determined, you change the The reference frequency is chosen to be a frequency whose
input frequency to another value that is not a sampling-rate gain is at or near the peak gain of the ADC pass band; typ-
subharmonic. You then measure the maximum peak-to-peak ically, it is the same frequency as the one used in the band-
range of the recorded data and divide it by the input ampli- width test. For dc-coupled ADCs, the reference frequency
tude measured by the ac voltmeter to find the gain at this is typically dc ( f = 0).
frequency. You repeat as necessary to find the upper (and, if
it exists, lower) frequency, closest to the reference frequency, Aperture Delay Estimation
at which the gain is 3 dB below the reference gain. If no To estimate the aperture delay of an ADC, apply a ramp to
lower −3 dB frequency exists, the upper −3 dB frequency is the analog input and apply a clock signal to the clock
the bandwidth. If a lower −3 dB frequency exists, the differ- input of the ADC adapting the arbitrary signal test setup.
ence between the upper and lower −3 dB frequencies is the Instead of a ramp signal at the analog input, you can use a
bandwidth of the ADC. portion of another waveform (e.g., a sine wave) provided
This test uses sine wave inputs and can be done very that the slew rate of the waveform does not vary substan-
quickly if the reference frequency and the approximate tially over the aperture width of the ADC (e.g., a sine
limit frequencies are known. The disadvantage is the typ- wave of frequency less than half the analog bandwidth of
ically low accuracy of estimates of the analog input the ADC). The ramp signal slew rate should be as high as
amplitudes, which reduces the accuracy of the band- possible without exceeding the slew rate limit of the ADC
width result as well. or causing excessive dynamic errors. The ramp and the
IEEE Std 1241-2000 proposes an alternative bandwidth clock must be synchronized such that the ADC samples
test method, which is generally more useful for ADCs that the ramp at the center of the ADC full-scale range. Using a
contain analog bandwidth limiting circuitry before the time-interval meter or oscilloscope with sufficient resolu-
quantizer(s). You use the step signal test setup to deter- tion and accuracy, the time delay is measured from the
mine the ADC frequency response. It is desirable to have time instant the clock input crosses its threshold to the
as many samples in the record as possible, to increase the instant the analog input crosses the dc value correspond-
resolution with which the bandwidth can be resolved from ing to the center of the ADC full-scale range. For ADCs
the DFT of the derivative of the step response. The sam- with very high sample rate, where the aperture delay may
pling rate, or equivalent-time sampling rate, should be be similar in magnitude to the clock period, extra care
Eulalia Balestrieri achieved the master’s degree in 2003 in 1961, respectively. He has two patents involving mixed-sig-
software engineering from the University of Sannio. She nal technology. He is currently a staff scientist and LTX
joined the research activities carried out at the Laboratory of Fellow at LTX corporation where he was one of the founders
Signal Processing and Measurement Information of the of the company in 1976. At LTX, he developed many of the
University of Sannio, Benevento. In 2004, she began a Ph.D. test instruments used in ATE systems. He is a Senior
course in information technology. She is a member of the Member of the IEEE and a member of Eta Kappa Nu, Tau
IEEE I&M TC-10. Beta Pi, and Sigma Xi.
Luca De Vito achieved the master’s degree cum laude in Steven J. Tilden has more than 33 years electronics experi-
2001 in software engineering from the University of Sannio. ence, six in the U.S. Air Force and the last 27 in Tucson,
Then, he joined the research activities carried out at the Arizona, at Burr-Brown, which became Texas Instruments in
Laboratory of Signal Processing and Measurement 2000. He has worked in nearly every area from wafer fabrica-
Information of the University of Sannio, Benevento. He tion through final test in several engineering disciplines. He
achieved the Ph.D. in information engineering in 2005 from a Senior Member of the IEEE and a senior member technical
the University of Sannio. Currently, he is a software design- staff at Texas Instruments. He is chair of the IEEE TC-10
er at Telsey telecommunications. He is a member of the IEEE subcommittee that published ADC test methods and termi-
I&M TC-10. nology standard 1241, is chair of the IEEE TC-10 subcommit-
tee on digital-to-analog converters, and is a U.S. national
Solomon Max has worked in the mixed-signal field for delegate to the International Electrotechnical Commission
almost 50 years. He received his B.E.E. degree from City for semiconductor, integrated circuits, which are publishing
College of New York in 1957, and S.M. and E.E. degrees IEC-level ADC and DAC test and terminology standards
from the Massachusetts Institute of Technology in 1959 and through TC47/SC47A/WG4.
The 2007 IEEE Sensors Applications Symposium (SAS-2007) provides a unique forum for sensor users and developers to meet
and exchange information about novel and emergent applications in smart sensors, biology, homeland security, system health
management, and related areas. Collaborate and network with scientists, engineers, developers and customers, in a balance of
formal technical presentations, workshops, and informal interface meetings—a unique feature of this conference.
Important Dates—Abstract submission deadline: 01 October 2006, Notification of acceptance: 01 December 2006, Final
manuscript submission deadline: 01 January 2007