Kayhan DURSUN

Mantıksal Devre Tasarımı Dersi

6.Bölüm Cevapları
 Include a two input NAND gate with the register of Fig. 6-1 and connect the gate output to the C inputs of all flip-
1 flops.One input of the NAND gate receives the clock pulses from the clock generator,and the other input of the
NAND gate provides paralel load control.Explain the operation of the modified register.

I0 D A0

I1 D A1
Clock Load Operation

C X 0 No change
Load 0 1 No change
I2 D A2 1 1 Load
CLK

I3 D A3

C
 Include a synchronous clear input to the register of Fig 6.2.The modified register will have a parallel load capability and a
2 synchronous clear capability.The register is cleared synchronously when the clock goes through a positive transition and the
clear input is equal to 1.

Load

Clear D A0
I0
C

D A1
I1 C

D A2
I2 Clear Load Operation
C 0 0 No change
1 0 0
X 1 Load inputs
A3
D
I3
C

CLK
3 What is the difference between serial and parallel transfer?Explain how to convert serial data to parallel and parallel
data to serial.

• Seri transferde bir saat vuruşunda yalnızca bir bit iletilirken,paralel

transferde bir saat vuruşu ile tüm bitler iletirlir.Bu nedenle seri
transfer daha yavaştır ancak maliyeti de daha azdır.

• Seri transferi paralel transfere çevirmek için,ilk başta bütün bitler

shift register ile tek tek aktarılıp çıkışlar paralel olarak bağlanır.

• Paralel transferi seri transfere çevirmek için ise ilk başta veri paralel
yüklenip çıkışta bitler teker teker iletilir.
4
The content of a 4-Bit register is initially 1101.The register is shifted six times to the right with the serial input being
101101.What is the content of the register after each shift?

S.I=101101
Initial 1.Shift 2.Shift 3.Shift 4.Shift 5.Shift 6.Shift
1101 1110 0111 1011 1101 0110 1011
5 The 4-Bit universal shift register shown in Fig. 6-7 is enclosed within one IC package.

a Draw a block diagram of the IC showing all inputs and outputs.Include two pins for the power supply.

A4 A3 A2 A1 Vcc GND

Sağa Sola
Kaydırıcı Kaydırıcı

S0
CLR
S1
I0 I1 I2 I3 CLK
5 b Draw a block diagram using two ICs to produce an 8-Bit universal shift register.

A0 A1 A2 A3 Vcc GND A0 A1 A2 A3 Vcc GND

Sola Sola
Sağa kaydırıcı Sağa kaydırıcı
kaydırıcı kaydırıcı

S0 S0

CLR CLR
S1 S1
I0 I1 I3 I4 CLK I0 I1 I3 I4 CLK
6

Design a 4 bit shift register with parallel load using D flip-flops.There are two
control inputs:shift and load.When shift=1,the content of the register is shift by
one position.New data is transfered into the register when load =1 and
shift=0.If both control inputs are equal to 0,the content of the register does not
change.
6 Load
Shift
S.I. D
I0
C

D
I1
C

D
I2
C

D
I3
C
7

Draw the logic diagram of a 4-bit register with four D flip-flops and four 4x1
multiplexers with mode selection inputs s1 and s0.The register operates
according to the following function table.
s1 s0 Register Operation
0 0 No change
0 1 Complement the four outputs
1 0 Clear register to 0(synchronous with the clock)
1 1 Load parallel data
7S 1
S0
4x1 D Q0

0 C Q 0’
I0

D Q1
4x1
C Q1’
I1

4x1 D Q2
C Q 2’
I2

4x1 D Q3
C Q 3’
I3
8 The serial adder of Fig. 6-6 uses two 4-Bit registers.Register A holds the binary number 0101 and regiser B holds 0111.The
carry flip-flop is initially reset to 0.List the binary values in register A and the carry flip-flop after each shift.

Initial 1.Shift 2.Shift 3.Shift 4.Shift

A 0101 0010 0001 1000 1100
Carry 0 1 1 1 0
9 Two ways for implementing a serial adder (A+B) ,is shown in section 6-2.It is necessary to modify
the circuits to modify them to serial subtractors (A-B)

a Using the circuit of Fig. 6-5,show the changes needed to perform A+2’s complement of B.

Figure 6-5‘te B registerinin çıkışına inverter

koyup carry’i de ilk olarak 1’e eşitlersek
A+(B’nin 2’ye göre tersi) işlemi yapılır.
9 b Using the circuit of Fig.6-6,show the changes needed by modifying Table 6-2 from an adder to a subtractor circuit.
Present Inputs
State
Q x
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Next Output FlipFlop
State Inputs
y Q W JQ KQ
0 0 0 0 X
1 1 1 1 X
0 0 1 0 X
1 0 0 0 X
0 1 1 X 0
1 1 0 X 0
0 0 0 X 1
1 1 1 X 0
 xy xy xy
00 01 11 10 Q 00 01 11 10 Q 00 01 11 10
Q
0 1 1 0 1 0 X X X X
0 1 1 0 X X X X 0 1
W=Q + x + y JQ = x’y KQ = xy’
 Design a serial 2’s complementer with a shift register and a flip-flop.The binary number is shifted out from one side
10 and it’s 2’s complement shifted into the other side of the shift register.

x
Shift Register

Q
D

C
CLK
 A binary ripple counter uses flip-flops that trigger on the positive edge of the clock.What will be the count if; a)the
11 normal outputs of the flip-flops are connected to the clock and b)the complement outputs of the flip-flops are
connected to the clock?

a)Geriye doğru sayan sayıcı olur.

b)İleriye doğru sayan sayıcı olur.

 Draw the logic diagram of a 4-bit binary ripple down counter using a)flip-flops that trigger on the positive-edge of the
12 clock and b) flip-flops that trigger on the negative-edge of the clock.

a T A0

C
Count
T A1

T A2

A3
T

Lojik 1 Reset
12
b T A0

C A0’
Count
T A1

C A1’

T A2

C A2’

A3
T

C A3’

Lojik 1 Reset
13 Show that a BCD ripple counter can be constructed using a 4-bit binary ripple counter with
asynchronous clear and a NAND gate that detects the occurence of count 1010.

Q0 0
BCD
Q1 1
Ripple Counter Q2 0
Clear Q4 1
14 How many flip-flop will be complemented in a 10-bit binary ripple counter to reach the next count after the
following count:

a) 100110 0111
4
100110 1000

b) 0 011111111
9
1 000000000

c) 1111111111
10
0000000000
15 A flip-flops has a 5 ns delay from the time the clock edge occurs to the time the output is complemented.What
is the maximum delay in a 10-bit binary ripple counter that uses these flip-flops?What is the maximum
frequency the counter can operate reliably?

Bütün flip-flop’ların complement olacağı düşünürlürse;

10 x 5 = 50 ns maksimum gecikme olacaktır.

Maksimum frequency ise

109/50 = 20 Mhz olur.
 The BCD ripple counter shown in Fig. 6-10 has four flip-flops and 16 states ,of which only 10 are used.Analyze
16 the circuit and determine the next state for each of the other unused states.What will happen if a noise signal
sends the circuit to one of the unused states?

1010 1011 0100

1011 0100
1100 1101 0100
1101 0100
1110 1111 0000
1111 0000
17 Design a 4-bit binary synchronous counter with D flip-flops.

Figure 6-12’deki çıkışları T flip-flop için yazıp count enable’a

I dersek:
TA0 = I , TA1 = IA0 , TA2 = IA0A1 , TA3 = IA0A1A2 olur

T flip-flop’tan D flip-flop
şekildeki gibi elde edildiği
D
için; D flip-flop’la
TAi yapılacak senkron sayıcının
C girişleri aşağıdaki gibi olur:

DA0 = I+A0 , DA1 = A1+(IA0) , DA2 =A1+IA0A1 ,

DA3 =A3+IA0A1A2 olur
 What operation is performed in the up-down counter of Fig. 6-13 when both the up and down inputs are
18 enabled?Modify the circuit so that when both inputs are equal to 1,the counter does not change state,but remains in the
same count.

*Up ve down girişlerinin ikisi birden 1 olursa ,devre yukarı doğru

sayma yapar.
*Eğer bu iki input 1 iken devrenin bir önceki durumda kalmasını
istiyorsak T flip-flop’unun girişinin 0 olması gerekir ki outputta
değişiklik olmasın.Bunun için devrede aşağıdaki değişikliği
yapmalıyız:
Up

T A0

Down C

Görüldüğü gibi inputlar 1 iken AND kapıları daima 0 çıktısı verip T flip-flop’unun durumunun
değişmemesini sağlar
19 The flip-flop input equations for a BCD counter using T flip-flops are given in section 6-4.Obtain the input equations
for a BCD counter that uses;

a J-K flip-flops

Present State Next State Flip-flop inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 JQ8 KQ8 JQ4 KQ4 JQ2 KQ2 JQ1 KQ1
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 0 X 0 1 X
1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1
 Q2Q1 Q2Q1
Q 8Q 4 00 01 11 10 Q8Q4 00 01 11 10
00 1 X X 00 1
01 1 X X 01 X X X X
JQ2 = Q8’Q1 JQ4 = Q1Q2
11 X X X X 11 X X X X
10 X X 10 X X
QQ QQ
Q8Q4 2 1 Q8Q4 2 1
00 01 11 10 00 01 11 10
00 X X X X 00
01 1 01 1
KQ4 = Q1Q2 JQ8 = Q1Q2 Q4
11 X X X X 11 X X X X
10 X X X X 10 X X X X
Ayrıca ; JQ1 = 1 KQ1 = 1 KQ2 = Q1 KQ8 = Q1 olduğu tablodan doğrudan görülür.
Present State Next State 19 b D flip-flops
Q2Q1
Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Q8Q4 00 01 11 10
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0 00 1 1
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0 01 1 1
0 1 0 0 0 1 0 1 DQ2=Q2Q1’+Q8’Q2’Q1
0 1 0 1 0 1 1 0 11 X X X X
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0 10 X X
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
Q 2Q 1 Q2Q1
Q8Q4 00 01 11 10 Q8Q4 00 01 11 10
00 1 00

01 1 1 1 01 1
DQ8=Q8Q1’+Q4Q2Q1
11 X X X X 11 X X X X
10 X X 10 1 X X
DQ4=Q4Q1’+Q4Q2’+ Q4’Q2 Q1
20 Enclose the binary counter with paraller load of Fig. 6-14 in a block diagram showing all inputs and outputs.

a) Show the connections of four such blocks to produce a 16-bit counter with parallel load.

A3 A2 A1 A0

Load Carry
Count 16 bitlik sayıcı oluşturmak için her bir
CLK devrenin carry çıkışını bir sonrakinin
Clear Count girişine bağlamalıyız.Bu işlem
için bu devreden 4 tane gereklidir.

I3 I2 I1 I0

b) Construct a binary counter that counts from 0 to 64.

CLK CLK
Load
4-Bit counter CLR Carry 4-Bit counter CLR
Carry Load
Count Count

0 0
21 The counter of Fig. 6-14 has two control inputs Load(L) and Count(C) and a data input ,(Ii).

a) Derive the flip-flop input equations for J and K of the first stage in terms of L,C,and I.

JA0 = CL’ + I0L

KA0 = LI0’ + L’C

b) The logic diagram of the first stage of an equivalent integrated circuit is shown in Fig. P6-21.Verift that this
circuit is equivalent to the one in a.

J = [L(LI’)][L + C] = (L’ + LI)(L + C)=L’C + LI

K = (LI’)(L + C) = (L’ + I’)(L + C) = L’C + LI’

22 Using the circuit of Fig. 6-14, design a mod-12 counter:

A3 A2 A1 A0

1011(11) olduktan sonraki

Clear clock darbesi ile inputlar
CLK sayaca yüklenir ve sayaç
Load Count sıfırlanır.

Using an AND gate and the load input

A3 A2 A1 A0

Load 1100(12) olduğu anda

sayaç sıfırlanır.
CLK
Count
Clear
Using an NAND gate and the asynchronous clear
input
23 Design a timing circuit that provides an output signal that stays on for exactly eight clock cycles.A start signal
sends the output to the 1 state,and after eight clock cycles the signal returns to the 0 state.

Count
3-bit
T İlk başta 1’e
sayıcı
eşit.

Sayaç 111 sayınca flip-flop 0 çıkarır ve count’a 0 girişi

giderek saymayı durdurur.
 24 Design a counter with T flip-flops that goes through the following binary repeated sequence: 0,1,3,7,6,4.Show that when binary
states 010 and 101 are considered as don’t care conditions,the counter may operate properly.Find a correct way to design.

Present State Next State Flip-flop inputs

A B C A B C TA TB TC
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 0 X X X X X X
0 1 1 1 1 1 1 0 0
1 0 0 0 0 0 1 0 0
1 0 1 X X X X X X
1 1 0 1 0 0 0 1 0
1 1 1 1 1 0 0 0 1
BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10

0 1 X 0 1 X 0 1 X
0 1 X 0 1 X 0 X 1
TA =A + B TB = B + C TC = A + C
Devrenin kullanılmayan bir duruma girdiğinde çıkıp çıkmadığını kontrol etmek
gerekirse;
010 101 010 olduğu ve devrenin kendini düzeltmediği görülür.Bunun
için;

BC
A 00 01 11 10

0 1 X
Şeklinde sadeleştirirsek bu durumda devre
0 X 1 kendini düzeltir.
101 010 100
 It is necessary to generate six repeated timing signals T0 through T5 similar to the ones shown in Fig. 6-17(c).Design
25 the timing circuit using:
a)Flip-flops only b)A counter and a decoder.

T0 T1 T2 T3 T4 T5
Sağa kaydır

0 T0
b 1 T1
2 T2
3-Bit Counter 3 X 8 Counter
4 T3
5 T4
6 T5
26 A digital system has a clock generator that produces pulses at a frequency of 80 Mhz.Design a circuit that
provides a clock with a cycle time of 50 ns.

(1000 x 10-9) / 50 = 20Mhz olur.

Bu durumda 80 ‘i 4’te birine indirmek için bir 2-bit sayıcı kullanmamız

gerekir.
 27 Present State Next State Flip-flop inputs
A B C A B C JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
Design a counter with 0 0 1 0 1 0 0 X 1 X X 1
the following repeated
binary
sequence:0,1,3,4,5,6.
0 1 0 0 1 1 0 X X 0 1 X
Use JK flip-flops.
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 X X X X X X X X X
BC BC BC
A 00 01 11 10 A 00 01 11 10 00 01 11 10
A
0 1 0 X X 1 0 1 X X 1
0 X X X X 0 X X X 1 0 1 X X
JA = BC KA = B KB = A + C JB = C JC = A’ + B’ KC = 1
 28 Present State Next State BC
A 00 01 11 10
A B C A B C
0 X 1
0 0 0 0 0 1 DA = A+B
0 0 1 0 1 0 0 1 X X
Design a
counter with the
0 1 0 1 0 0
following
BC
0 1 1 X X X A 00 01 11 10
repeated binary
sequence:0,1,2
,4,6.Use D flip- 1 0 0 1 1 0 0 1 X
flops. DB = AB’+C
1 0 1 X X X
0 1 X X
1 1 0 0 0 0
1 1 1 X X X
BC
A 00 01 11 10

011 110 101 110 111 010 0 1 X

DC = A’B’C’
Görüldüğü üzere devre beklenmeyen 0 X X
duruma girdiği zaman kendini düzeltir
29 List the 8 unused states in the switch-tail ring counter of Fİg. 6-18 (a). Determine the next state for each of these states and show that, if the counter
finds itself in an invalid state,it does not return to a valid state.Modify the circuit as recomended in the text and show that the counter produces the
same sequence of states and that circuit reaches a valid state from any of the unused states.

Present State Next State

A B C D A B C D
0 0 1 0 1 0 0 1
0 1 0 0 1 0 1 0 Görüldüğü gibi devre kullanılmayan bir duruma girdiği
0 1 0 1 0 0 1 0 zaman kendini kurtaramıyor.Belirtilen şekilde C flip-
0 1 1 0 1 0 1 1 flop’unun girişine Dc = (A + C)B değişikliği yapılınca
1 0 0 1 0 1 0 0 devre kullanılmayan bir duruma girince kendini
1 0 1 0 1 1 0 1 kurtaracaktır.
0 1 1 0 0 1 1 1
1 0 1 1 0 1 0 1
1 1 0 1 0 1 0 1

A B C E
D D D D
E’
C C C C

0010 1001 0100 1000

1010 1101 0110 1011 0101 0000
CLK
30
A B C D E
D D D D D
E’
C C C C C

A B C D E Outputs
0 0 0 0 0 A’E’
1 0 0 0 0 A B’ Görüldüğü gibi 5 flip-flop’tan 10
1 1 0 0 0 B C’ farklı durum oluştu.

1 1 1 0 0 C D’
Show that a Johnson counter with n flip-flops produces a sequence of 2n
1 1 1 1 0 D E’ states.List the 10 states produced with five flip-flops and the Boolean
terms of each of the 10 AND gate outputs.

1 1 1 1 1 AE
0 1 1 1 1 A’B
0 0 1 1 1 B’C
0 0 0 1 1 C’D
0 0 0 0 1 D’E