Baker Clamp application for PNP Transistor

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I have an issue related to Baker Clamp application for PNP Transistor. I know how to implement the Baker Clamp for NPN Transistor. However
I do not know how to do it for PNP. So could anyone can suggest me a schematic?

Secondly, can the Baker Clamp reduce the turn-off time of PNP transistor?

Thank you very much in advance.

bjt pnp switching-losses

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edited Feb 26 at 16:38

SamGibson
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asked Feb 26 at 16:34

Mert Karadeniz
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 to convert NPN to PNP just reverse everything. (all voltages, all diodes etc) – Jasen Feb 26 at 18:42

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How about this one?

simulate this circuit – Schematic created using CircuitLab

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answered Feb 26 at 16:55

G36
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Standard 2 diode version of a Baker Clamped NPN transistor on the left.

Switch all the arrows round, and viola, the PNP version on the right.

Omit D1/D3 and replace D2/D4 by shottky or germanium for the one transistor version. This is the normal way the technique is used today.

Add another diode anti-parallel to D1/D3 for the 3 diode version. This is faster than the two diode version, as the extra diode provides a path for
base charge to be abstracted by the driving circuit.
simulate this circuit – Schematic created using CircuitLab

The clamp will speed up switch off of a PNP, as it prevents collector saturation and so excess charge storage.

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answered Feb 26 at 16:53

Neil_UK
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The Baker clamp uses carefully selected Schottky to raise Vce >Vce(sat) and Silicon diodes to raise Vce(max) and to lower BC pF somewhat
like a Schottky Transistor used in 74Sxx and 74LSxx but at the expense of Pd drop like a Darlington. This raises the VI product while also
raising the transition frequency.

Most recent IC to use this I know is here. http://home.mira.net/~gnb/audio/lme49810.html

It is important to realize when rCE drops to conduct more current, the equivalent Collector capacitance Cce and storage charge increases which
is an RC=T (approx. limitation) . The same is true in cascading power FETs with T=RonCoss and RgCiss so there becomes an optimal critical
ratio of Ron/Rg for fastest yet efficient speeds . In slow SMPS it is common to see Ron/Rg be 1000:1 where in fastest high power FET designs
this sometimes reduces to 10:1 in Ron Input driver/Output driver ratios.

This is also apparently true in optimized Baker designs where the Ic/Id has been suggested around 4:1 which to me implies a component power
ratio of each.

Perhaps as well just as ESR*Pd(max) =1 is somewhat a design constant in all diodes with some reduction from 1 to 1/2 due to improved SMT
thermal design and some rising to 1.5 due to poor bulk resistance which accounts for all the tolerance spreading of Vf/If at rated current
tolerances often to +-50%.

I realize this is more than you asked for, but I thought others may find useful. If not voted as useful, I may reduce my answers in future. (Typing
on an iPod is hard,with frequent incorrect spelling subs. but then I can be resting on the beach!)