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CL1
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
52 51 50 49 48 47 46 45 44 43 42 41 40
CL2 1 39 S19
/SYNC 2 38 S18
VLC1 3 37 S17
VLC2 4 36 S16
VLC3 5 35 S15
VSS 6 34 S14
VDD 7 33 VDD
/SCK 8 32 S13
SI 9 31 S12
/CS 10 30 S11
/BUSY 11 29 S10
C, /D 12 28 S9
/RESET 13 27 S8
14 15 16 17 18 19 20 21 22 23 24 25 26
NC
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
S5
S6
S7
BLOCK DIAGRAM
VLC1
LCD DRIVER
VLC2
LCD
TIMING
VLC3 CONTROL
DISPLAY DATA LATCH
/SYNC
CL1
BLINKING
SEGMENT DATA DATA
OSC DATA
DECODER MEMORY POINTER
CL2 MEMORY
VDD
VSS
/RESET
/CS
COMMAND/DATA REGISTER
WRITE COMMAND
C, /D
CONTROL DECODER
SI /SCK
1. PIN FUNCTIONS
……Input
……
1.1 SI (Serial Input)……
This pin is used for inputting serial data (commands/data). Data to be displayed as well as 19 deffernet
commands for controlling the operation of the µPD7225 can be input to this pin.
……Input
……
1.2 /SCK (Serial Clock)……
This pin is used for inputting the shift clock for serial data (SI input). The content of the SI input is read into the
serial register at the rising edge of this clock one bit at a time. /SCK input is effective when /CS = 0 and /BUSY = 1.
If /BUSY = 0, this input is ignored. If /CS = 1, this signal is ignored regardless of the /BUSY status.
……Input
……
1.3 C, /D (Command/Data)……
This input indicates whether the signal input from the SI pin is a command or data. A low level indicates data; a
high level indicates a command.
……Tri-state
……
1.4 /BUSY…… output
This is an active-low output pin that is used to control serial data input disable/enable. A low level disables serial
data input; a high level enables serial data input. This pin becomes high impedance when /CS = 1.
……Input
……
1.5 /CS (Chip Select)……
When /CS is changed from high level to low level, the SCK counter in the µPD7225 is cleared and serial data
input is enabled. At the same time, the data pointer is initialized to address 0. When /CS is set to high level after
serial data is input, the contents of the data memory are transferred to the display latch and displayed on the LCD.
……Input/Output
……
1.6 /SYNC (SYNChronous)……
The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking
operation is synchronized in a multi-chip configuration.
When the µPD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (fCL) divided by four (refer to
Figure 1-1), and synchronizes the system clock (fCL/4) of the µPD7225. When the reset is released (/RESET =1), the
display timing of each µPD7225 is synchronized with the common drive signal timing shown in Figure 1-2.
fCL
/SYNC
1 frame
Static
COM0
/SYNC
Divie-by-2 1 frame
time division
COM0
/SYNC
Divie-by-3 1 frame
time division
COM0
/SYNC
Divie-by-4 1 frame
time division
COM0
/SYNC
……Input
……
1.7 /RESET……
……Output
……
1.8 S0-S31 (Segment)……
……Output
……
1.9 COM0-COM3 (COMmon)……
A resistor is connected across these pins for internal clock generation. When inputting an external clock, use the
CL1 pin for input.
1.12 VDD
1.13 VSS
GND pin.