Counters

ENT 263 Digital Electronics

Objectives

• Describe the difference between an asynchronous and a synchronous

counter
• Analyze counter timing diagram
• Analyze counter circuits
• Determine the sequence of a counter
• …and more…
Counting in Binary
000 LSB changes on
001 every number.
010
The next bit
011 changes on every
100 other number.
The next bit
101
changes on every
fourth number. 110
111

LSB 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0

MSB 0 0 0 0 1 1 1 1 0
Asynchronous Counter Operation

• In an asynchronous counter, the clock is applied only to the

first stage. Subsequent stages derive the clock from the
previous stage.

– Asynchronous binary counter

• 2-bit asynchronous binary counter
• 3-bit asynchronous binary counter
• 4-bit asynchronous binary counter

– Asynchronous decade counter

• 2-bit asynchronous binary counter
• 3-bit asynchronous binary counter
• 4-bit asynchronous binary counter
• Asynchronous decade counter
Propagation Delay
 Synchronous Counter Operation
• Clock signal supplied to all Flip-flops
• Synchronous binary counters
– 2-bit counter
– 3-bit counter
– 4-bit counter

• Synchronous BCD decade counter

• 2-bit synchronous binary counter
0 1 0
• 3-bit synchronous binary counter
0 0 0 0 0

1 0
0
 • 4-bit synchronous binary counter

AND gate
outputs is
HIGH
Synchronous BCD decade counter
0 0 0 0
1 0
01 0 0
0 0 0
0 0
1 1 0 0 0 0
Up/Down Synchronous Counters

• 3-bit up/down synchronous counter

• Up/down decade synchronous
counter
3-Bit Up/Down Synchronous Counter
Up/Down Decade Synchronous
Counter
Design of Synchronous Counters
General clocked sequential circuit
Next State

Present State
Steps used in the design of sequential circuit
1. Specify the counter sequence and draw a state diagram
2. Derive a next-state table from the state diagram
3. Develop a transition table showing the flip-flop inputs
required for each transition. The transition table is
always the same for a given type of flip-flop
4. Transfer the J and K states from the transition table to
Karnaugh maps. There is a Karnaugh map for each
input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive
the logic expression for each flip-flop input.
6. Implement the expressions with combinational logic, and
combine with the flip-flops to create the counter.
State diagram for a 3-bit Gray code counter
Next-state table for a 3-bit Gray code counter.

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0
 Transition Table for a J-K flip-flop

Output Transitions Flip-flop Inputs

QN QN+1 J K
0 → 0 0 X
0 → 1 1 X
1 → 0 X 1
1 → 1 X 0
QN : present state

QN+1: next state

X: Don’t care
Example of the Mapping Procedure
Three-bit Gray code counter.
 Example:
Design a counter with the irregular binary count sequence
as shown in the state diagram. Use J-K flip-flops
 Next-state table

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 1 0
0 1 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 1
 Transition Table for a J-K flip-flop

Output Transitions Flip-flop Inputs

QN QN+1 J K

0 → 0 0 X

0 → 1 1 X

1 → 0 X 1

1 → 1 X 0
K-MAP
THE COUNTER CIRCUIT
Example : State diagram for a 3-bit up/down Gray
code counter.
J and K maps for Table 9-11. The UP/DOWN
control input, Y, is treated as a fourth variable.
Three-bit up/down Gray code counter.
 CASCADE COUNTERS
Two cascaded counters (all J and K inputs are HIGH).
A modulus-100 counter using two cascaded decade
counters.
Three cascaded decade counters forming a divide-by-
1000 frequency divider with intermediate divide- by-
10 and divide-by-100 outputs.
Example: Determine the overall modulus of the two
cascaded counter for (a) and (b)

For (a) the overall modulus for the 3 counter

configuration is 8 x 12 x 16 = 1536
for (b) the overall modulus for the 4 counter
configuration is 10 x 4 x 7 x 5 = 1400
A divide-by-100 counter using two 74LS160 decade
counters.
Cascaded Counters with Truncated Sequences
A divide-by-40,000 counter using 74HC161 4-bit binary counters.
Note that each of the parallel data inputs is shown in binary
order (the right-most bit D0 is the LSB in each counter).
216 = 65,536
65,536 − 40,000 = 25,536 ≈ 63C016
 COUNTER DECODING
* To determine when the counter is in a certain states
in its sequence by using decoders or logic gates.

Decoding of state 6 (110).

Active –High Decoding

Example: Implement the decoding of binary state 2 and
binary state 7 of a 3-bit synchronous counter. Show the entire
counter timing diagram and the output waveforms of the
decoding gates.

2 = 010 (𝑄2 𝑄1 𝑄0 )
7 = 111 (𝑄2 𝑄1 𝑄0 )
A 3-bit counter with active-HIGH decoding of count 2 and
count 7.
Decoding Glitches

A basic decade (BCD) counter and decoder.

Outputs with glitches from the previous decoder. Glitch widths
are exaggerated for illustration and are usually only a few
nanoseconds wide.
The basic decade counter and decoder with strobing to
eliminate glitches.

Strobing: To enable the decoded outputs at a time after the

glitches have had time to disappear. Using LOW level of active-
HIGH clock to enable the decoder.
Strobed decoder outputs for the circuit
Counter Applications
Simplified logic diagram for a 12-hour digital clock.
Logic diagram of typical divide-by-60 counter using 74LS160A
synchronous decade counters. Note that the outputs are in
binary order (the right-most bit is the LSB).
Logic diagram for hours counter and decoders. Note that on
the counter inputs and outputs, the right-most bit is the LSB.
Functional block diagram for parking garage control.
Logic diagram for modulus-100 up/down counter for
automobile parking control.
Parallel-to-serial data conversion logic.
Example of parallel-to-serial conversion timing for the
previous circuit
 Thank You
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