Experiment No.:1 Aim: To Study Logic Gates Apparatus

Datta Meghe College of Engineering, Airoli, Navi Mumbai Pin 400708
Dept: Information Technology

Name of Process: LAB MANUAL Doc. No.: Ver.No:0.0
LT/IT/III/ADC/01
Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 1 of 28
Experiment No.:1
Aim: To study Logic gates
Apparatus: 7400, IC7402, IC7404, IC7432, IC7486, IC7408, Register, Power Supply 5V, Bread board , LED &
connecting wires.
Theory: 1. AND Gate(IC 7408)

Logic Gate in which input A=1, B=1
If anyone i/p is 0 i.e, when Q1 is OFF or Q2 is OFF & o/p is y=0. If i/p A=1 i.e, i/p B=1 then Q1 is ON & Q2 is ON.
Circuit Diagram:
2) OR Gate: (IC 7432)
Prepared By Reviewed By Approved By Issued By
Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Bobade Devane Principal
Asst. Professor H.O.D Controlled copy if
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Theory:
Logic gate in which if i/p A=1 or i/p B=1 then o/p=1 is called as OR gate.If A=B=0
the transistor Q1 & Q2 is off so o/p y=0.
If i/p A=1 or if B=1 then Q1 is ON or Q2 is ON so o/p y is correct.
Circuit Diagram:
3) NOT Gate: (IC 7404)
Theory: It is called as inverter. When I=0 the o/p y=5V. If i/p A=1 then transistor Q is also 0
o/p is connected to ground.
Circuit Diagram:

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4) NAND Gate :(IC 7400)
Theory:
The NOT-AND gate is also known as NAND operation & has two i/p in the form of
digital signal applied to terminal A & B. The Logical expression for NAND gate is Y=AB
5) EX-OR Gate :(IC 7432)
Theory:
O/p of EX-OR gate is high only when i/p are different. i.e, one is high & other is low. The EX-OR
operation is widely used in digital circuits. The logical expression is y=AB+AB
Circuit Diagram:

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6) NOR Gate:(IC 7402)
Theory: The NOT-OR operation is also called as NOR operation . It is reverse of OR gate operation & is
obtained by inverter connected to o/p of OR gate & given by y=(A+B)
Circuit Diagram:

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Procedure:
1. Connect the LED & resistor in series with o/p of IC .

2. Ground pin no. 7 & connect Vcc=5V to pin no. 14 of the IC.
3. Draw the truth table for respective IC
4. Give the i/p according to respective truth table
5. verify the truth table.
Conclusion:
All gates are studied & truth tables are verified.
Experiment No.:2
Aim: To realise given equation y=AB + BC using basic gates & NAND gates.
Apparatus: IC7432, IC7408, IC 7404, IC7400,Register, Power Supply 5V, Bread board , LED & connecting
wires.
Truth Table:
A B C Y= AB+BC
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0

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1 0 1 1
1 1 0 0
1 1 1 0
Theory:
The above equation is implemented using basic gates. For this i/p is fed to one i/p
NAND gates through NOT& second i/p B is directly to first & gates whereas for second AND
gate inverted B is applied & C is directly given to OR gate to get o/p.
For NAND gate implementation i/p A is fed to the single i/p NAND gate & B is fed
directly to first NAND, whereas the second is single i/p B is fed to single i/p NAND gate & C is
directly fed. Then, the two NAND gate i/p’s are given to third NAND gate for required o/p.
Circuit Diagram:

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Procedure:
1. Connect the circuit as shown in circuit dig.
2. Verify the truth table.
Conclusion:
From the above experiment, we realise the given equation using basic gates y= AB+BC.
Experiment No.:3
Aim: To design a circuit for Half Adder, Half subtractor, Full Adder, Full subtractor.
Apparatus: IC7432, IC7408, IC 7404, Register, Power Supply 5V, Bread board , LED &
connecting wires.
Theory:
HALF ADDER
One function of adder circuit is to add given numbers. This is basic building block for
addition of two single bit numbers. The truth table shows two i/p’s A & B and two o/p’s Sum &
Carry. Drawback of this ckt. is multibit addition.
It does not look after carry, say if we want to add A & B in the next stage to add 3-
bits A,B,C which will not be done by circuit . Therefore, we have to design 3 bit adder circuit
which is named as Full adder.

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Truth Table:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
FULL ADDER
To overcome the drawback of half adder, we will design 3 bit adder which will consider carry which
comes from the previous bit .
Truth Table:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Half Subtractor:
In this i/p A & B are two single bit nos. & o/p’s are difference & borrow.
Truth Table:
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

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Full Subtractor : In half subtractor there is no provision to subtract the previous borrow, so we use full subtractor.
A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
CIRCUIT DIAGRAM:

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PROCEDURE:
1. Connect the circuit as shown in circuit dig. for half adder, full adder, half
subtractor & full subtractor.
2. Verify the respective truth table.
CONCLUSION:
Thus we have design a circuit for half adder, full adder, half subtractor & full subtractor and
verified the truth tables.
Experiment No.:4
Aim: To design & implement 4 bit parity generator using minimum number of gates.
Apparatus: IC7486, Register, Power Supply 5V, Bread board, LED & connecting wires.
Theory:
Parity Bit:
To get even or odd parity we have to take extra bit & that extra bit is called as
parity bit. If the total no of 1’s in a given no is even then it is called even parity & if the total no
of 1’s are odd then it is called odd parity.
In the truth table below we have consider four input variables A, B, C, D & two
o/p variables F(O)& F(E) for odd & even parity respectively. We will obtain the equation for
even & odd parity by using k-map & that equation by using the gates.
Truth table for 4-bit Even/ Odd parity generator.
A B C D F(O) F(E)
0 0 0 0 0 1
0 0 0 1 1 0

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0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 1
K – map for F(O):
K- map for F(E):

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Procedure:
1. Connect the circuit as shown in fig.
2. Apply +5V to Vcc & -5V to ground.
Conclusion:
Thus we have designed & implemented 4 bit parity generator using Ex-OR gate.

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Experiment No.:5
Aim: To study multiplexer to realise that f(A,B,C,D)=∑ M (0,1,2,3,8,9,11,13,14) using

16:1multiplexer.
Apparatus: IC 75150 Register, Power Supply 5V, Bread board , LED & connecting wires.
Theory:
Multiplexer or data selector is very popular & most widely used in combinational circuit. It has multiple
i/p’s & one o/p. It accepts several data i/p & allows one of them at a time to get through to o/p. The routing of
derived data i/p to o/p is controlled by select line.
In this select lines will decide which data i/p (D n-1- D0) will appear over o/p. The 16:1, 8:1,4:1 & 2:1 Mux
are available. The only change will be the no of select lines & data lines increases. Basic block dig is as shown.
16:1 MUX
Truth Table:
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
Procedure: 0 1 0 0 0
0 1 0 1 0
1. Connect the circuit as 0 1 1 0 0 shown in fig.
0 1 1 1 0
2. Apply high or low 1 0 0 0 1 select i/p as given.
1 0 0 1 1
3. Verify the truth table. 1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
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1 By
1 1 1 0 1
1 1 1 1 0

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Conclusion:
Thus we have studied multiplexer design for given problem & verified the truth table.
Experiment No.:6
Aim: To design & implement BCD to Gray code converter using demultiplexer.
Apparatus: IC74154(1:16) demux, ,Register, Power Supply 5V, Bread board , LED &
connecting wires.
Theory: Demultiplexer

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A demux perform opposite operation of the mux. i.e, it is having one i/p & several o/p’s.
The o/p can be related by means of control i/p . The truth table for 1L:4:L demux is shown. If
select line AB=11 o/p D3 will be selected. If i/p E is used as enable i/p the demultiplexer is
decoder. Demultiplexer/decoder can be used to implement logic function. They can be combined
in the form of trees.
Truth Table:
Cicuit Diagram:
BCD to Gray code converter
BCD CODE GRAY CODE

A B C D X Y Z W
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
Procedure:
Conclusion:
Thus we have designed & implemented BCD to Gray code converter using demultiplexer.

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Experiment No.:7
Aim: Design JK flip flop using NAND gates & verification if this FF using IC 7476.
Apparatus: IC7476, Function generator, Power Supply 5V, Bread board & connecting
wires,LED.
Theory: The memory elements used in sequential logic circuits for storing data is called as flip
flop. A flip flop is a bistable device which can remain in a particular binary state indefinitely
until an input signal switches its state from 1 to 0 or 0 to 1.

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JK Flip Flop
This is most widely used flip flop. The J & K i/p are similar to S & R i/p except that J=1 & k=1 is not an
illegal condition. The flip flop can accept J=1 & K=1 & it will toggle or change state with every clock
pulse when these i/p are given. Thus when J=0 & k=0 there is a change of state. The FF will remain in
whatever state it has been.
When J=1 & K=0 the FF will be set similar to condition S=1 & R=0. When J=0 & K=1 , the FF will
be reset similar to the condition S=0 & K=1. For the last condition J=1 & K=1, the FF will toggle or
changes state. If present state is 0 next state will be 1 & if present state is 1 next state will be 0.
Excitation Table for JK FF Pin dig for IC 7476
Inputs Output
JK FF
J K Q using
0 0 No change NAND
0 1 0 Gates
1 0 1
1 1 No change
Procedure:
3. Observe the result.


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Conclusion:
Thus we have designed JK FF using NAND gates.

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Experiment No.:1 Aim: To Study Logic Gates Apparatus

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Datta Meghe College of Engineering, Airoli, Navi Mumbai Pin 400708

Dept: Information Technology

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 1 of 28

Aim: To study Logic gates

Theory: 1. AND Gate(IC 7408)

2) OR Gate: (IC 7432)

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 2 of 28

3) NOT Gate: (IC 7404)

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 3 of 28

4) NAND Gate :(IC 7400)

5) EX-OR Gate :(IC 7432)

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 4 of 28

6) NOR Gate:(IC 7402)

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 5 of 28

1. Connect the LED & resistor in series with o/p of IC .

All gates are studied & truth tables are verified.

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 6 of 28

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 7 of 28

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 8 of 28

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 9 of 28

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 10 of 28

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 11 of 28

Truth table for 4-bit Even/ Odd parity generator.

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 12 of 28

K- map for F(E):

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 13 of 28

1. Connect the circuit as shown in fig.

2. Apply +5V to Vcc & -5V to ground.

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 14 of 28

Aim: To study multiplexer to realise that f(A,B,C,D)=∑ M (0,1,2,3,8,9,11,13,14) using

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 15 of 28

Prepared By Reviewed By Approved By Issued By

Prof. Sunil Prof. Satish Dr.S.D.Sawarkar

Experiment No: Year/Sem: SE-III Date: 08-07-2013 Page 16 of 28

BCD CODE GRAY CODE

1. Connect the circuit as shown in fig.