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IC Nanometer Design
The IC Nanometer Design package provides a complete environment for the design, capture, layout and
verification of analog, digital and mixed-signal integrated circuits. This package includes all products that
incorporate the IC Nanometer Design platform

The Pyxis suite of IC design tools

 Schematic capture, netlisting, simulation setup and results viewing.
 Physical layout
 Editing, schematic-driven layout, and top-level floorplanning and routing.

The Questa ADMS analog and mixed signal verification suite

 Questa ADMS and Questa AMDS RF - A language-neutral, mixed-signal simulator that enables
top-down design and bottom-up verification of multi-million gate analog/mixed-signal SoC
designs.
 Eldo and Eldo RF - An analog simulator offering numerous simulation and modeling options that
deliver high-performance and high-speed simulation with the accuracy required by the user.
 ADiT™ - A fast-SPICE simulator built specifically for analog and mixed-signal applications.

The Calibre product line for physical verification and design for manufacturability of deep sub micron
integrated circuits
 Calibre - The industry standard platform for physical verification, offering superior performance
and capacity for both flat and hierarchical algorithms.
 Calibre xRC - Accurate transistor-level, gate-level and hierarchical parasitic extraction.

CoreEl Technologies (I) Pvt Ltd

#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com
Key Features

Pyxis suite
 Integrated with Pyxis Custom IC Design Platform, providing a unified capture, implementation
and layout automation flow
 Enables changes to layout based on updates to the schematic at any point in the design cycle
 Single application provides design capture, simulation control, and results viewing for analog, RF,
and mixed-signal designs.
 Specialized schematic constructs that are tailored to IC design increase design capture efficiency.

Questa ADMS
 For 25 years, Eldo has been used to verify and successfully fabricate thousands of ICs, from the
most modest ones to huge mixed-signal SoCs, in all domains of applications, from defense to
communications to automotive.
 The Mentor Graphics® Eldo™ RF simulator handles Full-chip RF IC verification for wireless
applications.
 Mentor's analog/mixed-signal verification tools offer a language-neutral verification environment
for complex analog/mixed-signal System-on-Chip designs.
 Single verification platform for AMS design and verification: system, block, and integration with
integrated post-layout simulation for analysis.
 Enables top-down design and bottom-up verification of multi-million gate AMS SoC designs.

Questa ADMS
 Direct access to Milkyway, LEF/DEF, OpenAccess, OASIS, and GDSII design databases.
 Provides the fastest methods possible to identify and repair LVS issues, including complex power-
to-ground short circuits.
 Seamless interface within many design environments.
 Delivers unparalleled performance on ASIC, memory, analog, SoC designs, etc. with no trade-off
in accuracy.
 Single rule file can drive DRC, LVS, and Calibre xRC functionality.
 Reads LVS data structures to integrate parasitic information with intentional circuit elements.

Platform
Operating System
 Linux RHEL 6.4 (64 bit)
Note: Platform is dependent on tool.

CoreEl Technologies (I) Pvt Ltd

#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com
 Custom IC Design
Mentor’s new Pyxis Custom IC Design Platform includes integrated solutions for design capture,
floorplanning, custom routing, polygon editing, physical layout, schematic-driven layout, concurrent
editing and chip assembly. To help companies jump-start their design cycles and cut time-to-market,
Mentor Graphics and its foundry partners have developed design kits.

Mentor Graphic’s Custom IC flow and its integrated schematic, extraction and simulation tools allow you
to take a design from system specifications to post-layout verification with a virtually seamless approach.

Key Features

 Single application provides design capture, simulation control, and results viewing for analog, RF,
and mixed-signal designs.
 Specialized schematic constructs that are tailored to IC design increase design capture efficiency.
 Enables engineers to conduct faster and more accurate mixed signal IC verification.
 Integrated with Pyxis Custom IC Design Platform, providing a unified capture, implementation
and layout automation flow.
 Improves layout design throughput up to 50X compared to manual layout methods.
 Multiple tools support increasing levels of layout automation.
 Reduces design rule checking (DRC) debugging cycles, leading to shortened time-to-market.
 Verifies DRC and layout vs. schematic (LVS) correctness throughout the layout process, without
adding complicated steps.
 Creates DRC/LVS–correct complex layout with a simple command to improve reliability of final
product.
 Enables changes to layout based on updates to the schematic at any point in the design cycle.
CoreEl Technologies (I) Pvt Ltd
#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com
Products

Pyxis® Schematic
Mentor Graphics Pyxis® Schematic is a powerful environment for capturing designs and their verification
within a full custom design flow. Pyxis Schematic works with other solutions in the Pyxis Custom IC Design
Platform to conceptualize, develop, simulate, verify, and implement to produce even the most challenging
full custom analog and mixed-signal IC designs quickly and accurately—the first time. As a designer, you
enjoy a consistent look and feel in single environment, whether creating schematics, block diagrams,
symbols, or HDL representations.

Pyxis® Layout
Pyxis® Layout supports an extensive set of editing functions for efficient, accurate polygon editing. This
gives the design engineer full control of circuit density and performance, while improving productivity by
as much as 5X. Hierarchy and advanced window management allows multiple views of the same cell and
provides the capability to edit both views. Additionally, design engineers can create matched analog
layouts quickly by editing using a half-cell methodology.

Pyxis® Implement
Pyxis® Implement combines all of the functionality of Pyxis Layout with a hierarchical SDL (Schematic-
driven layout) environment, enabling design engineers to quickly create complex designs without
sacrificing layout quality. Schematic-driven layout (SDL) is a design methodology that enables design
engineers to create "correct by construction" layouts.

SPECIFICATIONS
Operating System
 Linux RHEL 6 x86-64

Additional Information
 Design Kit provided by Europractise.

Analog / Mixed-Signal Verification

Questa ADMS combines four high performance simulation engines in one efficient tool: Eldo Classic for
general purpose analog simulations, Questa for digital simulations, ADiT™ for fast transistor-level
simulations and Eldo RF for radio frequency simulations.

CoreEl Technologies (I) Pvt Ltd

#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com
Key Features

 For 25 years, Eldo has been used to verify and successfully fabricate thousands of ICs, from the
most modest ones to huge mixed-signal SoCs, in all domains of applications, from defense to
communications to automotive.
 The Mentor Graphics® Eldo™ RF simulator handles Full-chip RF IC verification for wireless
applications.
 Mentor's analog/mixed-signal verification tools offer a language-neutral verification environment
for complex analog/mixed-signal System-on-Chip designs.
 Single verification platform for AMS design and verification: system, block, and integration with
integrated post-layout simulation for analysis.
 Enables top-down design and bottom-up verification of multi-million gate AMS SoC designs.
 Lets designers combine language and simulation algorithms to fit the task.
 Universally accepts IP written in any of the standard design languages for easy migration.
 Empowers high-level, system-level design, architectural exploration, and rapid learning of
behavioral modeling techniques.
 Questa ADMS RF preserves transistor-level accuracy wherever it is necessary.
 Integrated RF and mixed-signal baseband simulation. Supports behavioral RF modeling in Verilog-
A.
 Efficient time-frequency domain simulation with multi-GigaHertz carrier frequencies.
 Superior Cell Characterization.
 ADiT delivers good results out-of the-box without time-consuming option tuning.

Products

Questa®
The Questa® Advanced Simulator combines high performance and capacity simulation with unified
advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL,
SystemC, PSL and UPF. The Questa Advanced Simulator is the core simulation and debug engine of the
Questa Verification Platform; the comprehensive advanced verification platform capable of reducing the
risk of validating complex FPGA and SoC designs.

Questa ADMS RF
CoreEl Technologies (I) Pvt Ltd
#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com
Integrated RF and Mixed Signal Simulation for Complete Verification of RF-DSP Systems. Complete
simulation of RF system-on-chip (SoC) designs becomes a reality when you combination the RF
capabilities of Eldo RF with the mixed signal capabilities of Questa ADMS. Built upon these solid
foundations, the Questa ADMS RF solution allows effective simulation of communication systems
containing tightly linked RF and baseband functions—analog and digital.

ADiT™
The Mentor Graphics ADiT™ (Analog Digital Turbo Simulator) is an advanced Fast-SPICE simulation tool
targeting analog and mixed-signal (AMS) transistor level applications. It features a mixed-signal aware
partitioning algorithm that allows fast and accurate simulation of circuits with non-ideal power supplies.

Eldo®
The Eldo™ simulator offers numerous simulation and modeling options that deliver high-performance and
high-speed simulation with the accuracy required by the user. Eldo Classic is the simulator of choice for IC
silicon vendors and fabless design centers because of its speed, accuracy, and capacity. Eldo Classic’s
capabilities can be further extended with VerilogA analog behavioral modeling, advanced RF analysis with
Eldo RF, or mixed signal with Questa ADMS RF.

Eldo® RF
The Eldo™ RF extends the Eldo transistor-level simulator into the realm of RF IC design. Eldo® RF provides
the necessary performance and capacity breakthroughs for RF IC simulation, taking the baton where
existing tools reach their limits. Eldo RF provides a set of dedicated algorithms to accurately and
efficiently handle the multi-GHz signals in modern wireless communication applications.

SPECIFICATIONS
Operating System
 Linux RHEL 6 x86-64

Additional Information
 Extensive device model libraries include leading MOS, bipolar and MESFET transistor models such as
BSIM3v3.x, BSIM4.3, EKV, Philips MM9 & MM11, SPv32, HiSIM, Mextram, VBIC, and HICUM etc.
 Eldo-certified electrical models are available from major foundries such as TSMC, UMC, Chartered,
and STMicrolectronics.
 The raw maximum capacity of Eldo® is limited only by the amount of available RAM.

Physical Verification
Calibre's physical verification capabilities are the industry standard for accuracy, reliability, and
performance. Calibre® nmDRC, Calibre® nmLVS and Calibre® xRC are the market share leaders in physical
verification.

Circuit Verification involves several essential steps in the design process that will help identify potential
circuit or design errors as well as extract the necessary data for downstream circuit simulation. During this
step, layout is analyzed and compared vs. the schematic to ensure design integrity. Second, the design is
analyzed for short-term and long-term electrical failures and, if found, those are presented to the
designer for fixing. And finally, a detailed silicon model is constructed with intentional device, advanced

CoreEl Technologies (I) Pvt Ltd

#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com
parameters, and parasitic information into a format that consumed by a downstream simulator so that
designers can reliably determine if their design is meeting electrical specifications (timing, power, etc.)

Key Features

 Advanced Equation-based DRC enables advanced checking without complex rule decks for
reduced area and improved tolerance to manufacturing variability. Supports the open standard
TCL/TK macro language for extensive tool customization.
 Dramatically reduces time to tape-out with robust revision and iteration loop capabilities.
 Allows convenient re-verification of the full design, or only the data that has been modified.
 Efficiently automates chip finishing tasks..
 Direct access to Milkyway, LEF/DEF, OpenAccess, OASIS, and GDSII design databases.
 Provides the fastest methods possible to identify and repair LVS issues, including complex power-
to-ground short circuits.
 Seamless interface within many design environments.
 Delivers unparalleled performance on ASIC, memory, analog, SoC designs, etc. with no trade-off
in accuracy.
 Single rule file can drive DRC, LVS, and Calibre xRC functionality.
 Reads LVS data structures to integrate parasitic information with intentional circuit elements.
 Model-based engine calculates intrinsic and coupling capacitances for all nets using the same
high degree of accuracy.

Products

Calibre® nmDRC
To ensure acceptable design performance in new process technologies, foundries iteratively explore
design constraints and manufacturability to define the design rules ultimately used by their customers.
The physical verification tool used by every major foundry to develop these design rules is Calibre®
nmDRC. What that means to you is that Calibre rule decks are proven long before you need them. When
performance and time to market control potential profitability, using Calibre nmDRC for your physical
verification can mean the difference between market success and failure.

Calibre® nmDRC
Calibre® nmLVS, the market-leading layout vs. schematic physical verification tool, is tightly linked with
both Calibre nmDRC and Calibre xRC to deliver production-proven device extraction for both physical
verification and parasitic extraction. Calibre nmLVS performs a vital function as a member of a complete
IC verification tool suite by providing device and connectivity comparisons between the IC layout and the
schematic. Calibre’s hierarchical processing engine runs Calibre nmLVS, supplying data for modifying the
CoreEl Technologies (I) Pvt Ltd
#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com
IC design to achieve superior functionality and reliability. Calibre nmLVS enables accurate circuit
verification because it is able to measure actual device geometries on a full-chip for a complete
accounting of physical parameters. These precise device parameters supply the information for back
annotation to the source schematic and the comprehensive data for running simulations. In addition to
working with Calibre xRC, Calibre nmLVS can also be used with third party parasitic extraction tools.

Calibre® xRC™
Calibre® xRC™ is a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive
and accurate post-layout analysis and simulation. Calibre xRC is able to extract interconnect parasitics
hierarchically.

SPECIFICATIONS
Operating System
 Linux RHEL 6 x86-64
Additional Information
 Calibre is not only supported by the foundries, it is the GOLD standard.
 Foundry Partnership with Mentor to Define the Physical Verification Roadmap.
 Mentor Graphics Physical Verification Tools Fully Enabled on Intel’s 14nm Processes for
Customers of Intel Custom Foundry

CoreEl Technologies (I) Pvt Ltd

#21, 7th Main, I Block, Koramangala, Bangalore – 560 034
Tel: 91-80-4197 0400/2522 6775 Fax: 080- 2522 8955 Website: www.coreel.com