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Analysis of Very Fast Transient Over Voltages in GIS and its Mitigation
Techniques

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International Conference on High Voltage Engineering and Technology
(ICHVET-2015)-January 29-30, 2015, Hyderabad

Analysis of Very Fast Transient Over

Voltages in GIS and its Mitigation
Techniques
1 *1 2
K.Rathan, P.Dhananjay S.Rengarajan
1
Goldstone Infratech Limited, Cherlapally, Hyderabad, India
2
Department of Electrical and Electronics Engineering
Aurora’s Engineering College, Bhongir, India
Email: rathan@goldstone.net, dhananjay@goldstone.net, srenga_49@yahoo.com

Abstract— A unique problem in a GIS is the generation of is necessary to understand the conditions, at which VFTO
very fast transient over voltages (VFTO), when the is generated, employ suitable mitigation methods and
disconnector switches or circuit breakers operate. During thereby coordinate the insulation system. In a GIS, VFTO
such a switching operation, an arc is developed in between is generated during the operation of circuit breakers or
the contacts which involves both ionization and
disconnector switches and also during a ground fault. In
recombination processes. The resulting breakdown occurs in
a very short duration, resulting in high frequency all these events breakdown of SF6is involved.
overvoltage oscillations that may result in an inadvertent
electrical breakdown of a peripheral system. In the present In this paper, a VFTO is simulated due to the
paper, a GIS busduct with disconnector switches and a operation of either a disconnector or a circuit breaker in a
circuit breaker is represented and VFTO is simulated using GIS system and analysed. Also, effects of bay length and
an arc model. Effects of bay length and impedance change at impedance change at the open end on the magnitude of
an open end on the magnitude of VFTO are studied. The VFTO are studied. The VFTO generation is effected by
simulation is done using EMTP. Further, a laboratory considering an arc model viz., a piece-wise time varying
method of simulating VFTO practically is discussed. Finally,
resistor. A GIS bay with two disconnector switches and a
some terminations at the open end to mitigate VFTO are also
analysed. circuit breaker along with a load are simulated by EMTP
programme.
I. INTRODUCTION
Further, VFTO is practically generated in a model
Gas Insulated Substations (GIS) are widely used in
GIS bay by creating a breakdown of SF6 insulation system
electrical power systems due to their advantages viz.,
within a spark gap. The VFTO wave generated has been
immunity to pollution, compact in size, less maintenance
studied and compared with the results of the theoretical
and high reliability. However, a GIS has a unique
simulation. Lastly, methods to mitigate this effect have
problem. The SF6 gas, which is the main insulation used in
also been discussed.
GIS is highly electro-negative. Hence the breakdown in
SF6 gas involves both ionisation as well as the
recombination processes [1]. As a result, the breakdown II. SYSTEM UNDER STUDY
occurs in a short duration and this generates a very fast
rising overvoltage namely VFTO. It is considered as an
important factor in the insulation design of UHV GIS as it
belongs to the very high frequency range of transients in
power systems [2]. It has a very short rise time, ranging
from 4 to 100 ns and normally followed by oscillations
having frequencies in the range of 100 kHz to 50 MHz
Further, this voltage being a travelling wave gets reflected Figure 1: Circuit model under study.
at open ends and thereby multiplied. When such a voltage
impinges an inductive load like a transformer, its The system consists of a single phase busduct which is
distribution inside the windings is highly non-uniform that divided into two halves and connected to a 400 KV bus at
leads to an inter-turn failure near HV terminals. Hence, it one end through disconnector A (DS-A). On the other end,

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International Conference on High Voltage Engineering and Technology
(ICHVET-2015)-January 29-30, 2015, Hyderabad

one half of the bus duct is feeding a load of 100 MVA
through disconnector B (DS-B), circuit breaker (CB) and a
small transmission line. The other half of the bus duct is
left open at the far end as shown in Figure 1. The EMTP
representation of this system is depicted in Figure 2. The
system is studied for single phase operation only.
the GIS installation can be considered as a series of
distributed transmission line and lumped capacitor
elements. The values of each GIS section can be
calculated from the standard formula of capacitance and
inductance as shown below, treating the GIS as concentric
cylinder geometry. The modelling of the GIS is therefore a
combination of distributed and lumped parameters, as it is
summarized in Table 1 [4,5].

GIS component Modelling parameter

Closed Distributed transmission
Circuit breaker line.
Open Distributed transmission
line in series with grading
capacitor and an arc model
in parallel.
Disconnector Closed Distributed transmission
line.
Open Distributed transmission
line in series with capacitor
(contact gap) and an arc
model in parallel.
Earth switch Open Lumped capacitor to earth.
Cone insulator, line
bushing, power Lumped capacitor to earth.
transformer with line
Figure 2: Equivalent Circuit model in EMTP. bushing, VT and CT
Busbar Distributed transmission
III. EMTP MODELLING OF GIS COMPONENTS line
The source is represented by its peak value of the phase Overhead line π network terminated with
voltage i.e.400*√2/√3 kV with its short circuit impedance. a load.
Various components viz., voltage transformers, surge
arresters and earth switches are predominantly represented Table 1: GIS components to be modelled.
as capacitive loads as seen by a very high frequency wave
like VFTO. Disconnectors A and B (DS-A and DS-B) and The capacitance per unit length of the GIS is given as
circuit breaker (CB) are simulated as simple time
controlled switches. Across each such switch, an arc
model, which is represented by a piece-wise time varying
resistance, is connected. The simulation is made in such a
way that as soon as the breaker or a disconnector switch
opens, the arc model which is in parallel is connected into The internal inductance of the conductor is given as
the circuit. The switch or breaker opens with a chopping
current of 5 Amperes. At a given time only one switch is
allowed to open keeping the others closed.

With switching conditions where GIS As there is no other current carrying conductor, no mutual
disconnectors or circuit breaker are opened, it is possible inductance is involved.
to generate VFTO, which act as a travelling wave that
propagates within and outside the GIS. In view of the
travelling wave nature of the VFTO, the GIS bus duct is
modelled as electrical equivalent circuits comprised of
distributed parameter lines (defined by surge impedance
and travelling times) and other components as lumped
elements [3]. In order to achieve a reliable simulation, the
GIS is subdivided into several shorter sections. As such

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International Conference on High Voltage Engineering and Technology
(ICHVET-2015)-January 29-30, 2015, Hyderabad

Where, C and L are the capacitance and the inductance of their magnitudes. A breakdown phenomenon across the
the GIS bus bar, respectively. D is the outside diameter of contacts of a disconnector during a switching operation
the GIS bus bar and d is the diameter of the GIS current leads to an arc formation in SF6 gas, generating a very
conductor. Z0 is the surge impedance and v is the short rise time travelling wave which propagates in either
propagation velocity. The modeling of arc for the purpose direction from the breakdown region. It travels throughout
of VFTO involves only a single arc model. GIS and to other connected equipment. It also gets
reflected
IV. PRACTICAL SIMULATION OF VFTO
VFTO can also be simulated experimentally in a
pressurized model bus duct as indicated in Fig.3 [6]
This set up consists of a bus duct with a central conductor
supported by epoxy cast cone insulators fixed inside an
outer metal enclosure which is earthed. The central
conductor has an adjustable gap. On one side of the gap
high voltage is applied whereas the other end is left as an
open end without any termination. When a high voltage is
applied to the central conductor and increased, at a given
point the SF6 gap breaks down, resulting in VFTO
travelling over the conductor. Figure 4: Experimental setup of VFTO analysis. The
capacitor couple is seen on the top of the bus duct.
VFTO is captured by a special capacitive coupler
that is mounted on the enclosure. The coupler is connected and refracted at every impedance transition point. As a
to a 50 Ω cable which in turn connected to a digital consequence of multiple reflections and refractions,
oscilloscope with a 50 Ω termination. The experimental magnitude of travelling wave increases above the original
set up is shown in Fig 4. The VFTO obtained from the value and very high frequency oscillations occur. The
experimental set up is shown in Fig 5. The pattern of highest overvoltage is generated at the open end of the
VFTO is thus verified from the results of the experimental load side. The maximum value of the VFTO voltage is
set-up. dependent on the voltage drop at the disconnector just
before striking.

When DS-A is operated, remaining switches (i.e.,

DS-B and the CB) are kept closed and vice versa. After
opening of DS-A, instantaneously the auxiliary switch
between nodes AD12 and AD13 is closed so that arc
model will come into picture which generates a high
frequency voltage, resulting in generation of VFTO with a
Fig 3: Bus duct setup to analyse VFTO property of travelling wave nature. The travelling wave
causes different voltages with high frequencies at various
1- Non communicating insulator nodes due to reflection and refraction of travelling wave at
2- Communicating insulator every impedance transition point.
3- Gas filling port
4- Conductor Fig.6 depicts the voltage waveform at node
5- Gap AD06 i.e. at the start of the bus duct and immediately after
6- Capacitive divider port DS-A. Operation of DS-A also results in a high frequency
7- Dish end high voltage wave at open end of the busduct i.e. at node
8- 291Ø, 225mm long BS17 as depicted in Fig 7. The first peak rise time is 29
9- 291Ø, 450mm long ns, hence it is a VFTO and the simulation results show a
10- 291Ø, 1040mm long similar wave-shape obtained from the experiments.
11- Viewing port Operating DS-B and CB gives marginally higher
magnitude of voltage than that due to operating DS-A at
node BS17 and the time taken to reach peak is 25.2 ns,
V. RESULTS AND DISCUSSIONS Fig.8 and Fig 9 depict these voltage waveforms at BS17.
This can be attributed to the length of the bay. When
In GIS substations some bus ducts are left open for future transients are generated at DS-B or CB they travel twice
expansion to meet the increase in load demand. Such open the distance before reaching the open end when compared
ends make travelling waves to reflect and thereby increase

Analysis of Very Fast Transient Over Voltages in GIS and its Mitigation Techniques Page 106
International Conference on High Voltage Engineering and Technology
(ICHVET-2015)-January 29-30, 2015, Hyderabad

to the wave from DS-A. Since the magnetic energy stored

is higher in the former case, it can cause a more severe
VFTO. However the difference is marginal as the length
of bay is limited.

It is observed that though the oscillating

frequency is very high, the magnitude of VFTO is around
2pU [7]. If the magnitude is less than the MCOV, then it
remains in the system and the oscillating frequency is a
concern. Such a voltage creates highly non-uniform
voltage distribution in the windings of a transformer or
any rotating machine. However, the VFTO magnitude and
frequency of oscillations were reducing when moving
towards load side under similar conditions. At load, the
voltage waveform changed nearer to sinusoidal waveform,
because the transients were dissipated due to circuit
resistance. Fig. 10 exhibits the voltage waveform at load Figure 7: VFTO at open end of the busduct, at node BS17
i.e., at node RD26. when disconnector A is operated.

Figure 5: Measured VFTO waveform from experimental

set-up.
Figure 8: VFTO at open end of the busduct, at node BS17
when disconnector B is operated.

Figure 6: Voltage waveform at node AD06 when DS or

Figure 9: VFTO at open end of the busduct, at node BS17
CB is operated.
when CB is operated.

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International Conference on High Voltage Engineering and Technology
(ICHVET-2015)-January 29-30, 2015, Hyderabad

Figure 11: Voltage waveform at BS17 when RC-surge

Figure 10: Voltage at load (node RD26) when DS or CB is
suppressor is used.
operated

VI. EFFECTS AND MITIGATING TECHNIQUES OF

VFTO
The main effects of generation of VFTO are Direct
connected transformers can experience an extremely
nonlinear voltage distribution along the high voltage
winding, connected to the SF6 - oil bushings, due to steep
fronted wave impulses.

Transient current in the earth circuit in case of a fault may

interfere with secondary equipment or damage sensitive
circuits, by raising the housing potential if they are
directly connected or through cable shields to GIS
enclosure by emitting free radiation which may induce
currents and voltages in adjacent equipment.

Two methods are analysed to suppress VFTO at open end

of busduct-2 i.e., at node BS17. They are a) connecting
RC surge suppressor b) a capacitor. RC suppressors (R in
series with C) have been widely used to dissipate the
transients. R is used to make energy attenuates and C
reduces the circuit oscillation frequency. Here, R is varied
from 50 Ω to 400 Ω and C is changed from 0.01μF to 0.2
μF. The optimum mitigation of the VFTO is found when
R equal to 50 Ω and at C equal to 0.02 μF. Connecting RC
suppressor at open end greatly reduces the magnitude and
frequency of oscillations, Fig.11 exhibits the mitigated
voltage waveform at open end of the bus duct (at BS 17).
Figure 12 indicates the reduced voltage waveform at open
end of the bus duct by connecting a simple capacitor at
BS17 as it offers less impedance for high frequency
components.
Figure 12: Voltage waveform at BS17 when capacitor is
used.
It is observed that a two methods exhibit a similar result
and hence a simple big capacitor can reduce the effect of
the severity of VFTO.
VII. CONCLUSIONS
VFTO in GIS is of greater concern at the higher voltage
systems for which the ratio of the BIL to the system
voltage is low. Generation of VFTO can cause high non-
uniform voltage distributions in the windings. In this
paper VFTO has been simulated in a GIS by introducing a
suitable arc model using EMTP. Effects of bay length and
open end without termination on VFTO are also
simulated. A method to practically simulate the VFTO
was also discussed. Finally methods to mitigate VFTO
with different terminations were studied.

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 International Conference on High Voltage Engineering and Technology
(ICHVET-2015)-January 29-30, 2015, Hyderabad

ACNOWLEDGEMENTS in India. Presently he is working as a professor in Aurora’s

Engineering College.

The first two authors are thankful to the management Ms.

Goldstone Infratech Limited for the permission to publish
this paper and Mr. B. Kiran Kumar Reddy, GM
(Technical) for his constant encouragement and
motivation. The third author would like to thank the
management of Aurora’s Engineering College for
motivating and encouraging research work and
publications.

REFERENCES

[1] [1] O. Farish, M.D. Judd, B.F. Hampton and J.S. Pearson “ SF6
Insulation Systems and their monitoring- Advances in High
Voltage Engineering” Power and energy Series 2004.
[2] “
[2] E.E. Henriksen, Study of very fasttransient overvoltages in
Transformers (VFTO)”, ELECTRA, No 179, August 1998.
[3] [3] EMTP Hand Book.
[4] [4] JA Martinez(Chairman), P. Chowdari, R. Iravani, A. Keri, D.
Povh “ Modelling Guidelines for Very Fast Transients in Gas
Insulated Substations” by The VFT Task Force of the IEEE
working group.
[5] [5] M.S. Naidu “ Very Fast Transient Overvoltages in Gas
Insulated Substations” Workshop on Gas Insulated systems, Central
power Research institute , Bangalore, India, December 1998.
[6] [6] M. Mohan Rao, H.S. Jain, S. Rengarajan, K.R.S. Sheriff and
S.C.Gupta “ Measurement of very fast transient
overvoltages(VFTO) in a GIS module” 11th International
Symposium on High Voltage Engineering, Ish99, August 1999.
[7] [7] Mariuszn Stosur, Marcin Szewczyk, Wojciech Piasecki, Marek
Florkowski, Marek Fulczyk “ GIS Disconnector Switching
Operation- VFTO Study” ABB Corporate Research Center in
Krakow, Poland.

K.Rathan pursued B.Tech degree in Electrical &

Electronics Engineering from JNTU Hyderabad.
Presently working at Goldstone Infratech Limited,
Cherlapally, Hyderabad. His areas of interest are Gas
Insulated substations, Transformers and Power
systems

P. Dhananjay pursued B.Tech degree in Electrical &

Electronics Engineering from JNTU Hyderabad.
Presently working at Goldstone Infratech Limited,
Cherlapally, Hyderabad. His areas of interest are Gas
Insulated substations, Surge arresters and Power
systems.

S. Rengarajan obtained his B. E (Electrical) degree from

Madurai-Kamaraj University and M.Sc (High Voltage
Engineering) degree from Indian Institute of Science. He
also got his PG diploma in Management from All India
Management Association (AIMA). He had a brief stint at
Karnataka Power Corporation before joining BHEL
(Corporate R&D). At BHEL he led many research
projects, pertaining to High Voltage Engineering. He
also carried out many investigations at various BHEL sites, which
include solving of problems and RLA of power equipment. He
planned and designed a 765 kV system HV test laboratory. He has
many national and international publications, which includes papers
in IEEE and R&D management journals. He has filed eight patents

Analysis of Very Fast Transient Over Voltages in GIS and its Mitigation Techniques Page 109

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