NCG WRITTEN TEST – May ‘07

Instructions:

1. Fill in your name and the centre details in the space provided below
2. Duration of the written test is one hour
3. Answer all questions
4. Each question carries one mark
5. Negative marking applies: Each wrong answer will be marked -0.5

NAME:

CENTRE LOCATION:

NCG Written Test – May’07 1/17

1. A cup of milk contains 3 parts of pure milk and 1 part of water. How much of the mixture is
to be withdrawn and substituted with water in order that the resulting mixture may have
half milk and half water?

(a) ½
(b) 1/3
(c) ¼
(d) 1/5 Answer:
(e) None of the above

2. A number of friends decided to go on a picnic and planned to spend Rs.96 on eatables. Four
of them however did not turn up. As a consequence each of the remaining ones had to
contribute Rs. 4 extra. The number who attended the picnic was:

(a) 24
(b) 16
(c) 12
(d) 8
(e) None of the above Answer:

3. A and B are two stations 500KMs apart from each other. A train starts from A and moves
towards B at a speed of 20km/hr. Another train starts from B at the same time and moves
towards A at a speed of 30km/hr. How far from A will they cross each other?

(a) 40 km
(b) 200 km
(c) 300 km
(d) 120 km Answer:
(e) None of the above

4. The area of triangle whose vertices are (0,0, (1,0), (0,1) is

(a) 1
(b) 2
(c) 1/2
(d) 2/3 Answer:
(e) None of the above

5. The event E1 and E2 have probabilities 0.25 and 0.50 respectively. The probability that
both E1 and E2 occur simultaneously is 0.14. The probability that neither E1 nor E2 occurs
is:

(a) 0.39
(b) 0.25
(c) 0.11
(d) 0.18 Answer:
(e) None of the above

NCG Written Test – May’07 2/17

6. Three horses H1, H2 and H3 enter a grass-field which has six distinct portions marked P1,
P2, P3, P4, P5 and P6. If not more than one horse can enter the same portion and each
horse grazes at least one portion, they can graze of the field in

(a) 36 ways
(b) 18 ways
(c) 180 ways
(d) 120 ways
(e) None of the above Answer:

7. If the diameter of a wire is decreased by 5 percent, by how much percent will the length
be increased if the volume remains the same?

(a) 2.5
(b) 5
(c) 10
(d) 10.8
(e) None of the above Answer:

8. Refer figure below:

R1 R2

D combi
logic

Clk

• The delay through combi logic is ‘t’.

• The clock skew is ‘s’ (Assume positive skew)
• The setup time for the flop is ‘t_su’ and hold time is ‘t_hold’
• Ignore clock-to-q delay

Select the most appropriate answer for the following questions (i and ii):

i. What is the maximum frequency of operation of the circuit?

(a) 1/(t + t_su)

(b) 1/(t + t_su + s)
(c) 1/(t+t_su – s) Answer:
(d) 1/(t – t_su – s)

ii. If the logic had a minimum delay (or the contamination delay) of ‘t_cd’ then which
equation would apply for the above stated conditions?

(a) t_hold < t_cd

(b) s < t_cd
(c) t_hold < t_cd – s Answer:

NCG Written Test – May’07 3/17

9. The largest positive number in n-bit 2’s complement representation is

(a) 2n
(b) 2(n-1) – 1
(c) 2(n-1)
Answer:
(d) 2n + 1

10. How many 2-input NAND gates would be required to form a M-input NAND gate?

(a) 2M + 1
(b) 2M – 1
(c) 2M - 2
(d) 2M - 3 Answer:

11. What is the minimum number of 2-input NAND gates required for implementing AB’ + A’B?

(a) 3
(b) 4
(c) 5
(d) 6 Answer:

12. For a Johnson counter using N-flip flops, the length of the counting sequence is

(a) 2N
(b) 2N
(c) N–1
(d) N
Answer:

13. In an ‘M’-level pipelined system, if the operating voltage is reduced by a factor of ‘B’, then
the power consumption of the pipelined system

(a) Increases by a factor MB

(b) Reduces by a factor B
(c) Reduces by a factor B2
(d) Increases by a factor MB2
(e) Reduces by a factor B2/M Answer:

14. The most negative number in n-bit 2’s complement representation is

(a) -2n
(b) -2n-1
(c) -2n + 1
(d) -2(n-1) Answer:

15. How many flip flops would be required to implement a decade counter?

(a) 10
(b) 5
(c) 4
(d) 3 Answer:

NCG Written Test – May’07 4/17

16. The circuit in the figure below does not make efficient use of logic gates. Find a different
circuit having the same transfer function but using fewer gates.

A
B
C
B
O

Answer:

17. A ripple counter is to operate at a maximum frequency of 10MHz. If the propagation delay
time of each flip-flop in the counter is 10ns and the strobing time is 50ns, how many stages
can the counter have?

Answer:

18. Mention the logic performed by the following circuits

Vcc

OUT

Answer:

NCG Written Test – May’07 5/17

19. Mention the logic performed by the following circuit

Vcc

OUT

Answer:

20. What is metastabilty?

Answer:

21. What are the main factors that determine the power consumption of a design?

Answer:

22. What is PLL? What do they do?

Answer:

NCG Written Test – May’07 6/17

23. How is testing different from verification?

Answer:

24. What are the main programming technologies for FPGAs?

Answer:

25. The following “single error detecting and correcting” and “double error detecting”
hamming coded word has been received:

P1 P2 I3 P4 I5 I6 I7 P8
0 1 0 1 0 1 0 1

(a) The information has been correctly received

(b) There is single error and the error is in bit position P1
(c) There is single error in bit position P4
(d) There is double error in the message which cannot be identified

Answer:
26. Example of a zero – address machine is

(a) Microprocessor
(b) Stack machine
(c) Systolic array
(d) Vector processor Answer:

27. What is the value (in decimal) of the 8 bit 2’s complement binary number 10101001

(a) -87
(b) -41
(c) 169
(d) None of the above Answer:

28. Guard bits are used for:

(a) To guard against failures in data transmission

(b) To protect the system from overflow
(c) Additional bits used in arithmetic unit to preserve the maximum precision of
floating point numbers
(d) None if the above Answer:

NCG Written Test – May’07 7/17

29. Microprogramming refers to

(a) A higher level computer language

(b) Technique of designing a control unit of a computer
(c) Technique of designing an arithmetic unit of a computer
(d) Input – Output drivers of a computer system
Answer:
30. Direct Memory Acess (DMA) refers to

(a) CPU access main memory directly

(b) Peripheral access main memory directly
(c) CPU access peripheral directly
(d) Peripheral access CPU directly Answer:

31. Memory mapped I/O refers to

(a) Main memory is addressed as a part of I/O

(b) I/O is addressed as a part of main memory
(c) I/O is accessed through specific I/O instruction
(d) Memory is accessed through specific I/O instruction Answer:
32. For a disc read/write operation, the preferred I/O mode is

(a) DMA
(b) Interrupt
(c) Programmed I/O
(d) Any one of the above Answer:

33. A good example of a standard parallel asynchronous bus is

(a) USB
(b) RS 232C
(c) Centronix
(d) None of the above Answer:

34. In the memory hierarchy in a computing system, the L1 cache is

(a) The fastest memory and is integrated with the processor

(b) The slowest memory and is located on board
(c) The fastest memory and is located on board
(d) The slowest memory and is integrated with the processor

Answer:

35. In the 80x86 architecture NMI is used when

(a) An attempt to divide by zero is made

(b) An interrupt is to be generated at the end of each instruction
(c) When processor faces a sudden power failure
(d) Processor gets in to NOP mode
Answer:

NCG Written Test – May’07 8/17

36. Counter that counts the sequence (0,0,1,1,2,2,3,3) should have a minimum of

(a) One flipflop

(b) Two flipflops
(c) Three flipflops
(d) None of the above Answer:

37. A circuit takes an n-bit number X and another input "A". The output "O" is 2*X if A is 0; and,
2*X + 1 if A is 1. A circuit realizing the above functionality needs a minimum of

(a) 0 gates
(b) 2 gates
(c) 4 gates
(d) 16 gates Answer:

38. The set {AND, NOT} is

(a) Not a functionally complete set

(b) A minimum functionally complete set
(c) A minimal functionally complete set
(d) A maximal functionally complete set Answer:

39. The number of n-input boolean functions with distinct truth tables are

(a) 2^n
(b) 2^(2^n)
(c) 2^(2^(2^n))
(d) 2^(2^(2^(2^n)))
Answer:
Note: p^q stands for p raised to the power of q

40. A Translation Look Aside Buffer is a

(a) Normal Random Access Memory

(b) Set Associative Memory
(c) Content Addressable Memory
(d) None of the above Answer:

41. Find which one of the following is least related to the other three

(a) Write back policy

(b) Write through Policy
(c) Locality of reference
(d) Prefetching Answer:

NCG Written Test – May’07 9/17

42. What do the following two pieces of codes generate?

Case 1: Case 2:

process (somesignal) process (somesignal)

begin begin

if (somesignal = “00”) then if (somesignal = “00”) then

data_out <= data_in; data_out <= data_in;
end if; else
data_out <= ‘0’;
end process; end if;

end process;

Answer: Answer:

43. What is `event? What do the two `event functions return in the following code assuming at
all the five lines of code are executed?

wait on s;
s`event;
s <= s;
wait for 0 ns;
s`event;

Answer:

NCG Written Test – May’07 10/17

44. What happens if the boolean expression in the following code is false?

P: process
begin

if <boolean expression> then

wait for 1 ns;
end if;

end process P;

Answer:

45. What do the wait statement in the following process do?

P: process
begin
wait;
end process P;

Answer:

46. In VHDL delay statements are

(a) Synthesized using cascade of inverters

(b) Synthesized using RC delay circuits
(c) Synthesized using D Flip Flops
(d) Not synthesized at all Answer:

47. In VHDL

(a) Both variables and signals are updated at the end of a process
(b) Both variables and signals are updated immediately at the time of assignment
(c) Variables are updated immediately at the time of assignment and signals are
updated at the end of a process
(d) Signals are updated immediately at the time of assignment and variables are
updated at the end of a process
Answer:

NCG Written Test – May’07 11/17

48. A configuration declaration describes the binding of entity interfaces (and architectures)
with

(a) Component instances

(b) Component declaration
(c) Simulation models
(d) Internal signals Answer:

49. Generate statement is a

(a) Concurrent statement

(b) Sequential statement
(c) Both concurrent and sequential
(d) Cannot classify Answer:

50. Two pieces of verilog code is presented below. What will be the logic synthesized by them?

module pipe1 (q3, d, clk); module pipe2 (q3, d, clk);

output q3; output q3;
input d; input d;
input clk; input clk;
reg q3, q2, q1; reg q3, q2, q1;

always @(posedge clk) always @(posedge clk)

begin begin
q1 = d; q1 <= d;
q2 = q1; q2 <= q1;
q3 = q2; q3 <= q2;
end end

endmodule endmodule

Answer: Answer:

NCG Written Test – May’07 12/17

51. Explain the logic implemented by the verilog code given below:

module m16(ctr, clk, rst); Answer:

input clk;
input rst;
output [3:0] ctr;
reg [3:0] ctr;

always @(posedge clk or negedge rst)

begin
if (~rst)
ctr <= 4’b0;
else
ctr <= ctr + 1;
end

endmodule

52. The or-reduction approach will assign '1' to the output signal if at least one element of the
input vector is

(a) ‘X’
(b) ‘1’
(c) ‘0’
(d) ‘Z’ Answer:

53. Which of the following transition would return true for the condition clk'event and clk = '1'

(a) ‘0’ to ‘1’

(b) ‘H’ to ‘1’
(c) ‘X’ to ‘1’
(d) ‘0’ to ‘H’ Answer:
54. Sensitivity list is used for

(a) Control execution

(b) Assign value to registers
(c) Bypass registers
(d) None of the above Answer:

NCG Written Test – May’07 13/17

55. In the following Verilog code the sensitivity list is

always @( ---------- )
begin
Temp = C;
B = Temp + A + D;
end

(a) (Temp or A or D)
(b) (Temp or A or C or D)
(c) (Temp or A or B or C or D)
(d) None of the above Answer:

56. Refer the verilog code below:

always @(posedge clk or posedge A)

begin
if (clk)
B = 5;
else
B = 7;
end

This code is equivalent to a circuit which has a flipflop F

(a) With "A" as the clock input to F

(b) With "clk" as the clock input to F
(c) With "B" as the clock input to F
(d) With "A" AND "clk" as the clock input to F Answer:

57. In the following verilog code, the variable "p" shall be initialized to "0" after

reg [2:0] X;
integer k,p;

initial
begin
for (X=0; X <= 8; X = X + 1)
#2 k = k + 1;
#3 p = 0;
end

(a) 16 time units

(b) 17 time units
(c) 19 time units
(d) Shall never be initialized Answer:

NCG Written Test – May’07 14/17

58. One of the following scheduling algorithms is a preemptive scheduling algorithm

(a) First Come First Served

(b) Shortest Job First (Shortest Process Next)
(c) Round Robin
(d) Shortest Time to Complete Answer:

59. What are the three regions in the conduction characteristics of a MOS transistor?

Answer:

60. What is threshold voltage of a MOS transistor?

Answer:

61. In the figure below, Vi = 5V initially and the transistor is in saturation. The total stored
base charge is 1nC. At t = 0, Vi drops abruptly to 0V. The capacitor C is included so that the
base charge can be removed abruptly.

+ Rc
5 KΩ

Vi
Vcc

i. Calculate the minimum value of C required to allow removal of all base charge

Answer:

NCG Written Test – May’07 15/17

 ii. With what time constant, the transistor returns to its stable state due to the change in
the input?

Answer:

62. What is the memory storage required for this piece of C code (The size of integer is 4
bytes)

char c; Answer:
int i;
char *cp;
int *ip;

63. What is the relationship called between a class and its public parent class?

(a) "...is a..."

(b) "...has a..."
(c) "...is implemented as a..."
(d) "...uses a..."
(e) "...becomes a..." Answer:

64. Which is the correct syntax if we wish class D to publicly inherit from class B?

(a) class D: public: B {};

(b) class D: public B {};
(c) class D public: B {};
(d) class B: public D {};
(e) class B public: D {}; Answer:

65. What is the accessibility of a protected: member of a base class which is inherited
privately?

(a) Private:, because the private inheritance makes everything from the base class
private in the derived class
(b) Protected:, because it wasn't public in the base class, it doesn't become private in
the derived class
(c) Public:, because accessibilities add: private: + private: = protected:, protected: +
private: = public:, etc.
(d) Inaccessible. Private inheritance makes all non-public: members of the base class
inaccessible in the derived class
(e) None. It's a compile-time error to privately inherit a protected: member

Answer:

NCG Written Test – May’07 16/17

66. If a derived-class object is created and later destroyed what is the order of the constructor
and destructor calls on the object

(a) Base(), Derived(), ... , ~Base(), ~Derived()

(b) Derived(), Base(), ... , ~Derived(), ~Base()
(c) Base(), Derived(), ... , ~Derived(), ~Base()
(d) Derived(), Base(), ... , ~Base(), ~Derived()
(e) Derived(), ... , ~Derived() Answer:

67. If the pointer p is a pointer to a base class B, but actually points to an object of a derived
class D, which member function gets called when the call p->Print() is executed?

(a) B::Print()
(b) D::Print()
(c) B::Print() if B::Print() is not virtual, D::Print() if B::Print() is virtual
(d) D::Print() if B::Print() is not virtual, B::Print() if B::Print() is virtual
(e) Neither. The compiler flags it as an ambiguous case

Answer:

68. In C++, exceptions will only be caught when they are thrown by code

(a) which is physically located in a try block

(b) which has been called from a try block
(c) which is physically located in a catch block
(d) which has been called from a catch block
(e) which has not yet executed Answer:

69. If a try block has two or more associated catch blocks, which of them will be triggered by
an exception?

(a) The first one whose catch parameter type matches that of the exception
(b) The last one whose catch parameter type matches that of the exception
(c) The one whose catch parameter type most closely matches that of the exception
(d) Every one whose catch parameter type matches that of the exception.
(e) The only one whose catch parameter type matches that of the exception. If two or
more catch blocks would match, the compiler flags an ambiguity

Answer:
70. Which of the following declares a pointer to a function g, which takes two ints and returns
nothing?

(a) (*g)(int*2);
(b) (*g)(int,int);
(c) void (*g)(int,int);
(d) (*g)(int,int) = void;
(e) *(void g(int,int)); Answer:

END OF THE PAPER

NCG Written Test – May’07 17/17