IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 7.
JULY 1992
Special Brief Papers
Class-AB High-Swing CMOS Power Amplifier
F . Mistlberger and R. Koch
Abstract-For power amplifiers there is a need to combine
small area and low quiescent power consumption with large
peak currents and high output voltage swing. For a single 5-V
supply, drain-coupled near class-A output stages are the best
solution to this. These stages, however, suffer from large quies-
cent current variations and/or crossover distortion. A power
amplifier for a loudspeaker and, in a smaller version, for the
earpiece of a telephone are presented, where new solutions have
been implemented to solve these problems. The amplifier has
1.2-mA quiescent current, 64-mA peak current, and >60 dB
WTHD with 3.2-V output swing into a 2 5 4 load.
I. INTRODUCTION
D RIVEN by the requirement to reduce costs and to
achieve a maximum amount of flexibility, it is nec-
essary to integrate power amplifiers in telecom CMOS
chips. These amplifiers often have to fulfill contradictory
requirements like low quiescent current for minimum
power consumption, large signal currents, high output
swing, and low distortion. In the following pages a power
amplifier for a loudspeaker and the earpiece of a telephone
subset, integrated in the codec chip ARCOFI-SP (Audio
Ringing Codec Filter featuring Speakerphone Function),
are presented. The ARCOFI-SP is part of a subscriber
telephone chip set. The analog section of the receive path
(Fig. 1) comprises a low-noise (105-dB SNR) program-
mable gain microphone amplifier with a maximum gain
of 30 dB followed by a 16-b second-order sigma-delta
A/D converter. The analog section of the transmit path
consists of two 16-b second-order sigma-delta D/A con-
verters, one driving a pair of handset amplifiers for 200-Q
differential load and the other one a pair of loudspeaker
amplifiers for 5 0 4 differential load. The loudspeaker am-
plifier is described below. A digital signal processor cal-
culates the filter functions and handles frequency and tone
generation.
The target specifications for the power amplifier are
given in Table 1. The moderate requirements for the signal-
to-noise ratio allowed optimization of current and area
consumption at the cost of increased harmonic distortion.
Manuscript received December 9, 1991; revised March 17, 1992.
The authors are with Siemens AG, W-8000 Munich 80, Germany.
IEEE Log Number 9200845.
0018-92001’92$03.000 1992 IEEE
1089
11. PSEUDO-SOURCE-FOLLOWER OUTPUT
The maximum possible output voltage swing of CMOS
operational amplifiers is achieved with drain-coupled
complementary output transistors. However, simple
structures of this type suffer from the additional pole in-
troduced in this stage and from load-dependent gain of the
output stage. Source-follower stages, on the other hand,
have insufficient voltage swing. One structure frequently
used [3], [4] to overcome this problem is the pseudo
source follower (PSF) comprising a complementary drain-
connected output pair and one so-called error amplifier
per transistor (Fig. 2 ) . The complete structure operates in
unity-gain configuration. The error amplifiers are able to
drive the gates of the output transistors with a large dy-
namic voltage swing so these can be reduced in area. For
moderate distortion requirements the output transistors can
even be driven into the triode region. The major drawback
of the PSF in its basic form is the sensitivity of the quies-
cent current and consequently of the standby power con-
sumption to the offset voltage mismatch of the two error
amplifiers. The quiescent current varies proportionally to
the product of offset voltage mismatch and gain of the
PSF stage. Taking into account that the offset voltages are
in the range of a few millivolts and using a small-signal
model, the quiescent current variation calculates to
I=g; VGS for one output transistor
VGS = U V,, for one output transistor
I= U g, 1/2 V,, since V,, averages
with both branches assumed to have equal values of open-
loop gain of each error amplifier ( U ) , transconductance of
each output transistor (g,), gate-to-source voltage of each
output transistor (V,,), and offset voltage difference of the
error amplifiers (V,, ) .
To keep the quiescent current variation reasonably low,
only an open-loop gain of around 20 dB or less is allowed.
Therefore, a high-gain preamplifier stage is necessary to
get enough loop gain for S/THD, PSR, etc. requirements.
A common extension of the PSF approach adds an ad-
ditional complementary source-follower (SF) stage with
relatively small transistor size and current consumption
1090 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 21, NO. I, JULY 1992

XlNP
XlNN

MIP
MIN

' FHM

LSP
LSN

D-- HOP
HON

1 VREF +1wnF 1 DCUCLK RS SP2

FSC SPl
1
VSSP VSSA VSSD
Fig. 1. ARCOFI-SP block diagram. AMI: microphone amplifier; ALS: loudspeaker amplifier; AHO: handset earpiece ampli-
fier.

TABLE I Preamp Preamp din control Pseudo source-follower

POWERAMPLIFIER
PERFORMANCE
DATA output stages stage source
follower

Specification Measured

Supply voltage 5V+5% 5 v

Diff voltage swing 32VPP 4VPP
Peak current 64 mA 80 mA
Power into load 102 mW 160mW
Load 25 0 25 0 OUT
S/N +THD 55 dBm 70 dBm
Quiescent power dissipation 20 mW 6 mW
Signal frequency range 34kHz 34kHz
Slew rate 15V/p
Area 1 mm2
Technology 2-pm CMOS double metal,
double polysilicon

Fig. 3 . Simplified power amplifier schematic.

Preamp Preamp Pseudo-source-follower

output stages SOYrCe

However, a new problem arises with this type of cir-

Fig. 2. Pseudo source follower plus standard source follower.
to the output (Fig. 2). For small output voltages the PSF
stage is turned off, e.g., by an intentionally built-in offset
voltage, and only the standard SF is active. By this means
a quiescent current of zero is possible for the large PSF
output transistors and the problem of variation due to off-
set mismatch is solved. For larger output voltages the PSF
output transistors take over.
cuit. To minimize takeover distortion the two output
stages have to track. This can be achieved when the two
preamplifier outputs are connected, so that the SF and PSF
are driven by the same node [ 5 ] . The voltage swing of the
SF-related output (Ml-M4), however, is limited by the
number of stacked transistors. Since both preamp outputs
are connected, the distortion level of the output driving
the PSF ( M 5 , M 6 ) starts to increase as soon as the
SF-related output is driven into triode region and the out-
put swing of the PSF output is then limited.
A better solution can be achieved when SF- and PSF-
related preamp outputs are not directly coupled. It is,
however, necessary to guarantee tracking of both outputs.
By implementation of an additional amplifier as shown in
Fig. 3 , tracking of the low-swing SF driving output to the
high-swing PSF driving output of the preamplifier can be
achieved. The functional principle is similar to that often
used in single-ended-to-differential conversion. The ad-
ditional amplifier-in our case a differential stage-mon-
itors both preamp outputs and controls the SF-related out-
 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 7, JULY 1992 1091

put by means of the additional current source (M11). The

size of transistor M4 has to be reduced accordingly. For
low and medium output voltages, the SF output tracks the
PSF output voltage with small error. For large output
swings, transistor M1 or M4, depending on the sign, is
pushed into the triode region and causes the correspond-
ing SF output transistor to be turned off. Then only the
PSF output is active.

111. ERRORAMPLIFIERS
An often-used topology for the error amplifiers is a
standard differential stage with current mirror load as
shown in Fig. 4 together with the corresponding n-channel
output transistor. For the upper branch of the output the L - - - - - - _ - - . - - - - - - -

same structure is used with n and p transistors exchanged. Fig. 4. Standard error amplifier.
The maximum voltage swing on the gate of the output
transistor of the structure shown can be approximately de- ~ . . . . . . . . .. . . . . . . . . . . ,

rived as follows: 1 : I
VGSM10 - VGSMl - vD\atMI
with
VGSMI = VTMI+ I/GSeffMI

and
vGSeffM1 - VDsatM1

we get
VGSMIO= Vin

With V,,, = Vi, and the condition V,,,

- VTM,.
-
VDsatMI0we get
the maximum voltage swing on the gate of M10, which
. _ _ . _ _ . . . . . . . _ _ _ _ _ _ _ _ _ _
1
Fig. 5. Improved error amplifier for NMOS output transistor.
1 , l

evidently occurs for the minimum value of V,,,, to be

VGSrnax = VDsatM1O - VTMl - v. where
. For low values of Vi, a large VGSM10is needed but only a I/DsatM5 - vGSeffM5
low value is possible. The limited common-mode range
of the error amplifier versus V,, also limits the output volt- and
age swing of the whole amplifier. VGSeffM5 = VDD - - VGSM7 - V G S M 2 .
An improved version of an error amplifier is shown in
Fig. 5 . The additional current mirror stage M5,M 6 in- Assuming VGSM7and VGsM2equal in value (but opposite
troduces the phase inversion needed to tie the gate of out- in sign) we get
put transistor M10 to the noninverting output of the dif- VDtatM5 = VDD -
ferential stage. Now the buffer output voltage and the
differential-stage output voltage have the same sign and which shows that VDsatM5 can nearly reach the supply
move more or less in parallel. With the differential stage voltage. To ensure a high gate voltage swing for M10,
of Fig. 4, however, the negative output swing would be however, VDsatM5 should be smaller than V / 2 leaving
DD I
limited to about one threshold voltage above ground. With more than vDD/2 for VGSMIO,e.g., VDsatM5 = 71/00 gives
the addition of the source followers the common-mode VGSM,, = VDD 2/3 - 3.3 V
range of the differential stage is extended to ground. The
asymmetrical loads in the differential stage of Fig. 5 de- which is about twice the value achieved with the standard
liver the built-in offset voltage needed to ensure zero configuration.
quiescent current in the output transistor M10.
The maximum gate voltage on the gate of the output IV. MEASURED RESULTS
transistor of M10 now calculates to: A schematic of the complete power amplifier is shown
in Fig. 6. The amplifier is fabricated in a 2-pm double-
VGSM,O = VGSM6
polysilicon, double-metal-layer process. Fig. 7 is a pho-
VGSM6 = VDD - VDsat M 5 tomicrograph of two amplifiers in bridge configuration.
 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 21, NO. 7 . JULY 1992

3 ,

out

’ OTA ’ PSF ’ ’ SF ’ Erroramp ’ Erroramp ’

PSF Output , S F Output
Bias ’ Preamp ’ drive ’ s , = ~ e d r l v y for PMOS ’ tor NMOS ’

Fig. 6. Schematic of the complete power amplifier.

8.0 1.6 2.0 3.0 4.0 5.6 6.0 7.8 9.0 9.6 18.8
F r e q u e n z CkHzl
Fig. 8. Output spectrum for 7.4-V, output signal at 1 kHz into 50-n load.
The amplifier is in the bridge configuration ( V = 4.5 dB).
Fig. 7. Photomicrograph of two power amplifiers in bridge configuration.
ACKNOWLEDGMENT
Low-resistive connections via double bonding must be The authors wish to thank E. Engelhardt for the layout
provided for the high currents of up to k64 mA. In the of the amplifier and J. Feldmann for helpful discussions.
complete ARCOFI circuit the power amplifiers have their
own power supplies separated from the other chip sup- REFERENCES
plies. The width of the supply lines is 100 pm maximum. [ l ] J. A. Fisher and R . Koch, “A highly linear buffer amplifier,” IEEE
The measured results summarized in Table I were taken J . Solid-Stare Circuits, vol. SC-22, pp. 330-334, June 1987.
from two amplifiers set up in bridge connection. The dif- [2] L. Tomasini et al., “A low-voltage high-drive differential amplifier
for ISDN applications, ” in Proc. ESSCIRC’88.
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plifier at 1 kHz with an output voltage of 7.4 Vp.p. The [4] K . E. Brehmer and J. B. Wieser, “Large swing CMOS power arnpli-
fier,” IEEE J . Solid-State Circuits, vol. SC-18, pp. 624-629, Dec.
second and third harmonic coefficients are below 75 dB, 1983.
which is far better than specified so that further optimi- [5] K. Nagaraj, “Large-swing CMOS buffer amplifier,” IEEE J . Solid-
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[6] D. M. Monticelli, “A quad CMOS single-supply op amp with rail-to-
sumption is possible. The measured differential PSRR at rail output swing,” IEEEJ. Solid-state Circuits, vol. SC-21, pp. 1026-
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