Automated Synthesis from

HDL models
Leonardo (Mentor Graphics), Design Compiler (Synopsys)
ASIC Design Flow
Behavioral
Verify
Model
Function
VHDL/Verilog
Synthesis

DFT/BIST Gate-Level Verify

& ATPG Netlist Function

Test vectors Full-custom IC

Transistor-Level Verify Function

Standard Cell IC Netlist & Timing
& FPGA/CPLD

Physical
DRC & LVS Verify
Layout
Verification Timing
Map/Place/Route

IC Mask Data/FPGA Configuration File

Automated synthesis
HDL Behavioral/RTL Models

Technology
Synthesis
Libraries

FPGA Leonardo Spectrum, Design

Synopsys Design Compiler Constraints
ASIC

Leonardo:
Technology-
Level 1 – FPGA
Specific
Level 2 – FPGA + Timing
Netlist
Level 3 – FPGA + ASIC
or ASIC only
VHDL, Verilog, SDF,
EDIF, XNF
Leonardo – ASIC synthesis flow
Synthesis design flow
Leonardo synthesis procedure
1. Invoke leonardo
2. Select & load a technology library (ASIC or FPGA)
 ASIC > ADK > TSMC 0.35 micron
3. Read input VHDL/Verilog file(s): count4.vhd
4. Enter any constraints (clock freq, delays, etc.)
5. Optimize for area/delay/effort level
6. Write output file(s)
 count4_0.vhd - VHDL netlist
 count4.v - Verilog netlist (for IC layout)
 count4.sdf - Standard delay format file (for timing)
 count4.edf - EDIF netlist (for Xilinx/Altera FPGA)
Synthesis example
 Load technology library:
tsmc035 (ASIC), or Xilinx Spartan2 (FPGA)
 Load design file: modulo7.vhd
 Specify constraints: clock freq, delays, etc.
 Optimization: effort, performance vs. area
 Write synthesized netlist output(s):
 modulo7_0.vhd :VHDL netlist for ModelSim & DFT
 modulo7.v :Verilog netlist for import into DA-IC
 modulo7.sdf : For ModelSim to study timing
 modulo7.edf : EDIF netlist for 3rd party tools
 modulo7.xnf : Xilinx netlist for Xilinx ISE
Behavioral model to be synthesized
-- modulo-7 counter with asynchronous reset and synchronous load/count
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity modulo7 is
port( count, load, reset, clk: in std_logic;
I: in unsigned(2 downto 0); -- “unsigned” form of std_logic_vector
Q: out unsigned(2 downto 0)); -- defined in IEEE “numeric_std” package
end modulo7;
architecture Behave of modulo7 is
signal Q_s: unsigned(2 downto 0);
begin
process (reset,clk) begin
if (reset='0') then Q_s <= "000"; -- async reset
elsif (clk'event and (clk='1')) then
if (count = '1') and (Q_s = "110") then Q_s <= "000"; -- count rolls over
elsif (count='1') then Q_s <= Q_s + 1; -- increment count
elsif (load='1') then Q_s <= I; -- synchronous load
end if;
end if;
end process;
Q<=Q_s; -- drive the outputs
end;
Synthesized netlist (1)
-- Definition of modulo7
-- Thu Sep 21 10:48:09 2006
-- LeonardoSpectrum Level 3, 2005a.82
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity modulo7 is
port (
count : IN std_logic ;
load : IN std_logic ;
reset : IN std_logic ;
clk : IN std_logic ;
I : IN std_logic_vector (2 DOWNTO 0) ;
Q : OUT std_logic_vector (2 DOWNTO 0)) ;
end modulo7 ;
Synthesized netlist (2)
architecture Behave of modulo7 is
signal Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, NOT_reset, nx4, nx14, nx22,
nx48, nx60, nx169, nx179, nx189, nx202, nx204, nx208, nx212, nx214,
nx218, nx225, nx228, nx230: std_logic ;
begin
Q(2) <= Q_2_EXMPLR ;
Q(1) <= Q_1_EXMPLR ;
Q(0) <= Q_0_EXMPLR ;
ix170 : mux21_ni port map ( Y=>nx169, A0=>nx14, A1=>Q_0_EXMPLR, S0=>nx225);
ix15 : oai22 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>nx202, B0=>nx230,
B1=>count);
ix203 : nand02 port map ( Y=>nx202, A0=>count, A1=>nx204);
ix205 : nand04 port map ( Y=>nx204, A0=>count, A1=>Q_2_EXMPLR,
A2=>Q_1_EXMPLR, A3=>nx228);
ix180 : oai32 port map ( Y=>nx179, A0=>nx208, A1=>count, A2=>load,
B0=>nx212, B1=>nx225);
Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>nx208, D=>nx179,
CLK=>clk, R=>NOT_reset);
 Synthesized netlist (3)
ix211 : inv01 port map ( Y=>NOT_reset, A=>reset);
ix213 : aoi22 port map ( Y=>nx212, A0=>I(2), A1=>nx214, B0=>nx22, B1=>nx4 );
ix216 : inv01 port map ( Y=>nx214, A=>count);
ix219 : nand02 port map ( Y=>nx218, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR);
Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx189,
CLK=>clk, R=>NOT_reset);
ix190 : mux21_ni port map ( Y=>nx189, A0=>nx60, A1=>Q_1_EXMPLR, S0=>nx225);
ix61 : ao32 port map ( Y=>nx60, A0=>nx48, A1=>nx218, A2=>nx4, B0=>I(1),
B1=>nx214);
ix49 : or02 port map ( Y=>nx48, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);
ix226 : nor02_2x port map ( Y=>nx225, A0=>count, A1=>load);
Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>nx228, D=>nx169,
CLK=>clk, R=>NOT_reset);
ix231 : inv01 port map ( Y=>nx230, A=>I(0));
ix5 : inv01 port map ( Y=>nx4, A=>nx202);
ix23 : xor2 port map ( Y=>nx22, A0=>nx208, A1=>nx218);
end Behave ;
Synthesis steps
1. Load technology library into database
2. Read HDL models into database
3. Get design constraints (timing, area)
4. Analyze design
5. Elaborate design
6. Compile/optimize design
 Repeat as necessary to meet constraints
7. Generate technology-specific netlist(s)
8. Generate simulation timing data (SDF file)
9. Generate reports (cells, area, timing)
Leonardo
Main
Window
Leonardo
Quick Setup Tab
Command
Technology Window

HDL Files

Target Clock Freq

Optimization Effort

Output File
Leonardo commands/scripts
 Enter “commands” at the command prompt, or read from
a Tcl script file.
 A “variable” specifies a global constraint, directive, etc.
 Tcl “set” and “unset” commands change variables
set voltage 3.3
 An “attribute” is information attached to an object
(owner of the attribute) in the memory design database.
 Allows user to fine-tune the process at the object level.
 Set with Tcl “set_attribute” command (also “unset_attribute)
 An attribute has: owner, name, value
 Example:
set_attribute –net n1 –name max_fanout_load –value 10
Technology library (ASIC)
 Load synthesis library for target technology into memory
 Command example: load_library tsmc025_typ
 Searches for $EXEMPLAR/lib/tsmc025_typ.syn
 Technology “variables” affecting delay calculations (“delay
derating factors”)
 Use tech library defaults if variables not set
 set voltage 2.5 (volts)
 set temp 40 (degrees celcius/centigrade)
 set process 1 (process variation # – if available)
 set max_fanout_load 5
 Global limit on max inputs driven by one output
 Override with max_fanout_load attribute on a net (prev. slide)
 Leonardo splits nets or adds buffers as needed (but buffers add delay)
Technology Tab
(ASIC)

Operating
Choose ASIC library temp/voltage
for delay
calculations
FPGA options include
device family, part,
speed grade and
pin selection

Advanced settings:
Select max fanout
 Technology
Tab (FPGA)

Specify:
part,
speed grade,
wire load,
use of IOB registers
Loading a design into the database
 Input VHDL/ Verilog source file(s) to memory database
 Analyze – syntax check and build database
 check dependencies & resolve generics/parameters
 Elaborate – synthesize into generic gates and black boxes
 technology-independent gates
 operators (arithmetic, relational, etc.) recognized and
implemented with “black boxes” (no logic in them yet)

 Read command does analyze + elaborate + pre-optimize

Analyze Command
 analyze {f1.vhd src/f2.vhd “top file.vhd”}
 Read and analyze into default memory database library “work”
 List VHDL files in {} in “bottom up” order – top level last
 Use quotes if embedded spaces in file name: “top file.vhd”
 Include directory information if necessary: src/f2.vhd
 Analyze command switches:
 -format vhdl (or verilog) [default VHDL if file ext = .vhd/.vhdl or
Verilog if file ext = .v/.verilog]
 -work lib_name [lib where design to be stored (default = “work”.)
Different libraries might be used for comparing designs]
 Examples:
 analyze {src/f1.vhd src/f2.vhd}
 analyze {src/f1.vhd src/f2.vhd} –work lib_version1
Elaborate Command
 “Elaborate” a design previously loaded into the memory
database
 elaborate divider [“divider” = VHDL entity/Verilog module]
 Switches
 -single_level [only do top level – for bottom-up design]
 -architecture a1 [if other than most recently analyzed]
 -work lib_name [if name other than work]
 -generics { size=9 use_this=TRUE initval=“10011” }
 List format is { generic=value generic=value …. }
 -parameters [format same as generics]
Read command
 Performs both analyze and elaborate steps
 read {f1.vhd src/f2.vhd “top file.vhd”}
 Use switches from analyze and elaborate commands, plus:
 -dont_elaborate {f1.vhd} – do analysis but not elaborate

 Input Flow Tab can be used to run read/analyze/elaborate

 Uncheck “Run Elaborate” box for analyze only
 Uncheck “Run Pre-Optimization” to skip that step for now
 Select other analyze/elaborate options via the “Power Tabs”
 Input Flow Tab

HDL file list:

List VHDL files from
bottom to top levels of
hierarchy.

FSM encoding

Share resources (adders,

etc.) to do multiple op’s

Run Elaborate step

after Analysis.

Run Pre-Optimize
step after Elaborate “Power Tabs” below here
Elaborate & VHDL Options Power Tabs
Elaborate: Select:
top-level design name,
architecture,
work library,
generics,
top-level only

VHDL Options:
Select VHDL 87 instead of 93

Other power tabs for other formats

(Verilog, SDL, etc.)
Design Constraints
 Area constraints
 Timing constraints
 Simple: specify target clock frequency
 Advanced: specify globally or on specific blocks
 Clock: period/frequency, pulse width, duty cycle
 Input: arrival time, transition times, driver strength
 Output: required time, transition times
Design Constraints
 Area constraints
 Timing constraints (clocks, delays, inputs, outputs)
 Simple: specify target clock frequency
 Advanced: specify globally or on specific blocks
 Four delay variables can be specified:
 Input pin to output pin (through combinational logic)
 Input pin to register & register to output pin
 Register (from time it is clocked) to register (to meet setup time)
Clock-related constraints
 clock_cycle <clock_period> <primary_input_port>
 pulse_width <clock_pulse_width> <primary_input_port>
 clock_offset <clock_offset> <primary_input_port>
Clock constraint examples
Global clock and delay
constraints

- Clock fequency/period
- Max delays

These apply to the entire

design, except for objects
for which attributes have
been defined that specify
other clock values.
Individual clock
net attributes

Clock name(s)

These override the

global clock settings
for the selected clock
signals.
 Input constraints

Arrival time at input pin from previous

circuit, relative to the clock.

D Q
Pin
Clk
Clk

Drive level of circuit driving the pin &

max rise/fall time allowed – used in
delay/loading calculations.
 Output constraints

Time signal from an output pin is

required the next circuit.

Pin D Q

Clk
Clk

Max rise/fall time allowed – used in

delay/loading calculations.
Sequential circuit example (Synopsys)

create_clock -period 20 -waveform {5 15} clka

Required clock periods
create_clock -period 30 -waveform {10 25} clkb
set_input_delay 10.4 -clock clka in1 Arrival at input pin from
set_input_delay 6.4 -clock clkb -add_delay in1 previous clock edge
set_output_delay 1.6 -clock clka -min out1 Setup time of output pin
set_output_delay 4.8 -clock clka -max out1 from next clock edge
Other signal constraints
preserve_signal attribute

Preserve signal during

optimization
(do not eliminate it)
Module constraints
Commands/Attributes:
don’t_touch, noopt
Select modules

Don’t touch: keep module as-is,

including lower levels

No Opt: keep selected module,

but lower levels may be optimized

Select area/delay optimization

and effort level for each module
Write a Constraint File

For subsequent synthesis

and/or for physical place &
route tool.
Pre-optimization step
 Technology-independent logic optimization
 Always done as part of optimize command
 pre_optimize [<design_name>]
[-common_logic] share operators/primitives with
common inputs – used in different clock cycles
[-unused_logic] remove logic that doesn’t affect outputs
[-extract] recognize counters, decoders, RAMs, ROMs
[-xor_comparator_optimize] factor common sub-
expressions from wide XORs/comparators
[-single_level] do top level only (default is all levels)
[-boundary] propagate constants (inputs tied high/low)
from boundary, unused inputs, etc.
Pre-Optimize Power Tab

Select specific design to pre-optimize

Optimization step
 Control optimization via:
 Timing constraints on I/O signals
 Input drive and capacitance and output load
 Definition on clocking schemes
 optimize <design> (default = current design)
 -target <tech> [default is to use loaded library]
 -io_target <tech>
 -single_level [optimize top only – otherwise all levels]
 -effort quick (one pass) | standard (multiple passes) | remap
 -area | -delay | -auto [optimize area, delay or both]
 -pass N | -nopass N [FPGAs- select/omit optization steps]
 -hierarchy preserve | flatten | auto
Optimize Tab

Set variables for both

optimize and
optimize_timing
commands
“Optimize Timing” “Advanced Settings”
Output Tab

Write one or more files:

VHDL netlist
Verilog netlist
SDF (timing)

Select “Technology Cells”

for circuit structure of
cells from the technology
library.