Central Clock Generator (CCG(A)) Siemens

Central Clock Generator (CCG(A))

Contents
1 Functional Description 3
1.1 Introduction 4
1.2 Hardware 6
1.3 Operating Variants 8
1.4 Clock Distribution 10
1.5 Frame and Rack Layout of the CCG(A) 12
2 MML Commands 15
2.1 Interrogation of the CCG 16
2.2 Configuration of the CCG 16
3 Exercise 19
4 Solution 25

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1 Functional Description

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1.1 Introduction
In order to switch and transmit digital information, the sequence of operations must
be synchronous throughout the equipment involved. This requires a clock supply with
a high level of reliability, precision and consistency for all the nodes in the digital
network. In a D900 system or an EWSD system respectively this task is fulfilled by
the central clock generator (CCG).
In view of its vital role, the central clock generator is duplicated. One is always
switched as active and is called the master, while the other one is standby and is
called the slave. This ensures that in the event of a malfunction or failure affecting the
master CCG, the master/slave roles can be switched over immediately and
automatically and that the clock supply to the connected subsystems continues
uninterrupted.
The CCG itself is normally synchronizing to an external reference frequency, e.g. an
atomic clock signal or a 2MHz clock signal taken from an ordinary 2Mbps PCM30
system from a connected network node.

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LTGx SN(B)
To other
nodes

DSU/DLU LTGx

LTGx

External CCG(A)1
reference
frequencies

CDEX1 MB(B)1

To additional
CDEX modules
and external
equipment
CDEX0 CCG(A)0 MB(B)0
(optional)

External
reference
frequencies

Clock signal for IOP:TA

(Real time clock) and CP113x
crossconnected parallel
Interface to IOP:MBs for
safeguarding

Fig. 1 Position of the CCG in the EWSD system

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1.2 Hardware
The Central Clock Generator consists of four module types:

one CCGxxA module with own oscillator and external reference inputs

one CCGB module with own oscillator for distributing the system clock

one CCGD module, only for amplifying and distributing the system clock

up to 10 optional CDEX modules for distributing the system clock to external
equipment if necessary

The "xx" in the CCGxxA module name are variables for the external reference
frequencies. There are four possibilities for each input:

x Possible input frequencies

0 free-running (no external reference, only plesiochronous operating mode)
1 300 kHz and 2048 kHz
2 5 MHz and 10 MHz
3 308 kHz and 1544 kHz

Example: CCG01A means only one reference input for 300kHz and 2048kHz .

The CCG can work in two operating modes:

synchronous operating mode (with at least one external reference signal)

plesiochronous operating mode (no external reference frequency; free-running)

In synchronous operating mode it generates the clock fO1 for the module CCGB with
the on-board, high-quality oscillator and synchronizes it to one of the two possible
external reference frequencies. The clock generated in module CCGB is
synchronized with fO1 as a reference clock in accordance with the selected external
reference clock. The synchronization clock of the module CCGB (SYCLK) is thus
also synchronized to this reference.
The active (master) CCG transfers the SYCLK via the modules CCGB and CCGD to:

the duplicated message buffer (MB(B) 0 and MB(B) 1)

the coordination processor (Real time Clock on IOP:TA in CP113x)

the CCGB module of the standby (slave) CCG to synchronize both CCG

two external master clock distributors (CDEX0 and CDEX1), if required

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The optional CDEX modules can be used to provide a 2048kHz synchronous system
clock to external equipment . Ten modules can be installed with four outputs each.
The modules CDEX0 and CDEX1 only have a connection to the CCG and are called
the masters. They provide a clock signal for the remaining eight modules.

CCG(A)0

fR0 fO1 SYCLK0

CCGxxA0 CCGB0 MB(B)0, MB(B)1
External SYCLK0
reference CP113x
fR3 fO2´ SYCLK0
frequencies CDEX0, CDEX1
SYCLK0
Reserve

SYCLK0

CCGD0 SYCLK0
SYCLK0 MB(B)0, MB(B)1
SYCLK0
Reserve

ACT, Master*

CCG(A)1

fR2 fO1 SYCLK1

CCGxxA1 CCGB1 MB(B)0, MB(B)1
External SYCLK1
reference CP113x
fR1 fO2´ SYCLK1
frequencies CDEX0, CDEX1
SYCLK1
Reserve

SYCLK1

CCGD1 SYCLK1
MB(B)0, MB(B)1
SYCLK1
Reserve

STB, Slave*
*in this example!

Fig. 2 Internal structure of the CCG

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1.3 Operating Variants

Depending on the accuracy required, the following operational variants or modes can
be implemented with the central clock generator (A):

Synchronous operation with external reference frequencies (fR):

The precision of the CCG(A) output clocks depends on the tolerance of the
controlling reference frequency. The tolerance in synchronous networks with
international digital traffic and synchronization of the master nodes by cesium (Cs)
standards is: I∆fRI/fR≤10−11=(CCITT G.811).
There are different possibilities to connect external reference frequencies to the
CCGxxA module. See Fig. 3 for details.

Plesiochronous operation (self-synchronization) without external reference

Frequencies for the master nodes in national synchronous networks (without
international digital traffic): the precision of the CCG(A) output clocks depends on the
tolerance of the oscillator frequency (fO) generated in the master CCG(A). This
tolerance is: I∆fOI/fO≤10−8=.
TIP
In this mode one of the CCG distributes his CCGxxA clock signal to a CCGxxA input
of the other CCG as a "pseudo" external reference! Thus, the second CCG works in
synchronous mode, because he can not distinguish between a real external
reference and a signal from his partner CCG (see DISP CCG).

In plesiochronous operation, the CCG(A)s can, via the reference clock inputs, be
balanced with a rubidium standard on initial start-up or synchronized from time to
time as part of preventive maintenance.

Plesiochronous operation without the CCGxxA module

For island SSS nodes without digital traffic from and to other SSS nodes, whereby
the accuracy of the CCG(A) output clocks is dependent on the tolerance of the
oscillator frequency 2 (fO2), which is generated at the CCGB module of the master
CCG(A): I∆fO2/fO2≤10−5= to 10−6=.

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fR0 fR0
CCG(A)0 CCG(A)0
fR3
Can be used for a start-up or
time to time synchronization
fR2 fR2
CCG(A)1 CCG(A)1
fR1 fR1
CCG(A)0

Four different reference frequencies Three different reference frequencies

CCG(A)1

fR0 fR0
CCG(A)0 CCG(A)0

Plesiochronous operation, no
(continuos) reference frequency

CCG(A)1 CCG(A)1
fR1

Two different reference frequencies One reference frequency

Fig. 3 Operating modes of the CCG

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1.4 Clock Distribution

The clock distribution in the D900 / EWSD system has an hierarchical structure.
Clocks are generated, synchronized and transferred within the D900 / EWSD network
node in several sequential stages.
The hardware units in every level have their own clock generators. This unit-specific
oscillators are synchronized with the input clock coming from the higher level. If the
higher level clock signal fails, the lower level clock generators continue in free-
running mode and therefore the system continues working to a certain extent. Due to
the inferior quality of the clocks generated on lower levels, calls to other network
nodes may not be possible.

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External reference frequency

Level 0 CF pilot
PCM
5/10MHz

CCG(A)

Level 1
8kHz SYCLK
(synchronization clock)

CG/MUX IOP/TA
(2048kHz
to external CDEX
MB(B) CP113x
equipment)

Level 2 8192kHz (CLK, node

clock), 2kHz (FMB,
Frame Mark Bit)

SGCB SGCB SGCB

SSG(B) TSG(B) SN(B)

or
Level 3
8192kHz (CLK'),
2kHz (FMB')

GCG part MUXMA

LTG CCNC

Level 4 2048kHz (LCLK, Line

clock for PCM30), LFS
(Line Frame Signal)

BDCG
SSS node
DSU/DLU

Level 5

Fig. 4 Clock hierarchy levels in the EWSD system

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1.5 Frame and Rack Layout of the CCG(A)

The clock generator normally shares a rack together with the message buffer and the
system panel control (basic rack R:MB/CCG). Other rack types, e.g. racks with LTG
or SN are possible (see maintenance manuals).
The CCG are located in the same frame as the message buffer group 0 for the
switching network halves 0 and 1(F:MB/CCG(B)). They use mounting units MUT02
and MUT03.
The optional CDEX modules belonging to the CCG are located in the frame for the
system panel control (F:SYPC(A)), because the SYP is normally mounted in the
same rack and uses only a small part of the frame.

MB(B)

CCGxxA

DCCCR
CCGB
CCGD
MOLOC Axxx 001 007 013 019 025 031 037 043 049 055 061 067 073 079 085 091 097 103 109 115 121

Frame for MB(B) and CCG(A) F:MB/CCG(B)

SYPC
DCCCL
CDEX0

CDEX3
CDEX4
CDEX5
CDEX6
CDEX7
CDEX8
CDEX9
CDEX1
CDEX2

MOLOC Axxx 001 007 013 019 025 031 037 043 049 055 061 067 073 079 085 091 097 103 109 115 121

Frame for SYPC and CDEX modules F:SYPC(A)

Fig. 5 Frames for the CCG(A)

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Fuses MUT01

F:MB/CCG(B) MUT02

F:MB/CCG(B) MUT03

(Gap) (MUT04)

F:SYPC(A) MUT05

(MUT06)
(Gap)

(Gap) (MUT07)

F:MB/CCG(B) MUT08

CCG-part empty

F:MB/CCG(B) MUT09

Fig. 6 Basic rack for the CCG(A) (R:MB/CCG)

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2 MML Commands

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2.1 Interrogation of the CCG

Interrogating the CCG

STAT CCG ;
DISP CCG ;

2.2 Configuration of the CCG

Configuring the CCG

CONF CCG : CCG= , OST= [ ,SUP= ] ;

TIP
It is not possible to configure a CCG to active directly. Configure the currently active
unit to standby for changing active/standby (master/slave) status. The same applies,
if no unit is active. The system sets the first standby configured unit to active
automatically.

TIP
After the module CCGxxA was pulled out and reinserted or a power failure occurred,
it is not possible to configure the CCG immediately, because the module has to
warm-up. Wait for 35 minutes (plesiochronous mode) or 2 hours (synchronous
mode), then configure it to standby.

TIP
No DIAG command is necessary for the CCG. During configuration from MBL to STB
an integrated diagnose is performed by the system.

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X522/CTYCPZ1V1332/R03/003 00-03-17 18:03:22

3717 CA EWSD2000 3080/00229

STATCCG; EXEC'D

CCG-0 CCG-1
----- -----
STB ACT

END JOB 3717

X522/CTYCPZ1V1332/R03/003 00-03-17 18:03:31

3721 CA EWSD2000 3080/02810

DISPCCG; EXEC'D

STATUS AND ERROR INFORMATION : CCG-0 CCG-1

----------------------------------------------------------

REF. FREQUENCIES AT CCGXXA : PRESENT PRESENT

CCGXXA-MODULE : FAULT-FREE FAULT-FREE
CCGXXA-PROCESSOR : FAULT-FREE FAULT-FREE
CCGB-MODULE : FAULT-FREE FAULT-FREE
CCGB-PROCESSOR : FAULT-FREE FAULT-FREE
INTERFACE CCGXXA/CCGB : FAULT-FREE FAULT-FREE
CCGB MS-STATUS : MASTER SLAVE
CCGB CLOCK DISTRIBUTOR : ENABLED ENABLED

OPERATING STATE : ACT STB

REFERENCE FREQUENCY 0 : GOOD GOOD

REFERENCE FREQUENCY 1 : GOOD GOOD
USED REFERENCE FREQUENCY : 0 0
STATUS FREQUENCY STORAGE : NORMAL NORMAL
SYNCHRONIZATION STATUS : SYNCHRON 4 SYNCHRON 4

END JOB 3721

Fig. 7 Interrogating the CCG

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ACT STB

MBL UNA

NAC

MSC2/D2MMPK1V9502-I21/000 98-10-09 12:29:42

8762 CA SIEMENS0 3077/06611

CONFCCG:CCG=1,OST=STB;

STARTING CONFIGURATION FOR CCG -1 FROM ACT TO STB

END TEXT 8762

MSC2/D2MMPK1V9502-I21/000 98-10-09 12:29:45

8762 CA SIEMENS0 3077/06609

CONFCCG:CCG=1,OST=STB;

END OF CONFIGURATION FOR CCG -1 FROM ACT TO STB

END TEXT 8762

MSC2/D2MMPK1V9502-I21/000 98-10-09 12:29:46

8762 CA SIEMENS0 3076/00007

CONFCCG:CCG=1,OST=STB; EXEC'D

END JOB 8762

Fig. 8 Configuring the CCG

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3 Exercise

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Exercise 1
Title: Questions about the Central Clock Generator
Objectives: Repetition of the Topics in this chapter
Pre-requisite: The student can explain the Central Clock Generator
Task
Please answer the following questions
Query

How is the CCG connected to the CP?

How many external reference frequencies can be connected to the CCG?

Which of the following statements is correct?

The CCG halves work in

Master/Slave mode
ACT/STB mode
Loadsharing mode

What is the meaning of plesiochronous and synchronous operating modes?

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Exercise 2
Title: Standard HW Fault Clearance CCG: Hands On Training
Objectives: The participant is able to
 perform the CCG fault clearance tasks of a network element
manager
Pre-requisite:  Training exchange or Computer Based Simulator is
available
 MMN, CML and ECD
Task

Perform fault clearance for a given example!

Query

List the MMN procedure(s) which have to be performed!

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4 Solution

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Solution 1
Title: Questions about the Central Clock Generator
Objectives: Repetition of the Topics in this chapter
Pre-requisite: The student can explain the Central Clock Generator
Task

Please answer the following questions

Query

How is the CCG connected to the CP?

1) Cross-connected parallel interface to IOP/MBs for operation and maintenance

2) Clock line to IOP:TA for providing the signal for the real time clock

How many external reference frequencies can be connected to the CCG?

Which of the following statements is correct?

The CCG halves work in

Master/Slave mode
ACT/STB mode
Loadsharing mode

What is the meaning of plesiochronous and synchronous operating modes?

Plesiochronous: No external reference frequency (free-running)

Synchronous: Synchronized to an external reference frequency

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