®

CA3086

Data Sheet August 2003 FN483.5

General Purpose NPN Transistor Array Applications

The CA3086 consists of five general-purpose silicon NPN • Power Applications from DC to 120MHz
transistors on a common monolithic substrate. Two of the
• General-Purpose Use in Signal Processing Systems
transistors are internally connected to form a differentially
Operating in the DC to 190MHz Range
connected pair.
• Temperature Compensated Amplifiers
The transistors of the CA3086 are well suited to a wide
variety of applications in low-power systems at frequencies • See Application Note, AN5296 “Application of the CA3018
from DC to 120MHz. They may be used as discrete Integrated-Circuit Transistor Array” for Suggested
Applications
transistors in conventional circuits. However, they also
provide the very significant inherent advantages unique to
Pinout
integrated circuits, such as compactness, ease of physical
CA3086 (PDIP, SOIC)
handling and thermal matching.
TOP VIEW

Ordering Information
1 14
PART NUMBER TEMP. PKG. Q5
(BRAND) RANGE (oC) PACKAGE DWG. # 2 13 SUBSTRATE
Q1
CA3086 -55 to 125 14 Ld PDIP E14.3 3 12
CA3086M96 -55 to 125 14 Ld SOIC Tape M14.15 Q2
4 11
(3086) and Reel
Q4
5 10

6 9
Q3
7 8

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
 CA3086

Absolute Maximum Ratings Thermal Information

The following ratings apply for each transistor in the device: Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W)
Collector-to-Emitter Voltage, VCEO ..................................................... V PDIP Package . . . . . . . . . . . . . . . . . . . 110 N/A
Collector-to-Base Voltage, VCBO ......................................................... V SOIC Package . . . . . . . . . . . . . . . . . . . 130 N/A
Collector-to-Substrate Voltage, VCIO (Note 1) ............................ V Maximum Power Dissipation (Any one transistor) ................. 300mW
Emitter-to-Base Voltage, VEBO ............................................................ V Maximum Junction Temperature (Plastic Package) ................ 150oC
Collector Current, IC ........................................................................ 50mA Maximum Storage Temperature Range ............... . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s)......................... 300oC
Operating Conditions (SOIC - Lead Tips Only)
Temperature Range ............................................ . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. The collector of each transistor in the CA3086 is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. To avoid
undesirable coupling between transistors, the substrate (Terminal 13) should be maintained at either DC or signal (AC) ground. A suitable
bypass capacitor can be used to establish a signal ground.
2. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications TA = 25oC, For Equipment Design

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Collector-to-Base Breakdown Voltage V(BR)CBO lC = 10A, IE = 0 20 60 - V
Collector-to-Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 15 24 - V
Collector-to-Substrate Breakdown Voltage V(BR)ClO IC = 10A, ICI = 0 20 60 - V
Emitter-to-Base Breakdown Voltage V(BR)EBO IE = 10A, IC = 0 5 7 - V
Collector-Cutoff Current (Figure 1) ICBO VCB = 10V, IE = 0, - 0.002 100 nA
Collector-Cutoff Current (Figure 2) ICEO VCE = 10V, IB = 0, - (Figure 2) 5 A
DC Forward-Current Transfer Ratio (Figure 3) hFE VCE = 3V, IC = 1mA 40 100 -

Electrical Specifications TA = 25oC, Typical Values Intended Only for Design Guidance
TYPICAL
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
DC Forward-Current Transfer Ratio hFE VCE = 3V IC = 10mA 100
(Figure 3)
IC = 10A 54
Base-to-Emitter Voltage (Figure 4) VBE VCE = 3V IE = 1 mA 0.715 V
IE = 10mA 0.800 V
VBE Temperature Coefficient (Figure 5) VBE/T VCE = 3V, lC = 1 mA -1.9 mV/oC

Collector-to-Emitter VCE SAT IB = 1mA, IC = 10mA 0.23 V

Saturation Voltage

Noise Figure (Low Frequency) NF f = 1kHz, VCE = 3V, IC = 100A, 3.25 dB

RS = 1k

2
 CA3086

Electrical Specifications TA = 25oC, Typical Values Intended Only for Design Guidance (Continued)

TYPICAL
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS

Low-Frequency, Small-Signal Equivalent- f = 1kHz,VCE = 3V, IC = 1mA

Circuit Characteristics:
Forward Current-Transfer Ratio hFE 100 -
(Figure 6)

Short-Circuit Input Impedance hIE 3.5 k

(Figure 6)
Open-Circuit Output Impedance hOE 15.6 S
(Figure 6)
Open-Circuit Reverse-Voltage hRE 1.8 X 10-4 -
Transfer Ratio (Figure 6)

Admittance Characteristics: f = 1MHz,VCE = 3V, lC = 1mA

Forward Transfer Admittance yFE 31 - j1.5 mS
(Figure 7)
Input Admittance (Figure 8) yIE 0.3 + j0.04 mS
Output Admittance (Figure 9) yOE 0.001 + j0.03 mS
Reverse Transfer Admittance yRE See Figure 10 -
(Figure 10)

Gain-Bandwidth Product (Figure 11) fT VCE = 3V, IC = 3mA 550 MHz

Emitter-to-Base Capacitance CEBO VEB = 3V, IE = 0 0.6 pF
Collector-to-Base Capacitance CCBO VCB = 3V, IC = 0 0.58 pF
Collector-to-Substrate Capacitance CClO VC l = 3V, IC = 0 2.8 pF

Help Data TA = 25oC, Typical Values.

GV
PARAMETER SYMBOL TEST CONDITIONS GC
For basic polarization fBP VCC = SE ICQ = SE hfe -hfeRl´/hie+Rg

hFE = SL hfe/hfe+1 RL/RG+(1+GM

)
For basic polarization VBE VRC = Vcc/2 IE = 1 mA hfe+1 (HFE+1)RL/RG
+hie+(hfe+1)Rl´
RC= Vcc/2Icq
IE = 10mA 0.800 V
VRE=Vcc/10
VBE Temperature Coefficient (Figure 5) VBE/T RE=Vcc/10Icq R1=(Vcc/Vbb)Rb -1.9 mV/oC
R2=(R1 RB)/(R1-RB) RB=10RE
Vbb=VBE+VRE
Collector-to-Emitter VCE SAT IB = 1mA, IC = 10mA 0.23 V
Saturation Voltage
In higth frecuency NF hie=r π=hfe/gm=hfe*26mv/Icq 3.25 dB
gm=Ic/26m ro=1/hoe
FH=1/2π sum(T) T=ReqCeq


3
 CA3086

Typical Performance Curves

102 103
IE = 0 IB = 0
COLLECTOR CUTOFF CURRENT (nA)

COLLECTOR CUTOFF CURRENT (nA)

10 102
VCB = 15V
VCE = 10V
VCB = 10V
1 VCB = 5V 10
VCE = 5V
10-1 1

10-2 10-1

10-3 10-2

10-4 10-3
0 25 50 75 100 125 0 25 50 75 100 125
TEMPERATURE (oC) TEMPERATURE (oC)

FIGURE 1. ICBO vs TEMPERATURE FIGURE 2. ICEO vs TEMPERATURE

4
 CA3086

Typical Performance Curves (Continued)

120 0.8
VCE = 3V VCE = 3V
TA = 25oC TA = 25oC

BASE-TO-EMITTER VOLTAGE (V)

110 hFE
STATIC FORWARD CURRENT
TRANSFER RATIO (hFE)

0.7
100 VBE

90
0.6
80

70
0.5

60

50 0.4
0.01 0.1 1 10 0.01 0.1 1.0 10
EMITTER CURRENT (mA) EMITTER CURRENT (mA)

FIGURE 3. hFE vs IE FIGURE 4. VBE vs IE

100
VCB = 3V VCE = 3V
f = 1kHz
TA = 25oC hFE = 100 hOE
NORMALIZED h PARAMETERS hIE = 3.5k AT
hRE = 1.88 x 10 -4
BASE-TO-EMITTER VOLTAGE (V)

0.9 hIE 1mA

hOE = 15.6S
10
hRE
0.8

0.7

IE = 3mA hFE
1.0
0.6
IE = 1mA
IE = 0.5mA
0.5 hRE
hIE
0.4 0.1
-75 -50 -25 0 25 50 75 100 125 0.01 0.1 1.0 10
TEMPERATURE (oC) COLLECTOR CURRENT (mA)

FIGURE 5. VBE vs TEMPERATURE FIGURE 6. NORMALIZED hFE, hIE, hRE, hOE vs IC

FORWARD TRANSFER CONDUCTANCE (gFE)

6
COMMON EMITTER CIRCUIT, BASE INPUT COMMON EMITTER CIRCUIT, BASE INPUT
40 TA = 25oC, VCE = 3V, IC = 1mA TA = 25oC, VCE = 3V, IC = 1mA
AND SUSCEPTANCE (bFE) (mS)

AND SUSCEPTANCE (bIE) (mS)

5
INPUT CONDUCTANCE (gIE)

30
4
gFE
20
3
bIE
10

2
0
gIE
-10 bFE 1

-20 0
0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

FIGURE 7. yFE vs FREQUENCY FIGURE 8. yIE vs FREQUENCY

5
 CA3086

Typical Performance Curves (Continued)

REVERSE TRANSFER CONDUCTANCE (gRE)

6 COMMON EMITTER CIRCUIT, BASE INPUT COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25oC, VCE = 3V, IC = 1mA TA = 25oC, VCE = 3V, IC = 1mA
AND SUSCEPTANCE (bOE) (mS)

AND SUSCEPTANCE (bRE) (mS)

OUTPUT CONDUCTANCE (gOE)

5 gRE IS SMALL AT FREQUENCIES

LESS THAN 500MHz
0
4
bOE
bRE
-0.5
3

-1.0
2

1 -1.5
gOE

0 -2.0
0.1 1 10 100 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

FIGURE 9. yOE vs FREQUENCY FIGURE 10. yRE vs FREQUENCY

VCE = 3V
TA = 25oC
1000
GAIN BANDWIDTH PRODUCT (MHz)

900
800
700
600
500
400
300
200
100
0
0 1 2 3 4 5 6 7 8 9 10
COLLECTOR CURRENT (mA)

FIGURE 11. fT vs IC

6
 CA3086

Dual-In-Line Plastic Packages (PDIP)

N
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2 A
-C- B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C
L B1 0.045 0.070 1.15 1.77 8
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e
eC C D 0.735 0.775 18.66 19.68 5
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A BS
E 0.300 0.325 7.62 8.25 6
NOTES:
E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.430 - 10.92 7
Publication No. 95.
L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3. N 14 14 9
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpen-
dicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).

7
 CA3086

Small Outline Plastic Packages (SOIC)

N M14.15 (JEDEC MS-012-AB ISSUE C)
INDEX
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
H 0.25(0.010) M BM PACKAGE
AREA
E
INCHES MILLIMETERS
-B-
SYMBOL MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
123
L
A1 0.0040 0.0098 0.10 0.25 -
SEATING PLANE B 0.013 0.020 0.33 0.51 9
-A- C 0.0075 0.0098 0.19 0.25 -
D A h x 45o
D 0.3367 0.3444 8.55 8.75 3
-C- E 0.1497 0.1574 3.80 4.00 4
µ e 0.050 BSC 1.27 BSC -
e A1
C H 0.2284 0.2440 5.80 6.20 -
B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5
0.25(0.010) M C AM BS
L 0.016 0.050 0.40 1.27 6
N 14 14 7
NOTES:
 0o 8o 0o 8o -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95. Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

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