4th Generation Intel® Core™ i7-

4700EQ Processor with Mobile

Intel® QM87 Chipset
Development Kit User Guide

August 2013

Document ID: 524150-1.2

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2 User Guide
Contents
1 Introduction .......................................................................................................5
1.1 Terminology ............................................................................................5

2 Development Kit Features....................................................................................7

2.1 Development Kit Feature Set Summary ......................................................8
2.2 Power Supply Solutions, Usage and Recommendation ................................ 10

3 Development Kit Summary ................................................................................ 11

3.1 Features ............................................................................................... 11
3.2 Connectors, Headers & Jumpers .............................................................. 14
3.2.1 Back Panel Connectors .............................................................. 14
3.2.2 Front Panel Header ................................................................... 15
3.2.3 CPU Straps .............................................................................. 16
3.2.4 Configuration Jumpers/Switches ................................................. 17
3.3 LEDs .................................................................................................... 17

4 Quick Start Guide ............................................................................................. 18

4.1 Required Peripherals .............................................................................. 18
4.2 Instructions to Flash BIOS to SPI ............................................................. 19
4.3 Power Up .............................................................................................. 20

Figures
Figure 1. Dev Kit Block Diagram ...........................................................................7
Figure 2. Pin Out Specification ............................................................................ 10
Figure 3. Development Kit Top View.................................................................... 11
Figure 4. Development Kit Bottom View .............................................................. 13
Figure 5. Dev Kit Back Connector........................................................................ 14
Figure 6. Front Panel Header Pin Out Diagram ...................................................... 15
Figure 7. Dediprog SF600 with Adaptor B ............................................................ 19

Tables
Table 1. Development Kit Feature Set Summary .....................................................8
Table 2. Development Kit Components List .......................................................... 12
Table 3. Back Panel Connectors .......................................................................... 14
Table 4. Front Panel Header Pin Out Description ................................................... 15
Table 5. Configuration Jumper/Switches .............................................................. 17
Table 6. Development Kit LEDs........................................................................... 17

User Guide 3
 Revision History

Document Revision Description Revision Date

Number Number

524150 1.2 Chipset name change August 2013

524150 1.1 Release to EDC July 2013

524150 1.0 Initial Release June 2013

4 User Guide
1 Introduction
This user guide describes the typical hardware set-up procedures, features and use of
the 4th Generation Intel® Core™ i7-4700EQ Processor with Mobile Intel® QM87 Chipset
Development Kit. Read this document in its entirety prior to powering ON the
Development Kit.

The Quick Start section provides quick start procedures for reference. It is
recommended to have both the schematic and Development Kit present as you
proceed through this document.

The Development Kit is a dual channel DDR3 mobility platform. It is designed to

support the 4th Generation Intel® Core™ processor BGA and the Intel® 8 Series
Chipset family chipset.

This document is relevant to the Development Kit only. The references in this
document correlate to reference designators and board properties of the Development
Kit. Socket and connector locations are labeled with a letter-number combination (for
example, the first memory SODIMM connector is located at J7G1). Please refer to the
silkscreen labeling on the Development Kit for socket locations.

1.1 Terminology
Term Description
ACPI Advanced Configuration Power Interface
BGA Ball Grid Array
BIOS Basic Input / Output System
Dev Kit Development Kit
DDR Double Data Rate
DDI Digital Display Interface
DMI Direct Media Interface
eDP Embedded Display Port
ESD Electrostatic Discharge
FCIM Full Clock Integration Mode
FPIO Front Panel Input Output
FSB Front Side Bus
GPIO General Purpose Input Output
®
Intel HD Audio Intel® High Definition Audio
KBC Keyboard Controller
LAN Local Area Network
LED Light Emitting Diode
LPC Low Pin Count
OS Operating System

User Guide 5
 Term Description
PCB Printed Circuit Board
PCH Platform Controller Hub
PCI Peripheral Control Interface
PCI-e* PCI Express
PEG PCI Express Graphics
PLL Phase Lock Loop
RTC Real Time Clock
SATA Serial AT Attachment
SIO Super Input Output
SMC System Management Controller
U-DIMM Unbuffered Dual In-line Memory Module
USB Universal Serial Bus
VGA Video Graphics Array
VR Voltage Regulator
XDP Extended Debug Port

6 User Guide
2 Development Kit Features

Figure 1. Dev Kit Block Diagram

User Guide 7
2.1 Development Kit Feature Set Summary
Table 1. Development Kit Feature Set Summary

Dev Kit Comments

Implementation
• Supports 2 DDR3 channels
Processor Intel® Core™ i7-4700EQ • 1364-pin BGA Foot-Print
Processor

Chipset Mobile Intel® QM87 Chipset • 695-pin BGA Foot-Print

The Dev Kit supports:
F Memory 2x DDR3/DDR3L ECC U-DIMM • DDR3 frequency of up to
E slots 1600 MT/s
A • J7G1 (Channel A)
T • J7G2 (Channel B)
Can be supported as:
U
PCIe*/ 1x PCI 3.0 Express x16 • 1x16 PEG through x16 slot on Dev Kit
R
External
E Graphics
• DDI Port B
D Video Display Port • Back panel Display Port connector
E • DDI Port C
S Video High Definition Multimedia • Back panel HDMI connector
Interface (HDMI)
C
• DDI Port D
R
Video Digital Video Interface (DVI) • Back panel DVI connector
I
P • Supports VGA through Dongle
T Video Video Graphics Array (VGA)
I • 10/100/1000 Mbps Ethernet through
O On-Board Ethernet the onboard PHY.
N LAN • On board RJ45 interface
• Support for Serial Flash Discovery
BIOS (SPI) SPI flash devices parameter (SFDP)
• Supports TPM
• 2x 8 MB SPI Flash device parts
provided on board
• Support new Dual I/O Fast read,
Quad I/O Fast read, Quad Output Fast
read
20-pin header
TPM TPM on SPI Interface
All 4 ports capable of 6GT/s
SATA Up to 4x SATA Ports • 3 Cable Connector
• 1 to Mini PCIe

8 User Guide
 Dev Kit Comments
Implementation
• 6 USB2.0 ports on back panel.
USB2.0 Up to 7 USB 2.0/1.1 Ports Out of which USB2.0 port (0,1) &
USB3.0 ports (1,2) are paired and
connected to a dual USB2.0/3.0 combo
connector. USB2.0 port (12,13) are
stacked together with Display Port.
USB2.0 port (6,7) are stacked together
with eSATA.
• 1 USB2.0 port (4) to Mini PCIe
• 2 USB3.0 ports (1,2) muxed with
USB3.0 2 USB3.0 Ports USB2.0 ports (0,1) and connected to
dual USB2.0/3.0 combo connector
• Over current protection provided
• 2x5 for Serial header
SIO Serial IO
• Two fan controllers for CPU and
Chassis
• Supports PECI
3.5 mm connector for Audio in/out
Audio 7.1+2 HD Audio CODEC
SPDIF (Digital Interconnect Format)
ALC892 7.2 from Realtek*
Implementation similar to earlier
RTC Battery-backed real time Platforms.
clock
• Full-Clock Integration Mode
Clock Integrated clock from PCH (FCIM) is supported by default
• 15A max
Power 12V DC Power Brick
Supply
• On board CPU PCH XDP Port
Debug CPU and PCH XDP • On board Port 80. Two seven-segment
Interfaces displays
Port 80 display

Form Mini-ITX form factor • 8 layer board – 6.7” x 6.7”

Factor

User Guide 9
2.2 Power Supply Solutions, Usage and
Recommendation
The Development Kit must be supplied by a power brick with the following
specification:
• DC Voltage : +V = 12V; -V = Ground
• Current Range : 15A Maximum
• Rated Power : 180W Maximum
• Pin out as per Figure 2

Figure 2. Pin Out Specification

• Any Power brick can be used as long as the Power and Pin Out match the specification.
Using the wrong power type or pin type may damage the board permanently. For
example, Mean Well GS220A12-R7B matches the requirement for the power supply.

10 User Guide
3 Development Kit Summary

3.1 Features
Figure 3. Development Kit Top View

Table 2 shows the major components of the Development Kit and its reference
designation.

User Guide 11
 Table 2. Development Kit Components List

Item# Description Reference

1 CPU U3E1

2 CPU PCH XDP J1T1

3 CPU Fan Connector J1D1

4 DDR3 DIMM A0 J7G1

5 DDR3 DIMM B0 J7G2

6 PCH U6C1

7 SATA0 Connector J7C1

8 SATA1 Connector J7C2

9 SATA2 Connector J7C3

10 SATA HD Power J1C1

11 PCIe 3.0 x16 Connector J1B1

12 Mini PCIe Connector J7F1

13 Serial Port J7E1

14 Speaker LS5E1

15 Front Panel Header J7D1

16 Front Panel LED Header J1E2

17 Power Button Header J1E3

18 Port 80 Display DS5F1

19 Coin cell battery holder BT5F1

20 SIO NCT6776F U7E1

21 SPI Based TPM Header J7C4

22 AUX Fan Header J1E1

12 User Guide
 Item# Description Reference

24 ATX 2x2 Power Connector J1A1

Figure 4. Development Kit Bottom View

User Guide 13
3.2 Connectors, Headers & Jumpers

Caution: Many of the connectors provide operating voltage (+5 V DC and +12 V DC,
for example) to devices inside the computer chassis, such as fans and internal
peripherals. Most of these connectors are not over-current protected. Do not use
these connectors for powering devices external to the computer chassis. A fault in the
load presented by the external devices could cause damage to the computer, the
interconnecting cable, and the external devices themselves.

This section describes the board’s various connectors, headers and jumpers.

3.2.1 Back Panel Connectors

Figure 5 shows the back panel connectors on the board.

Figure 5. Dev Kit Back Connector

Table 3. Back Panel Connectors

Item# Description Reference
1 HDMI connector J2A1
2 DVI Connector J3A1
3 Display Port with dual USB2.0 Connector J4A1
4 eSATA Port with dual USB2.0 Connector J5A1
5 Dual USB 3.0 with RJ45 Connector J6A1
6 Five port Audio Jack and SPDIF J7A1

14 User Guide
3.2.2 Front Panel Header

The Development Kit has a front panel header comprising the pin out for the Power
Switch, Reset Switch, Hard Drive Activity LED, Power LED and +5V DC. Figure 6 shows
the pin out for the header. The header is located at J7D1; refer to Figure 3 for location
on board.

Figure 6. Front Panel Header Pin Out Diagram

Table 4. Front Panel Header Pin Out Description

Pin Signal In/ Description Pin Signal In/ Description
Out Out
Hard Drive Activity LED Power LED
1 HD_PWR Out Hard disk 2 HDR_BLNK_G Out Front panel
LED pull-up RN green LED
to +5 V
3 HAD# Out Hard Disk 4 HDR_BLNK_YE Out Front panel
active LED L yellow LED
Reset Switch On/Off Switch
5 Ground Ground 6 FPBUT_IN In Power switch
7 FP_RESET# In Reset switch 8 Ground Ground
Power Not Connected
9 +5V Power 10 N/C Not
Connected

• The Power Switch is also alternatively accessible from header J1E3. A button/switch needs
to be connected to these pins.

• The Power LED can use either a Single-colored or a Dual-colored Power LED. The header
is also alternatively accessible from header J1E2.

User Guide 15
3.2.3 CPU Straps

Reference DEV KIT Comments

Implementation
(Resistor)
CFG [1:0] N/A Reserved
CFG [2] R5R2 – Unstuffed PCIe x16 lane Reversal
LOW = Lane Reversal
HIGH = Normal Operation (Default)
CFG [3] R4R1 – 1KΩ to Ground MSR Privacy Bit Feature
LOW = Default setting overridden (Default)
HIGH = Debug capability determined by
IA32_Debug_Interface_MSR
CFG 4 R4E1 – Unstuffed eDP Enable
LOW = Enable
HIGH = Disable (Default)
CFG [6:5] R5R1 (CFG 5) – Unstuffed PCIE PORT BIFURCATION
R4P6 (CFG 6) – Unstuffed 00 : 1 x8, 2 x4 PCIe
01 : Reserved
10 : 2 x8 PCIe
11 : 1 x16 PCIe (Default)
CFG [19:7] N/A Reserved

16 User Guide
3.2.4 Configuration Jumpers/Switches
Caution: Do not move jumpers with the power on. Always turn off the power and
unplug the power cord from the computer before changing jumper settings. Modifying
jumpers with the power on may cause damage to the board.

Table 5. Configuration Jumper/Switches

Reference Comments
Flash Descriptor Security Override
J6B1 (1-2) : Enable Security
Open : Disable (Default)
RTC Reset
J6D1 (1-2) : Clear PCH RTC
Open : Normal (Default)
SRTC Reset
J6D2 (1-2) : Clear ME RTC
Open : Normal (Default)
BIOS Recovery
(1-2) : Recover Mode
J7D2
Open : Normal (Default)
GPIO22 of Intel 8 Series PCH

3.3 LEDs
The following LEDs provide status of various functions:

Table 6. Development Kit LEDs

Reference Function

DS4C1 VCC3P3_A (Yellow LED)

DS4C2 CATERR - Indicates CATASTROPHIC ERROR (Red LED)

DS6E1, Mini-PCIE LAN Status (Green LED)

DS6E2,
DS6E3

User Guide 17
4 Quick Start Guide
The following sections summarize the necessary hardware and power-on instructions
for the Development Kit.

4.1 Required Peripherals

• Fan/Heat sink combination for processor

• DDR3 SDRAM ECC U-DIMM

• Mobile 12V DC Power Brick

• Keyboard, Mouse

• SATA Hard Drive

• SATA cable

• PCI Express* Graphics Card if not using Internal Graphics

• External display

18 User Guide
4.2 Instructions to Flash BIOS to SPI
• It can be programmed in dual I/O mode as well as quad I/O mode for more speed.
• In-Circuit programming of SPI flash is supported only when the system power is
OFF.
• The Dediprog SF600 with Adaptor B is connected to the header at J7C4.

Figure 7. Dediprog SF600 with Adaptor B

1. Install the latest USB drivers for the SF600 Dediprog Programmer on host
platform.

2. Ensure that the target board that needs to be programmed is in the S5 State.

a. Connect power to board and the VCC3P3_A (DS4C1) LED will glow
indicating the system is in the S5 state.

3. Launch the Dediprog tool and confirm the settings in the menus from Config 
Miscellaneous Settings  Dual/Quad IO Option  select Always Single I/O.
Default is single I/O.

4. Ensure that “Currently working on” is in “Application Memory Chip 1”.

5. Go to “File” and select the .bin file to program chip1.

6. Execute the batch operation to erase and program the chip.

7. Ensure Quad IO/Single IO is set when the programming begins.

8. On seeing “no operation on-going” at the bottom left, switch to “Application

Memory chip 2”.

9. Select the .bin file for chip2 and execute batch operation.

User Guide 19
4.3 Power Up
Complete the following steps to operate the Development Kit.

• Place one or more DDR3 SO-DIMMs in memory sockets, populating J7G1 and/or
J7G2
• Attach the heat sink/fan for the processor at U3E1 and plug the fan power cable
into J1D1.
• Install the configuration jumpers as shown in Table 5 of this document
• Verify presence of RTC battery in Battery Holder at BT5F1.

The following steps must be completed by the user:

• Plug a Power Brick into chassis. Alternatively, if a chassis is not used, connect the
power brick to the board’s ATX 2x2 Power Connector (J1A1) using power cable.
• Attach a hard drive in J7C1, J7C2, and/or J7C3.
• Connect a USB keyboard in one of the USB connectors.
• Connect a USB mouse in one of the USB connectors.
• If internal graphics is not used, plug a PCI Express Graphics card in the PCI-E x16
slot J1B1 and connect a monitor to the card. (Only if chassis is not used)

Powering up the board:

• Press the Front Panel power button that is connected to either J7D1 or J1E3.
• As the system boots, press F2 to enter the BIOS setup screen.
• Check time, date, and configuration settings. The default settings should be
sufficient for most users.
• The PCIe hot plug support has to be enabled in setup if hot plug detect is
required.
• Save and exit the BIOS setup.
• The system boots and is ready for use.

Powering down the board:

There are three options for powering-down the Dev Kit:

• Use OS-controlled shutdown through the Windows Start menu (or equivalent)
• Press the Front Panel power button connected to the motherboard at J7D1 or J1E3
to begin power-down.
• If the system is hung, it is possible to asynchronously shut the system down by
holding the power button down continuously for 4 seconds.
• Intel does not recommend powering down the board by simply shutting off
power at the power supply.

20 User Guide