DESIGN OF LOW POWER CMOS LATCH

PROJECT REPORT
Submitted in partial fulfilment of the
requirements for the award of the degree
of
BACHELOR OF TECHNOLOGY
in
ELECTRONICS ENGINEERING

by
ISHANK VARSHNEY
14LEB431
HIRDESH KUMAR
14LEB432

Supervisor
DR. NAUSAHD ALAM

DEPARTMENT OF ELECTRONICS ENGINEERING

ZAKIR HUSAIN COLLEGE OF ENGINEERING & TECHNOLOGY
ALIGARH MUSLIM UNIVERSITY ALIGARH
ALIGARH-202002 (INDIA)
APRIL, 2018
 STUDENTS’ DECLARATION

I hereby certify that the work which is being presented in this project report entitled “DESIGN OF LOW
POWER CMOS LATCH” in partial fulfilment of the requirements for the award of the Degree of Bachelor
of Technology and submitted in the Department of Electronics Engineering of the Zakir Husain College
of Engineering & Technology, Aligarh Muslim University, Aligarh is an authentic record of my own work
carried out during final year of B. Tech. under the guidance of Dr. Naushad Alam, Assistant Professor,
Department of Electronics Engineering, Aligarh Muslim University, Aligarh.

ISHANK VARSHNEY HIRDESH KUMAR

This is to certify that the above statement made by students is correct to the best of my
knowledge.

(Dr. Naushad Alam)

Project Guide

Date:
Electronics Engineering Department
Aligarh Muslim University
Aligarh -202002, India

CERTIFICATE

This is to certify that the project entitled “Design of Low Power CMOS
Latch” which is being done by the Ishank Varshney and Hirdesh Kumar, in
partial fulfilment of the requirement for the award of the degree of
Bachelor of technology in Electronics Engineering of the faculty of the
Engineering and Technology, Aligarh Muslim University, Aligarh, India, for
the session 2017-18, is a record of their work carried by them under my
supervision.

Dr. Naushad Alam

Date-
Professor
Electronics Engineering Department
Aligarh Muslim University
 DEPARTMENT OF ELECTRONICS ENGINEERING

Aligarh Muslim University

Aligarh, India

Acknowledgement

I would like to express my profound gratefulness to my supervisor Dr. Naushad Alam for
his guidance, support and constant encouragement. I am thankful to him for having faith
in my ability and potential. His deep insight and broad knowledge provided me with
valuable inputs and helped me to achieve this goal in a timely manner. I also highly
appreciate the resources he provided with and that too conveniently.

I would like to thank my friends and family members who out of their comfort zone,
helped me to achieve my goal in a stress-free manner.

(Ishank Varshney) (Hirdesh Kumar)

 ABSTRACT

With the advancement in technology in today’s world, there has been a growing
demand of lower power consumption by electronic devices. Earlier 180nm
technology with a 1.8V supply was used. But now we have come down a long way,
with research going on towards 10nm technology. The need of the time is to
develop new design techniques which provides better performance in terms of
fast speed, less area and consumes low power.

This report mainly focuses on the analysis of various topologies of D Flip Flop.
Various performance parameters like average power, average delay and average
PDP have been estimated. The layout was done using an open source software
namely Electric VLSI Design System which is an Electronic Design Automation
(EDA) tool. LT Spice (Simulation Software) is used to carry out the simulation
work. The technology node used is 22nm PTM with a supply voltage of 1V.

Also, a new circuit of D latch was proposed. This was compared with the
reference latch at different parameters as mentioned earlier. A flip flop was
designed using the proposed D latch. Its working was analysed at different
voltages and temperatures. A 3 bit Johnson’s counter was also designed and its
working was verified.
CONTENTS……

CHAPTER 1: INTRODUCTION TO SEQUENTIAL CIRCUITS

1.1 INTRODUCTION 1
1.2 LOW POWER LATCH 2

CHAPTER 2: LITERATURE SURVEY

2.1 DESIGN METHODOLOGY 3

CHAPTER 3: SOFTWARES USED

3.1 ELECTRIC VLSI 4
3.2 LT-SPICE 5

CHAPTER 4: D-FLIPFLOPS
4.1 TGFF 6
4.2 TGFFv2 8
4.3 TGMSFF 10
4.4 HLFF 12
4.5 PHLFF 14

CHAPTER 5: SIMULATIONS
5.1 SIMULATION SETUP 16
5.2 SPICE CODE 18
5.3 RESULTS 19

CHAPTER 6: PROPOSED LATCH

6.1 CIRCUIT DIAGRAM AND ITS WORKING 23
6.2 REFERENCE LATCH 26

CHAPTER 7: RESULTS
7.1 COMPARISON WITH REFERENCE LATCH 29
7.2 FLIP-FLOP RESULTS 30
7.3 JOHNSON’s COUNTER 34

PROJECT OVERVIEW AND CONCLUSIONS 35

REFERENCES 36
 CHAPTER-1
INTRODUCTION TO SEQUENTIAL CIRCUITS

LOGIC
CIRCUITS

COMBINATIONAL SEQUENTIAL

BISTABLE MONOSTABLE ASTABLE

Fig1.1: Hierarchical diagram of Logic Circuits.

Logic circuits are classified into two categories namely, Combinational logic and Sequential
logic. Combinational logic or non-regenerative circuits are those whose output depends only
on current inputs while Sequential circuits or regenerative circuits are those whose output not
only depends on the current inputs but also on the previous outputs. In other words, we can say
that sequential circuits contains memory. Fig1.2 shows a block diagram of sequential circuits
contains a combinational circuit block and registers. The output of this finite state machine
(FSM) depends upon the inputs and the current state. The next state of the FSM which is the
input of the register depends upon the current inputs and the current state. The sequential
circuits are classified as:
• BISTABLE: Contains two stable states.
• MONOSTABLE: Contains only one stable state.
• ASTABLE: Contains no stable state.
 Fig1.2: Block diagram of a sequential circuit (FSM)

Sequential circuits like shift registers, counters etc. are mostly used in Very Large Scale
Integrated (VLSI) circuits. The memory element used in the sequential circuits is a latch (or
register). Latch is a level sensitive device used to store one bit information. The D (or Data)
latch is used to latch the logic levels present on the data input when clock is high. The main
constraints are taken into consideration while designing VLSI chips are:
• Power Dissipation
• Speed
• Area

Power consumption plays a crucial role and nowadays become the most important in above
three challenges for the semiconductor industry. The major sources of the power dissipation in
the CMOS circuits are:
• Switching power: Due to node capacitances.
• Short circuit power: Due to current flowing during transitions.
• Static power: Due to leakage current.

Therefore, the objective of the designers in the industry is to reduce the power dissipation
without affecting the other parameters like propagation delay, area etc. But as we know there
is a trade-off in these parameters so that the designers always tried to solve the problem in the
optimum way. Here, our objective is to design a CMOS latch that consume less power with
good other parameters results which can be used in various applications like shift register,
Johnson’s counter etc.
 CHAPTER-2
LITERATURE SURVEY

2.1. Design Methodology

There are basic design rules which are to be used in order to design an IC layout successfully.
These rules are called layout design rule. The layout rule which is to be followed in Electric
VLSI Design System has a universal parameter λ in which rule described. Table.1 gives the
clarification about layout design rule. [2]

WELL
minimum well size 12λ
minimum well spacing between same potential 6λ
minimum well spacing between different potential 0λ
minimum well area 144λ2
POLYSILICON1
minimum polysilicon1 width 2λ
minimum polysilicon1 spacing 3λ
minimum spacing between polysilicon1 to metal N/A
minimum polysilicon1 area 4λ2
POLYSILICON2
minimum polysilicon2 width 2λ
minimum polysilicon2 spacing 3λ
minimum spacing between polysilicon1 to metal N/A
minimum polysilicon2 area 4λ2
METAL 1,2,3,4,5
minimum metal width 3λ
minimum spacing between same metal 3λ
minimum spacing between different metals N/A
minimum metal area 9λ2
METAL 6
minimum metal 6 width 5λ
minimum metal 6 spacing 5λ
minimum spacing between metal 6 to other metals N/A
minimum metal 6 area 25λ2
VIA 1,2,3,4
minimum via width 2λ
minimum via area 4λ2
VIA 5
minimum via 5 width 3λ
minimum via 5 area 9λ2
 CHAPTER-3
SOFTWARE USED

3. SOFTWARE USED

3.1. What is Electric VLSI Design System?

Electric VLSI Design System is an open source and very powerful full custom IC Design
Electronic Design Automation (EDA) tool. This tool consists of three processes for verifying
the IC Design layout. These three processes are DRC (Design Rule Check), LVS (Layout
Versus Schematic) and ERC (Electrical Rule Check).

Design Rule Check (DRC): It is the first and very powerful process of verification to check
IC design Layout. It checks the designs created by the designers and also the design placed in
the context where it will be used. So, the probability of design errors will be reduced and a
very high reliability of design and overall yield will be achieved. [2]
 Layout Versus Schematic (LVS): It is the second and very powerful process of verification to
match layout with its equivalent schematic design. Here, schematic is assumed as a reference
and then the layout is checked against it. Also, the connectivity of all the signals, as well as the
input, output and power signals to their corresponding schematic are checked. In addition to
this, the sizes of the device are checked including the transistor’s length and width, sizes of
capacitors and resistors.

Electrical Rule Check (ERC): It is the third and optional process of verification to check the
layout. Its purpose is to check the error in connectivity of device. It is mostly used to find any
unconnected, partly connected or redundant devices. Besides that, it also checks any transistor
that is disabled, nodes which are floating and short circuits. [2]

3.2. What is LTspice?

LTspice XVII is a software used for simulation and we have used the same in this project. It is
a Spice III simulator providing high performance .It also provides schematic capture and
waveform viewer with enhancements and also models for providing ease in the simulation of
switching regulators. Enhancements have made simulating switching regulators very fast in
comparison to the normal Spice simulators, this allows the user to view the waveforms for
most of the switching regulators in few minutes. It also provides us the facility to simulate the
outputs of both the schematic circuit and layout during DRC and LVS. [2]
 CHAPTER-4
D-FLIPFLOPS

4.1. Transmission Gate Flip-Flop (TGFF)

Fig 4.1.1: Circuit Diagram of Transmission Gate Flip-Flop. [5, 6]

To overcome the voltage-drop problem in the pass transistor logic, Transmission gates are used.
The transmission gates are formed by combining a PMOS transistor in parallel with the NMOS
transistor. The NMOS transistor passes a strong “0” and a weak “1” while the PMOS passes a
strong “1” and a weak “0”. Hence, the NMOS is used to pull down the device and the PMOS
to pull up. The control signals (here CLK and CLKB) are complementary to each other. The
transmission gates are bidirectional in nature controlled by the control signals. When the
control signal is active low (or active high), the PMOS (or NMOS) will provide path to the
input logic.
 Fig 4.1.2: Layout View of Transmission Gate Flip-Flop.

Fig 4.1.3: Output Waveforms of Transmission Gate Flip-Flop.

4.2. Modified Transmission Gate Flip-Flop (TGFFv2)

Fig 4.2.1: Circuit Diagram of Modified Transmission Gate Flip-Flop. [5]

The figure shows the modified version of the transmission gate flip-flop. The transmission
gates are used for both the master latches and the slave latches. The stack of the transistors are
used in both the topologies of transmission gate to reduce the power dissipation. The gate inputs
of these stacked transistors are modified, the only modification in the second topology to see
the behavior of the flip-flop. The isolation at the inputs provides the better noise immunity. The
additional inverters at the outputs are used to reduce the loading effect. As the transmission
gates are used, the voltage drop problem is also resolved.
 Fig 4.2.2: Layout View of Transmission Gate Flip-Flop.

Fig 4.2.3: Output Waveforms of Modified Transmission Gate Flip-Flop.

4.3. Transmission Gate Master-Slave Flip-Flop (TGMSFF)

Fig 4.3.1: Circuit Diagram of Transmission Gate Master-Slave Flip-Flop. [5]

The master-slave topology of the transmission gate is shown in figure. The master-slave
transmission gate topology is best suited to increase the speed (or to minimize the delay). It is
one of the fastest classical topologies, to improve the performance of the flip-flop. The master
latch and the slave latch are identical except that the control signals of the transmission gate
are inverted.
When CLK is active high (or CLKB is active low), the master latch is active and hence, slave
latch is isolated to the data input therefore, there is no change at the output due to change in the
input. The data is passed to output of the master latch. Now the CLK is active low (or CLKB
is active high), so that the master latch is inactive and the slave latch is active. The output of
the master latch is the input to the slave latch, therefore, the data stored on the output of the
master latch will passed to output Q.
The advantages of the topologies of transmission gate flip-flops are as follows: robustness (rail
to rail swing), low power dissipation, high speed (or low propagation delay), better noise
immunity.
 Fig 4.3.2: Layout View of Transmission Gate Master-Slave Flip-Flop.

Fig 4.3.3: Output Waveforms of Transmission Gate Master-Slave Flip-Flop.

4.4. Hybrid Latch Flip-Flop (HLFF)

Fig 4.4.1: Circuit Diagram of Hybrid Latch Flip-Flop. [3, 6, 7]

The hybrid latch flip-flop contains two stages namely, the front-end stage and the back-end
stage. The former is a simple pulse generator stage and the latter is used to capture the pulse as
a latch. One of the biggest advantage of the hybrid latch flip-flop is that the setup time is
negative therefore D-Q delay is small or we can say that the propagation delay is minimum as
compared to other topologies. The pulsed flip-flops like hybrid latch flip-flop, pulse-generator-
free hybrid latch flip-flop have a simpler circuitry as compared to transmission gate flip-flops.
But this topology has a major drawback of large static and dynamic power dissipation hence
the overall average power is quite large as compared to the topologies of the transmission gate
flip-flips.
 Fig 4.4.2: Layout View of Hybrid Latch Flip-Flop.

Fig 4.4.3: Output Waveforms of Hybrid Latch Flip-Flop.

4.5. Pulse-Generator-Free Hybrid Latch Flip-Flop (PHLFF)

Fig 4.5.1: Circuit Diagram of Pulse-Generator-Free Hybrid Latch Flip-Flop. [8]

Pulse-generator-free hybrid latch flip-flop is one of the high performance implicitly pulsed flip-
flops. It also contains a pulse generator and a latch used for data storage. It has similar
advantages like hybrid latch flip-flop of high speed (negative setup time) and less complexity.
Now a days, pulsed flip-flops are widely as compared to transmission gate flip-flops. As there
is a trade-off between the between the parameters, this circuit has more static power
consumption but resulting in faster flip-flop.
 Fig 4.5.2: Layout View of Pulse-Generator-Free Hybrid Latch Flip-Flop.

Fig 4.5.3: Output Waveforms of Pulse-Generator-Free Hybrid Latch Flip-Flop.

 CHAPTER-5
SIMULATIONS

5.1. SIMULATION SETUP

DATA

CLOCK
Fig 5.1: The simulation Setup

❖ CLK-Q DELAY

TCQ min indicates the speed of the sequential cells and is defined by the path from clock to the
Q output. It is measured when the data settles before the clock edge sufficiently.

❖ SETUP TIME

The setup time is defined as data to clock delay and is obtained by sweeping the input data
transition edge with respect to the clock edge to find the point where the clock-to-output delay
is 10% higher than the nominal Clock-Q delay (1.1 TCQ min).

❖ D-Q DELAY

TDQ min is achieved by selecting the optimum setup skew, which includes both the worst TCQ
min and Tsetup. In other words, the D-Q delay is the summation of the Clock-Q delay and the
setup time.

❖ RISE TIME

Rise time is the time taken for the amplitude of a pulse to increase (rise) from a specified value
(usually 10% of the minimum value) to another specified value (usually 90% of the minimum
value).
❖ FALL TIME

Fall time (or pulse decay time) is the time taken for the amplitude of a pulse to decrease (fall)
from a specified value (usually 90% of the peak value) to another specified value (usually 10%
of the maximum value).

76

CLOCK-OUTPUT DELAY (PS)

72

68

Minimum D-Q delay

64

60
0 20 40 60 80 100 120
Tsetup
DATA-TO-CLOCK OFFSET (PS)

❖ STATIC POWER

The power consumed by a D flip-flop when neither the clock nor the D input have active inputs
(i.e., all inputs are "static" because they are at fixed dc levels). CMOS devices have very low
static power consumption, which is the result of leakage current. This power consumption
occurs when all inputs are held at some valid logic level and the circuit is not in charging states.

❖ DYNAMIC POWER

When switching at a high frequency, dynamic power consumption can contribute significantly
to overall power consumption. Charging and discharging a capacitive output load further
increases this dynamic power consumption. The dynamic power includes both the ac
component as well as the static component.

❖ AVERAGE POWER

Average power (considering 1 GHz clock frequency is measured in μW) is the average amount
of work done or Energy transferred per unit time.

❖ AVERAGE PDP (Power-Delay Product)

PDP stands for the average energy consumed per switching event (i.e., for a 0to1, and a 1to0
transition). It is the product of the average D to Q delay and average power.
5.2. SPICE CODE

/* INITIALIZATION*/
.include C:\Users\Documents\Electric\22nm_bulk.pm.txt
V1 D 0 pulse 0 1 100p 10p 10p 500p 1000p
V2 CLK 0 pulse 0 1 300p 10p 10p 500p 1000p
vdd vdd 0 DC 1V
cload1 Q 0 2fF
cload2 QB 0 2fF
.tran 10p 1500p

/* RISE TIME & FALL TIME */

.measure TRAN t_rise TRIG V(Q) VAL=0.1v RISE=1 TARG v(Q) VAL=.9V RISE=1
.measure TRAN t_fall TRIG V(Q) VAL=0.9v FALL=1 TARG v(Q) VAL=.1V FALL=1

/* STATIC POWER */
V1 D 0 DC 0V
V2 CLK 0 DC 0V
.measure TRAN i FIND I(vdd) AT=t1
.measure TRAN v FIND V(vdd) AT=t1
.measure TRAN power PARAM=i*v

/* DYNAMIC POWER */
.measure TRAN t1 WHEN V(CLK)=0.01v RISE=1
.measure TRAN t2 WHEN V(Q)=0.99v RISE=1
.measure TRAN iavg AVG I(cload1) FROM=t1 TO=t2
.measure TRAN vavg AVG V(vdd) FROM=t1 TO=t2
.measure TRAN power PARAM=iavg*vavg

/* AVERAGE POWER */
.measure TRAN t1 WHEN V(CLK)=0.01v RISE=1
.measure TRAN t2 WHEN V(CLK)=0.01v RISE=2
.measure TRAN iavg AVG I(vdd) FROM=t1 TO=t2
.measure TRAN vavg AVG V(vdd) FROM=t1 TO=t2
.measure TRAN power PARAM=iavg*vavg
.measure TRAN avgpow AVG POWER FROM=t1 TO=t2
5.3. SIMULATION RESULTS

5.3.1. TGFF

Parameters Pre-layout Simulation Post-layout Simulation

TcQ min 0 to 1 61.5 79.62
(ps) 1 to 0 74.1 97.56
Tsetup 0 to 1 22 43
(ps) 1 to 0 15.5 35
TDQ min 0 to 1 89.55 130.8
(ps) 1 to 0 97 142.3
Rise Time (ps) 72.01 85.11
Fall Time (ps) 60.43 74.03
Static power 0 to 1 0.16
(μW) 1 to 0 0.22
Dynamic power 0 to 1 12.90 10.83
(μW) 1 to 0 14.17 11.41
Average power(μW/GHz) 4.70
Average PDP (aJ) 438.39

5.3.2. TGFFv2

Parameters Pre-layout Simulation Post-layout Simulation

TcQ min 0 to 1 67.74 86.5
(ps) 1 to 0 77.74 103
Tsetup 0 to 1 23.5 45.3
(ps) 1 to 0 16 33.6
TDQ min 0 to 1 98.11 140.35
(ps) 1 to 0 100.78 146.71
Rise Time (ps) 74 87.15
Fall Time (ps) 63.4 77.30
Static power 0 to 1 0.17
(μW) 1 to 0 0.27
Dynamic power 0 to 1 12.37 10.41
(μW) 1 to 0 13.61 10.94
Average power(μW /GHz) 4.01
Average PDP (aJ) 398.77
5.3.3. TGMSFF

Parameters Pre-layout Simulation Post-layout Simulation

TcQ min 0 to 1 66.43 97.2
(ps) 1 to 0 67.5 95.3
Tsetup 0 to 1 28.5 52.3
(ps) 1 to 0 17.2 29
TDQ min 0 to 1 101.54 159.2
(ps) 1 to 0 91.45 133.83
Rise Time (ps) 70.55 85.89
Fall Time (ps) 53.15 64.97
Static power 0 to 1 0.106
(μW) 1 to 0 0.164
Dynamic power 0 to 1 11.99 9.17
(μW) 1 to 0 14.79 11.29
Average power(μW /GHz) 3.56
Average PDP (aJ) 343.52

5.3.4. HLFF

Parameters Pre-layout Simulation Post-layout Simulation

TcQ min 0 to 1 44.76 49.23
(ps) 1 to 0 11.37 13.57
Tsetup 0 to 1 -1 -0.5
(ps) 1 to 0 0.2 0.8
TDQ min 0 to 1 48.23 53.65
(ps) 1 to 0 12.70 15.72
Rise Time (ps) 43.67 49.03
Fall Time (ps) 23.66 27.51
Static power 0 to 1 1.43
(μW) 1 to 0 2.64
Dynamic power 0 to 1 20.22 18.23
(μW) 1 to 0 38.21 33.42
Average power(μW /GHz) 28.85
Average PDP (aJ) 878.91
5.3.5. PHLFF

Parameters Pre-layout Simulation Post-layout Simulation

TcQ min 0 to 1 52.53 62.17
(ps) 1 to 0 56.63 101.1
Tsetup 0 to 1 16.4 12
(ps) 1 to 0 61 1
TDQ min 0 to 1 74.18 80.38
(ps) 1 to 0 123.29 112.2
Rise Time (ps) 32.7 39.07
Fall Time (ps) 21.14 24.78
Static power 0 to 1 0.44
(μW) 1 to 0 0.49
Dynamic power 0 to 1 22.17 19.04
(μW) 1 to 0 24.90 14.25
Average power(μW /GHz) 5.76
Average PDP (aJ) 568.71
❖ TABLE 5.4: COMPARISON BETWEEN VARIOUS TOPOLOGIES

Parameters TGFF TGFFv2 TGMSFF HLFF PHLFF

TCQ min 0 to 1 61.5 67.74 66.43 44.76 52.53

(ps) 1 to 0 74.1 77.74 67.5 11.37 56.63

Tsetup 0 to 1 22 23.5 28.5 -1 16.4

(ps) 1 to 0 15.5 16 17.2 0.2 61

TDQ min 0 to 1 89.55 98.11 101.54 48.23 74.18

(ps) 1 to 0 97 100.78 91.45 12.70 123.29

Rise Time (ps) 72.01 74 70.55 43.67 32.7

Fall Time (ps) 60.43 63.4 53.15 23.66 21.14

Static power 0 to 1 0.16 0.17 0.106 1.43 0.44

(μW) 1 to 0 0.22 0.27 0.164 2.64 0.49

Dynamic power 0 to 1 12.90 12.37 11.99 20.22 22.17

(μW) 1 to 0 14.17 13.61 14.79 38.21 24.90

Average power(μW/GHz) 4.70 4.01 3.56 28.85 5.76

Average PDP (aJ) 438.39 398.77 343.52 878.91 568.71

 CHAPTER-6
PROPOSED LATCH

6.1. CIRCUIT DIAGRAM

Fig 6.1.1: Circuit Diagram of proposed D-Latch.

❖ TABLE 6.1: TRANSISTOR SIZING

Transistor W/L Ratio

Mp1 9.0
Mp4,6,7 4.5
Mp2,3,5 1.5
Mn3 4.5
Mn2,,4,7 2.25
Mn1,5,6 1.5
 Fig 6.1.2: Layout View of proposed D-Latch.

Fig 6.1.3: Output Waveforms of proposed D-Latch

❖ WORKING

Latch is a level sensitive device used to store one bit information. The D (or Data) latch is
used to latch the logic levels present on the data input when clock is high. When clock is
high, the output Q of the latch follows the input D. Similarly, when the clock is low, the
previous state of the data input retained at the output.

The proposed circuit contains transmission gates, inverters and stacked transistors. Instead
of using four transistor in stack, we are using three transistors to reduce the area with the
same performance. The transmission gates are used at the inputs instead of pass-transistor
logic to reduce the voltage-drop problem. The sizing of the circuit is done by the logical-
effort method with the reference circuit shown in above table.

The transistors namely Mp1 and Mn3 are used to pull-up and pull-down the output
respectively. Mp2,3 and Mn5,6 are the keeper transistors in the stack. The control signals
(CLK and CLKB) are generated by the inverter having transistors Mp7 and Mn7. The
transmission gates are formed by combining the NMOS and PMOS in parallel namely Mn2
& Mp4 and Mn4 & Mp6.

When CLK is active high (or CLKB is active low), the transmission gates are ON therefore
the data is stored at the output. Now, the CLK is active low, the transmission gates are OFF,
thus the output is isolated with the input and the previous state is maintained at the output.

❖ TABLE 6.2: SIMULATION RESULTS OF PROPOSED D-LATCH.

Parameters Pre-layout Simulation Post-layout Simulation

T CLK-QB (ps) 37.15 52.09
T D-QB (ps) 29.05 34.40
Rise Time (ps) 39.21 44.10
Fall Time (ps) 30.66 36.36
Static power (nW) 93.72
Dynamic power 0 to 1 23.27 20.70
(μW) 1 to 0 26.12 20.80
Average power(μW /GHz) 3.627 4.151
Area (λ2) 130*71
6.2. REFERENCE D-LATCH

Fig 6.2.1: Circuit Diagram of reference D-Latch.

❖ TABLE 6.3: TRANSISTOR SIZING

Transistor W/L Ratio

Mp1-5 4.5
Mn1-5 2.25

The Data-latch (or D-latch) is shown in figure consists of two transmission gates and two
inverters, and an inverter to generate the complementary controlled signals. The transmission
gate is formed by combining a NMOS and a PMOS in parallel. When the clock is active high,
the transmission gate at the input is ON while the transmission gate in the loop is OFF (and
vice-versa when clock is active low). The D latch is used to latch the logic levels present on
the data input when clock is high i.e. the input data is latched when the clock is active high.
The operation of the above latch is well explained by replacing the transmission gates with the
switches as shown in fig6.2.2.
 Fig 6.2.2: Working mechanism of the reference latch.

The data is applied to input of the latch (setup time and hold time are taken into consideration).
When the clock is high, the transmission gate at the input is ON therefore, the input signal is
reached at the output. Now the clock goes low, the transmission gate in the loop becomes active
thus the output will maintain its previous state (or the output is isolated with the input signal).

Fig 6.2.3: Layout View of reference D-Latch.

 Fig 6.2.4: Output Waveforms of reference D-Latch.

❖ TABLE 6.4: SIMULATION RESULTS OF REFERENCE D-LATCH.

Parameters Pre-layout Simulation Post-layout Simulation

T CLK-QB (ps) 50.68 68.20
T D-QB (ps) 45.25 56.48
Rise Time (ps) 74.71 84.54
Fall Time (ps) 56.84 65.23
Static power (nW) 75.06
Dynamic power 0 to 1 13.42 11.62
(μW) 1 to 0 16.23 13.28
Average power(μW /GHz) 3.313 4.423
Area (λ2) 115*68
 CHAPTER-7
RESULTS

❖ TABLE 7.1: COMPARISON BETWEEN PROPOSED LATCH & REFERENCE

LATCH

Proposed Latch Reference Latch

Parameters Pre-layout Post-layout Pre-layout Post-layout
Simulation Simulation Simulation Simulation
T CLK-QB (ps) 37.15 52.09 50.68 68.20
T D-QB (ps) 29.05 34.40 45.25 56.48
Rise Time (ps) 39.21 44.10 74.71 84.54
Fall Time (ps) 30.66 36.36 56.84 65.23
Static power (nW) 93.72 75.06
Dynamic power 0 t0 1 23.27 20.70 13.42 11.62
(μW) 1 to 0 26.12 20.80 16.23 13.28
Avg power(μW /GHz) 3.627 4.151 3.313 4.423
Area (λ2) 130*71 115*68

With the help of proposed latch and reference latch, we design a flip-flops in the master-slave
topology as shown in fig 7.1 and 7.2 respectively.

Fig 7.1: Circuit Diagram of Master-Slave Flip-flop using proposed D-Latch.

 Fig 7.2: Circuit Diagram of Master-Slave Flip-flop using reference D-Latch.

❖ TABLE 7.2: FLIP-FLOP RESULTS

Parameters WITH REFERENCE LATCH WITH PROPOSED LATCH

#ff1 #ff2
TcQ min 0 to 1 56.01 38.30
(ps) 1 to 0 65.80 56.38
Tsetup 0 to 1 23.5 18.8
(ps) 1 to 0 31.5 13.4
TDQ min 0 to 1 85.11 60.93
(ps) 1 to 0 103.88 75.41
Rise Time (ps) 77.32 42.71
Fall Time (ps) 62.51 42.52
Static power (nW) 154.59 208.74
Dynamic power 0 to 1 12.47 20.77
(μW) 1 to 0 14.28 19.96
Average power(μW /GHz) 4.67 5.09
Average PDP (aJ) 441.29 367.43

The table 7.2 shows the comparison between the flip-flops designed using both the latches. We
found that the flip-flop with the proposed latch is faster than the reference one and also the
power-delay product PDP is lower, but the average power comes to be comparable.
Now, we are trying to find out the behaviour of the flip-flop using proposed latch and reference
latch at different voltage levels. Table 7.3 and 7.4 shows the results of flip-flop using reference
latch and flip-flop using proposed latch respectively. We found that the ff2 is faster than ff1,
lower PDP but power is slightly higher (or comparable with ff1) in ff2.

❖ TABLE 7.3: FLIP-FLOP USING REFERENCE LATCH

Parameters VDD= 1V VDD=0.9V VDD=0.8V VDD=0.6V

TcQ min 0 to 1 56.01 65.98 83.54 220.60
(ps) 1 to 0 65.80 79.85 104.80 302.39
Tsetup 0 to 1 23.5 30.5 40 118
(ps) 1 to 0 31.5 36.5 44.5 109
TDQ min 0 to 1 85.11 103.07 131.89 360.66
(ps) 1 to 0 103.88 124.35 159.78 441.62
Rise Time (ps) 77.32 86.56 102.20 199.63
Fall Time (ps) 62.51 74.12 96.71 314.63
Static power (nW) 154.59 75.91 41.24 11.09
Dynamic 0 to 1 12.47 11.89 5.97 1.58
power (μW) 1 to 0 14.28 11.61 6.02 1.15
Avg power(μW/GHz) 4.67 3.49 2.73 1.47
Average PDP (aJ) 441.29 396.84 398.12 588.94

❖ TABLE 7.4: FLIP-FLOP USING PROPOSED LATCH

Parameters VDD= 1V VDD=0.9V VDD=0.8V VDD=0.6V

TcQ min 0 to 1 38.30 46.02 59.91 179.86
(ps) 1 to 0 56.38 68.05 88.76 248.08
Tsetup 0 to 1 18.8 22 28.5 83
(ps) 1 to 0 13.4 16 21 72
TDQ min 0 to 1 60.93 72.62 94.90 280.84
(ps) 1 to 0 75.41 90.85 118.63 344.88
Rise Time (ps) 42.71 48.15 57.79 135.15
Fall Time (ps) 42.52 49.85 63.92 184.94
Static power (nW) 208.74 92.62 50.12 14.85
Dynamic 0 to 1 20.77 18.82 9.70 2.30
power (μW) 1 to 0 19.96 15.17 8.50 1.73
Avg power(μW/GHz) 5.09 4.32 3.39 1.93
Average PDP (aJ) 367.43 353.09 361.94 603.82
Fig 7.1: Comparison charts of various performance matrices v/s Vdd.
Similarly, we made comparison in ff1 and ff2 at different values of temperature i.e. 25, 50, 75
and so on as shown in table 7.5 and 7.6 respectively to analyse the performance of these two
flip-flops for same voltage node (Vdd=1V). We found that the PDP increases as temperature
increases in both the cases. But the PDP of ff2 is lower than PDP of ff1 and the bar chart is
shown in fig 7.2.

❖ TABLE 7.5: FLIP-FLOP USING REFERENCE LATCH #ff1 (VDD=1V)

Parameters T=25 °C T=50 °C T=75 °C T=100 °C T=125 °C

TcQ min 0 to 1 54.34 76.32 100.85 127.65 156.39
(ps) 1 to 0 64.03 87.38 113.47 142.01 172.63
Avg power(μW/GHz) 4.70
Average PDP (aJ) 267.39 383.87 503.65 636.39 776.48

❖ TABLE 7.6: FLIP-FLOP USING PROPOSED LATCH #ff2 (VDD=1V)

Parameters T=25 °C T=50 °C T=75 °C T=100 °C T=125 °C

TcQ min 0 to 1 37.25 51.16 66.66 83.57 101.65
(ps) 1 to 0 54.77 76.24 100.25 126.46 154.50
Avg power(μW/GHz) 5.09
Average PDP (aJ) 234.19 324.23 424.78 534.52 651.90

Fig 7.2: Comparison charts of average PDP v/s temperature.

❖ JOHNSON’s COUNTERS
Here, the output Qbar of the last flip-flop is a feedback to the input of the first flip-flop, this
modification in the traditional ring counter is known as Johnson’s counter as shown in fig7.3.
We implemented a 3 bit Johnson’s counter using flip-flop composed of proposed latch. The
output waveform of Johnson’s counter is shown below which satisfies its working. One of the
major advantage over ring counter is that it requires only half number flip-flop as compared to
ring counter.

Fig 7.3: Block Diagram of 3-bit Johnson’s counter.

Fig 7.4: Output waveform of Johnson’s counter.

 PROJECT OVERVIEW AND CONCLUSIONS

With the increasing demand of low power consumption in modern world, the first
phase of project was started with the study of different VLSI Design technologies.
The technology of 22nm PTM was chosen to work with. The sequential circuit of
different topologies of D flip flop like TGFF, TGFFv2, TGMSFF, HLFF and
PHLFF were analyzed. The layout was done using Electric VLSI design system
and simulation using LT Spice. Mainly, power and time delay were found. The
result were analyzed and conclusions were drawn. It was found that TGMSFF
outshines other designs in terms of average power consumption. TGFF and
TGFFv2 almost tie in the second place. These results come from the fact that
static styles dissipate comparatively lower power.
With this knowledge we have proposed a D-latch circuit which dissipates less
power, provide high speed (or low propagation delay) therefore it has low PDP
as compared to the reference latch. Using both the latches, we design a master-
slave flip-flops and compare their performances on the above parameters. The
behaviour of the flip-flops was also analysed at different voltages and
temperatures and the results obtained shows that the proposed flip-flop has better
performance in terms of speed, PDP as compared to reference one but the average
power comes to be comparable. This opens the scope of further improvement in
the flip-flop designed by proposed D-latch in the context of average power.
 References
[1]. Shiva Taghipour, Rahebeh Niaraki Asli, “Aging comparative analysis of high-
performance FinFET and CMOS flip-flops”, Microelectronics Reliability 69 (2017) 52–
59.
[2]. Raj Kumar Mistri, Rahul Ranjan, “IC Layout Design of 4-bit Universal Shift Register
using Electric VLSI Design System”, International Journal of Engineering Research &
Technology (IJERT), ISSN: 2278-0181 Vol. 6 Issue 04, April-2017.
[3]. K. Ramakrishnan, X. Wu, N. Vijaykrishnan, Y. Xie, “IC Layout Design of 4-bit
Universal Shift Comparative analysis of NBTI effects on low power and high performance
flip–flops”, IEEE International Conference on Computer Design (ICCD) Oct. 12–15,
2008, pp. 200–205.
[4]. Rabaey, Jan M. “Digital integrated circuits: a design perspective”. Prentice-Hall,
Inc. Upper Saddle River, NJ, USA©1996.
[5]. C. Nunes, P.F. Butzen, A.I. Reis, R.P. Ribas, “BTI, HCI and TDDB aging impact in
flipflops, Microelectron. Reliab”, 53 (9–11) (Sep–Nov 2013) 1355–1359.
[6]. K. Absel, L. Manuel, R.K. Kavitha, “Low-power dual dynamic node pulsed hybrid
flipflop featuring efficient embedded logic”, IEEE Trans. Very Large Scale Integr. VLSI
Syst. 21 (9) (Sep. 2013) 1693–1704.
[7]. M.R. Lanuzza, F.F. De Rose, S. Perri, P. Corsonello, “Comparative analysis of yield
optimized pulsed flip-flops”, Microelectron. Reliab. 52 (8) (Aug. 2012) 1679–1689.
[8]. K. Liao, X. Cui, N. Liao, T.Wang, “Design of D flip-flops with low power-delay product
based on FinFET”, IEEE International Conference on Solid-State and Integrated Circuit
Technology (ICSICT) Oct. 28–31, 2014, pp. 1–3.
[9]. About Electric. (May 2013). [Online]. Available: www.staticfreesoft.com/electric.html

[10]. About LTspice [Online]. Available: www.linear.com

[11]. www.cmosedu.com