Академический Документы
Профессиональный Документы
Культура Документы
discharging the capacitor to ground, the charge is 2.2 PFAL BASED NOT GATE
discharged to the power supply. Since the charge The inverter (NOT circuit) performs the
has to be discharged to supply, the supply in operation called inversion or complementation. The
adiabatic circuits is a time varying one called the NOT operation changes one logic level to the
power clock. It has been observed that among the opposite logical level. When the input is Low, the
different waveforms for charging or discharging the output is high. When the input is high, the output is
load capacitor, a ramp is more efficient and as such low. The inverter changes one logic level to the
trapezoidal power clocks have been used in many opposite level. In terms of bits, it changes a 1 to a 0
adiabatic circuit styles [2]. Many adiabatic logic and 0 to 1. When a High level is applied to an
circuits which dissipate less power than static inverter input, a low level will appear on its output.
CMOS logic circuits have been introduced as a When a low level is applied to its input, a High will
promising approach in low power circuit design. appear on its output. PFAL based NOT gate is
shown in Figure 2.
2. MATERIALS AND METHODOLOGY
GATES POWER(mW)
BASIC PFAL
NOT 87.694 83.79
NAND 87.5 50.05
NOR 92.31 64.3
4. CONCLUSION
We conclude that the proposed adiabatic
logic circuit is advantageous to ultra low power
applications. This paper shows the simulation result
of universal gates and also compares the power
values using Tanner EDA. The NOT gate, NOR
gate and NAND gate achieves power reduction of
23%, 36.1% and 42.8% respectively. Among three
gates, NAND gate consume less power. Hence it
proves that positive feedback adiabatic logic based
NAND gate can be used for ultra low power
circuits.
REFERENCES