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EC381
Digital Systems I
University of Tripoli
Digital Systems 1
Schematic symbols for DFF
Digital Systems 2
Example: Timing Diagram of DFF
Change at
rising edge
Digital Systems 3
Sets, resets and enables
Flip-flops can have additional control signals that will force the
output Q to a known value.
An asynchronous signal that forces Q=1 is called an
asynchronous set or preset.
An asynchronous signal that forces Q=0 is called an
asynchronous clear or reset.
It is an asynchronous because the output changes immediately
regardless of what values of clk and D are.
Active high set and reset signals.
Digital Systems 4
Example of set, reset D flip-flop
Digital Systems 5
Toggle flip-flops (TFF)
Another type of flip-flop that has a different behavior when
compared to a DFF.
Symbol for a positive edge-triggered TFF:
Digital Systems 6
Characteristic tables and equations for TFFs
Digital Systems 7
Making a TFF from a DFF
We can actually build a TFF using a DFF and a 2-input XOR
gate.
Digital Systems 8
JK flip-flops (JKFF)
The characteristic table for the JKFF:
Digital Systems 9
Making a JKFF from a DFF
We can actually build a JKFF using a DFF and some other gates.
Digital Systems 10
Ex 1
(Zero-Delay Flip-Flop)
Digital Systems 11
Ex 2
(Flip-Flop Delay)
Digital Systems 12
Ex 3
Digital Systems 13
Ex 4 D-Latch
/Enable
Digital Systems 14
Ex 5
Digital Systems 15
Ex 5 (Negative edge-triggered DFF)
Digital Systems 16
Ex 6
Digital Systems 17
EC 7: D Flip-Flop: PR & CLR Timing
Q
Q=1 Q=1
Preset Preset
PR Q=0
Clear
CLR
CLK
Digital Systems 18
EX 8: Comparison of level-sensitive
D D Q Qa
and edge-triggered D storage
Clock Clk Q Qa elements
D Q Qb
Q Qb
D Q Qc
Q Qc
Clock
Qa
Qb
Qc
Digital Systems 19
EX 8: Comparison of level-sensitive
D D Q Qa
and edge-triggered D storage
Clock Clk Q Qa elements
D Q Qb
Q Qb
Level-sensitive
(the output mirrors the D input when Clk=1)
D Q Qc
Q Qc
Clock
Qa
Qb
Qc
Digital Systems 20
EX 8: Comparison of level-sensitive
D D Q Qa
and edge-triggered D storage
Clock Clk Q Qa elements
D Q Qb
Q Qb
Positive-edge-triggered
D Q Qc
Q Qc
Clock
Qa
Qb
Qc
Digital Systems 21
EX 8: Comparison of level-sensitive
D D Q Qa
and edge-triggered D storage
Clock Clk Q Qa elements
D Q Qb
Q Qb
Negative-edge-triggered
D Q Qc
Q Qc
Clock
Qa
Qb
Qc
Digital Systems 22
Digital Systems 23
Digital Systems 24