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PSG COLLEGE OF TECHNOLOGY, COIMBATORE - 641 004

SEMESTER EXAMINATIONS, NOVEMBER - 2016

MSc - DATA SCIENCE Semester : 3

15XD35 COMPUTER ORGANIZATION AND ASSEMBLY LANGUAGE

PROGRAMMING

Time : 3 Hours Maximum Marks : 100

INSTRUCTIONS:
1. Answer ALL questions from GROUP – I.
2. Answer any FIVE questions from GROUP – II.
3. Answer any ONE question from GROUP – III.
4. Ignore the box titled as “Answers for Group III” in the Main Answer Book.
GROUP - I Marks : 10 x 3 = 30

1. Consider the 4 bit adder – subtractor designed for signed magnitude numbers. It
computes Z = X+Y when SUB control input is 0, and Z = X – Y, when SUB control input
is 1. State the logic equation that defines the overflow V for this circuit.
2. RAM IC is used in a microprocessor system, having 16 bit address line and 8-bit data
line. It’s enable-1 input is active when A15 and A14 bits are 0 & 1, and enable-2 input is
active when A13 , A12 bits are ‘X’ and ‘0’ respectively. What shall be the range of
addresses that is being used by the RAM.
3. If a cache access requires one clock cycle and handling cache misses requires an
additional five cycles, calculate the cache hit rate to achieve an average memory access
of 2 cycles.
4. With regard to I/O devices what is the difference between polling and interrupts?
5. Register R5 is used in a program to point to the top of the stack. Write a sequence of
instructions using the Indexed addressing mode to POP the two top items off the stack,
add them and PUSH the result onto the stack.
6. Distinguish between the following: RISC and CISC architectures.
7. What are vectored interrupts? With the help of an example show how the address of the
Interrupt Service routine is calculated in vectored interrupts.
8. Write the equivalent instruction sequence for each of the following: CMPSB and SCASB
9. How does a prefetch buffer help in instruction pipelining process?
10. State the Flynn’s taxonomy of multiprocessing.

GROUP - II Marks : 5 x 10 = 50

11. Design a hardware circuit to implement logical shift, arithmetic shift and circular shift
operations. State your design specifications.
12. a) With the help of a flow chart, explain the interrupt cycle.

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b) Explain the difference between hardwired control and microprogrammed control. Is it

possible to have a hardwired control associated with control memory?
13. a) How is the physical address generated for different memory addressing modes?
Illustrate with suitable examples.
b) Mention how the following instructions differ in their functionality:
(i) NEG & NOT
(ii) DIV & IDIV
(iii) AND & TEST
(iv) CMP & SUB
14. Design a 3-way set associative cache given the following constraints:
 Total size of 24 words, Block size of 4 words, Word length of 16 bits
 Total addressable memory space is 1024 (1K ) - word-addressed
 Write-back policy
 Least Recently used (LRU) replacement policy
(a) Draw a diagram of the address bits in this machine, and split the address to indicate
offset, tag and index field & state what the bits are used for in this cache.
(b) What is the total size of the cache including the status bits used for write back policy
(c) Fill in the table below, indicating whether each request is a cache hit or miss:
Address 3 1 7 9 5 1 8 1 3 1 1 2 6

H/M

15. a) What is segmentation? Explain how the memory segmentation is implemented in

8086 microprocessor?
b) Explain the operation of Asynchronous data transfer .
16. Show how a typical DMA controller can be interfaced to an 8086 based system and
explain the operation.
GROUP - III Marks : 1 x 20 = 20

17. What is virtual memory? Explain how the logical address is translated into physical
address in the virtual memory system with a neat diagram. Explain the virtual memory
address translation and TLB with necessary diagram
18. Justify how pipelining in the CPU design would improve the performance of CPU. What
are reasons of pipeline conflicts in pipelined processor and how are they resolved?
Discuss any four interconnection structures used in connecting the multiprocessors and
the memory modules.

/END/
FD/RL

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