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Efficient code writing for FSM in verilog

Prepared by :-
Alka Solanki
Chinmay Sharma
Sandip Gajera
Sanket Chikani
Contents
• What is FSM?

•Different Types of FSM

- Mealy FSM
- Moore FSM

• Different Types of Encoding FSM

– Binary coding
– One Hot Coding
– Gray Coding

• Parameters and `define

What is FSM?

A FSM consists of combinational, sequential and output logic.
Combinational logic is used to decide the next state of the FSM,
sequential logic is used to store the current state of the FSM. The output
logic is a mixture of both combo and seq logic.

A finite-state machine (FSM) or simply a state machine, is a mathematical
model of computation used to design both computer programs and
sequential logic circuits.

The machine is in only one state at a time; the state it is in at any given
time is called the current state. It can change from one state to another
when initiated by a triggering event or condition; this is called a
transition.

A particular FSM is defined by a list of its states, and the triggering
condition for each transition.
Types of FSM
Depending on the need, we can choose the type of state machine.
There are two types of state machines:-

Mealy State Machine

Moore State Machine

Mealy State Machine :

In a Mealy machine, the outputs are a function of the present
state and the value of the inputs .
Accordingly, the outputs may change asynchronously in response
to any change in the inputs.

Moore State Machine :

Its output depends on current state only.
The outputs change synchronously with the state transition
triggered by the active clock edge.
Types of FSM
Types of FSM
Comparison
State Encoding Techniques
Encoding Techniques
Since we need to represent the state machine in a digital circuit, we need
to represent each state in one of the following ways:

Binary encoded

Gray encoded

One-hot encoded

The decision on which method to use is a function of design constraints

such as speed, area and power consumption.

And also “optimal” coding of the internal states are based on the minimal
number of states and sometimes also on the minimal number of flip-flops
used in the hardware implementation.
Different Encoding Style

Binary encoding :
Each state is represented in binary code (i.e. 000, 001, 010.…)


Gray encoding :
Each state is represented in gray code (i.e. 000, 001, 011,…)


One-hot encoding :
Only one bit is high and the rest are low (i.e. 0001, 0010, 0100, 1000)
State Encoding Techniques
FSM Encoding
Binary Encoding

In binary encoding, the relationship between the number of state
variables (q) and number of states (n) is given by the equation q=log 2
(n).

The no. of flip-flops used is equal to the number of state variables (q).

In this technique, the states are assigned in binary sequence where the
states are numbered starting from binary 0 and up
Advantage of Binary Encoding

Binary encoding uses fewer flip-flops/registers than one-hot
encoding. For eg., binary encoding requires only seven (flip-flops)
registers to implement a 100-state machine while one hot
encoding needs 100 flip-flops.

Binary encoding uses the min. no. of state variables (flip-flops) to
encode a machine since the flip-flops are maximally utilized.

It is usually the preferred method when implementing machines
that are fewer than 8 states.
Gray Encoding

Gray code assignment is a state assignment in which consecutive states
codes only differ by one bit In other words, only one flip-flop changes at a
time when changing consecutive states.


In this encoding, the number of flip-flops (register) used is also determined
by: Number of flip-flops = log 2 (number of states).

Advantage of Gray Encoding

Advantage of Gray Encoding technique is to minimizes hazards and glitches.
This encoding method is very reliable.
One Hot Encoding

In the one-hot encoding (OHE) only one bit of the state variable is “1”
or “hot” for any given state. All other state bits are zero. Therefore, one
flipflop (register) is used for every state in the machine i.e. n states uses
n flip-flops.

State decoding is simplified, since the state bits themselves can be used
directly to indicate whether the machine is in a particular state

Advantage of One-Hot Encoding


State decoding is simplified , Since the state bits themselves can be
used directly to check whether the fsm is in a particular state or not.
Hence additional logic is not required for decoding, this is extremely
advantageous when implementing a big fsm.

Low switching activity, hence resulting low power consumption and less
prone to glitches.
One-hot Encoding


Modifying a design is easier.


Faster than others encoding techniques.(speed is independent to no.
of states it depends only on the no. of transition into a particular
state).

Disadvantage of One-hot Encoding

The only disadvantage of using One-hot Encoding is that it required

more flip flops than the binary, gray encoding techniques.
Comparison

Binary Encoding Gray Encoding One-hot Encoding

It has less FF and It makes register toggle In one-hot we can easily
register compare to gray less. detect , if we're in an
coding. illegal state.
One bit can flip at any It minimizes hazards Faster than others.
time and can result in a and glitches.
glitch.
It is usually the preferred Decoding Speed is high. It takes one FF for each
method when state.
implementing machines
that are fewer than 8
states.
Verilog Constants
In Verilog there are two ways to define constants: the parameter , a constant that
is local to a module and macro definitions, created using the `define compiler
directive.

A parameter , after it is declared, is referenced using the parameter name.

A `define macro definition, after it is defined, is referenced using the macro name
with a preceding ` (back-tic) character.

It is easy to distinguish between parameters and macros in a design because

macros have a `identifier_name while a parameter is just the identifier_name
without back-tic.
 Parameters
Parameters must be defined within module boundaries using the keyword parameter .
A parameter is a constant that is local to a module that can optionally be redefined on an
instance-by-instance basis using defparam construct.

module hello_world;
parameter id_num = 0;
initial
$display("Displaying hello_world id number = %d", id_num);
endmodule

//define top-level module

module top;
defparam w1.id_num = 1, w2.id_num = 2;
hello_world w1();
hello_world w2();
endmodule
Parameter redefinition using #
Parameter redefinition during instantiation of a module uses the # character to
indicate that the parameters of the instantiated module are to be redefined.

module my_module (Clk, D, Q) ;

parameter width = 2,
delay = 10 ;
input [width - 1 : 0] D ;
input Clk ;
output [width : 0] Q ;
assign #delay Q = D;
endmodule

module top;
reg Clk ;
reg [7:0] D ;
wire [7:0] Q ;
my_module #(7, 25) inst_1(Clk, D, Q) ;
endmodule
localparam
An enhancement added to the Verilog-2001 localparam state1 = 4'b0001,
Standard is the localparam . Unlike a
parameter , a localparam cannot be state2 = 4'b0010,
modified by parameter redefinition state3 = 4'b0100,
(positional or named redefinition) nor can a
localparam be redefined by a defparam state4 = 4'b1000;
statement.
The localparam can be defined in terms of
parameters that can be redefined by parameter Width = 8;
positional parameter redefinition, named localparam Depth = Width*12;
parameter redefinition (preferred) or
defparam statements. localparam Size = 16;
The idea behind the localparam is to permit
generation of some local parameter values
based on other parameters while protecting
the localparams from accidental or
incorrect redefinition by an end-user.
`define Macro Substitution
The `define compiler directive is used to perform "global" macro substitution,
similar to the C-language #define directive. Macro substitutions are global from
the point of definition and remain active for all files read after the macro definition
is made or until another macro definition changes the value of the defined macro
or until the macro is undefined using the `undef compiler directive.
Macro definitions can exist either inside or outside of a module declaration, and
both are treated the same.
Guideline: only use macro definitions for identifiers that clearly require global
definition of an identifier that will not be modified elsewhere in the design.
Guideline: where possible, place all macro definitions into one " definitions.vh "
file and read the file first when compiling the design.
`define CYCLE 10
`define Inclusion
One popular technique to insure that a macro definition exists before its usage is to
use an `ifdef , or the new Verilog-2001 `ifndef compiler directives to query for the
existence of a macro definition followed by either a `define macro assignment or a
`include of a file name that contains the require macro definition.

`ifdef CYCLE
// do nothing (better to use `ifndef)
`else
`define CYCLE 100
`endif
`ifndef CYCLE
`include "definitions.vh"
`endif
State Machines and `define do not mix
Finite State Machine (FSM) designs should use parameters to define state
names because the state name is a constant that applies only to the FSM
module. If multiple state machines are added to a large design, it is not
uncommon to want to reuse certain state names in multiple FSM designs.
Example state names that are common to multiple designs include: RESET,
IDLE,READY, READ, WRITE, ERROR and DONE.
Using `define to assign state names would either preclude reuse of a state name
because the name has already been taken in the global name space, or one
would have to `undef state names between modules and re- `define state names
in the new FSM modules. The latter case makes it difficult to probe the internal
values of FSM state buses from a testbench and running comparisons to the
state names.
Thank You