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AC PERFORMANCE OF NANO ELECTRONICS SEMINAR REPORT ON 2018-19

CHAPTER 1

INTRODUCTION
The phenomenological predictions for the cut off frequency of carbon
nanotube transistors and the predictions of the effects of parasitic capacitances
on AC nanotube transistor performance are presented. The influence of
quantum capacitance, kinetic inductance, and ballistic transport on the high-
frequency properties of nanotube transistors is analyzed. The challenges of
impedance matching for ac Nano-electronics in general, and how integrated
Nano systems can solve this challenge, are presented Nano electronic devices
fall into two classes: tunnel devices and ballistic transport devices. In Tunnel
devices single electron effects occur if the tunnel resistance is larger than h/e″ =
25 KΩ. In Ballistic devices with cross sectional dimensions in the range of
quantum mechanical wavelength of electrons, the resistance is of order h/e″ = 25
KΩ .This high resistance may seem to restrict the operational speed of nano
electronics in general. However the capacitance values and drain source spacing
are typically small which gives rise to very small RC times and transit times of
order of ps or less. Thus the speed may be very large, up to THz range.

The goal of this seminar is to present the models an performance predictions


about the effects that set the speed limit in carbon nanotube transistors, which
form the ideal test bed for understanding the high frequency properties of Nano
electronics because they may behave as ideal ballistic 1d transistor

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LITERATURE SURVEY
I. we referred following paper for writing this seminar report.

1. In this paper we present phenomenological predictions for the cutoff frequency


of carbon nanotube transistors by Integrated Nano systems Research Facility,
CA 92697-2625, USA
P.J. Burke / Solid-State Electronics 48 (2004) 1981–1986. We also present
predictions of the effects parasitic capacitances on AC nanotube transistor
performance.

2. In this paper present kinetic inductance, and ballistic transport on the high-
frequency properties of nanotube transistors is analyzed. We discuss the
challenges of impedance matching for ac nano-electronics in general, and show
how integrated Nano systems Burke PJ. “An RF circuit model for carbon
nanotubes”. IEEE Transactions on Nanotechnology 2003:2(1):55–8.

3. Burke PJ. “Luttinger liquid theory as a model of the GHz electrical properties
of carbon

nanotubes” IEEE Transactions on Nanotechnology 2002:1(3):129–44.

4. that carbon Nano-electronics may be faster than conventional Si, SiGe, GaAs, or
InP semiconductor technologies Nauman Z. Butt, “Carbon-Nanotube Transistors
present by ” McEwen PL, Fuhrer M, Park H. “Single-walled carbon nanotube
electronics”. IEEE Transactions on Nanotechnology 2002;1(1):78-85;
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I We referred following content from Internet

1. Application of AC performance of Nano electronics.

2. Advantage and disadvantage of ac performance of Nano electronics.

3. Future scope of Nano electronics

CHAPTER 2

BALLISTIC TRANSPORT- AN OUTLINE

When carriers travel through a semiconductor material, they are likely to


be scattered by any number of possible sources, including acoustic and optical
phonons, ionized impurities, defects, inter faces, and other carriers. If, however,
the distance travelled by the carrier is smaller than the mean free path, it is likely
not to encounter any scattering events; it can, as a result, move ballistic ally
through the channel. To the first order, the existence of ballistic transport in a
MOSFET depends on the value of the characteristic scattering length (i.e. mean
free path) in relation to channel length of the transistor. This scattering length, l,
can be estimated from the measured carrier mobility

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Where t is the average scattering time, m* is the carrier effective mass, and vth
is the thermal velocity.

DEPENDENCE ON NORMAL ELECTRIC FIELD


In state-of-the-art MOSFET inversion layers, carrier scattering is dominated by
phonons, impurities (Coulomb interaction), and surface roughness scattering at
the Si-SiO2 interface. As shown in Figure2, the relative importance of each
scattering mechanism is dependent on the effective electric field component
normal to the conduction channel. At low fields, impurity scattering dominates
due to strong Coulomb interactions between the carriers and the impurity
canters. As the electric field is increased, acoustic phonons begin to dominate
the scattering process. At very high fields, carriers are pulled closer to the Si-
SiO2 gate oxide interface; thus,

surface roughness scattering degrades carrier mobility. A universal mobility


model has been developed to relate field strength with the effective carrier
mobility due to phonon and surface ro Where Vgs is the applied gate voltage,
VT is the transistor threshold voltage, Tox is the gate oxide thickness, and m0
and Ecrit are empirically-derived constants. As predicted by the International
Technology Roadmap for Semiconductors, device technologies at near ballistic
(~30nm) channel lengths will have power supplies of <0.8V, VT<0.2V,
Tox,eq~10Å. This yields an effective electric field of approximately ~1MV/cm.
The actual value may be lower, depending on the actual device structure and
operating conditions. With doping concentrations in the channel region of the
MOSFET expected to be on the order of 1018, from ,we find that the electron
mobility is ~230cm2/Vsec and the hole mobility is ~65 cm2/Vsec at room
temperature. This yields scattering lengths of approximately 5.5nm and 2.4nm.

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Inversion layer mobility is controlled by impurity

DEPENDENCE ON TEMPERATURE

When the temperature is changed, the relative importance of each of the


aforementioned scattering mechanisms is altered. Phonon scattering becomes
less important at very low temperatures. Impurity scattering, on the other hand,
becomes more significant because carriers are moving slower (thermal velocity
is decreased) and thus have more time to interact with impurity canters. Surface

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roughness scattering remains the same because it does not depend on


temperature. At liquid nitrogen temperatures (77K) and an effective electric field
of 1MV/cm, the electron and hole mobility are~700 cm2/Vsec and
~100cm2/Vsec, respectively. Using the above equations, the scattering lengths
are approximately 17nm and 3.6nm.These scattering lengths can be assumed to
be worst-case scenarios, as large operating voltages (1V) and aggressively
scaled gate oxides (10Å) are assumed. Thus, actual scattering lengths will likely
be larger than the calculated values. Further device design considerations in
maximizing this scattering length will be discussed in the last section of this
paper .Still, the values calculated above are certainly in the range of transistor
gate lengths currently being studied in advanced MOSFET research (<50nm).
Ballistic carrier transport should thus become increasingly important as
transistor channel lengths are further reduced in size. In addition, it should be
noted that the mean free path of holes is generally smaller than that of electrons.
Thus, it should be expected that ballistic transport in PMOS transistors is more
difficult to achieve, since current conduction occurs through hole transport.
Calculation of the mean scattering length, however, can only be regarded as a
first- order estimation of ballistic transport. To accurately determine the extent
of ballistic transport evident in a particular transistor structure, Monte Carlo
simulation methods must be employed

.Only by modelling the random trajectory of each carrier travelling through the
channel can we truly assess the extent of ballistic transport in a MOSFET.
Comparison of scattering length with the device channel length can
nevertheless provide a useful way of ascertaining whether ballistic transport
effects should be considered.

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EFFECTS OF BALLISTIC TRANSPORT IN MOSFET’S

If carrier transport in a device can be assumed to be completely ballistic,


analysis of MOSFET current voltage characteristics reduces to carrier
transmission over the channel potential barrier. As shown in figure 3, the
potential energy distribution in the channel of the transistor has a maximum,

E max , near the source end of the device. Carriers with a higher energy than E
max can be transmitted over the barrier through the process of thermionic
emission. Carriers with lower energies can travel from source to drain only by
tunneling quantum mechanically through the channel potential barrier. Such
transport phenomena is markedly different from that generally associated with
mobility-limited diffusive transport. As a result, the current-voltage
characteristics of MOSFET’s operating in the ballistic regime will be different.

Distribution along the channel of a MOSFET In ballistic transport

ACHIEVING BALLISTIC TRANSPORT IN DEEPLY-SCALED


MOSFET’S
As evidenced by preceding sections, ballistic transport allows for larger
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transistor saturation currents because carriers are experience no scattering.


Designing future transistors to maximize the likelihood of ballistic transport is
thus highly desirable. As shown, simply by shrinking current transistor designs,
a significant step can be taken towards this goal.

MOSFET designs (Figure 1.3) due to its superior immunity to detrimental short-
channel effects. This structure, in particular, lends itself to the promotion of
ballistic carrier transport due to its low-doped channel and dual-gate nature. The
following briefly describes some techniques that may be used in the design of
future transistor technologies to minimize carrier scattering, thus promoting
ballistic transport. The primary goal is to reduce the likelihood of scattering
events in the MOSFET inversion layer and increase the mean free path.
Minimizing surface roughness scattering Because of the large electric fields
experienced by carriers in MOSFET inversion layers, scattering is due
predominately to interface roughness. To minimize the impact of this scattering
mechanism, the problem can be attacked from two perspectives: improving the
Si- SiO2 interface quality, and decreasing the normal electric field. The former
will indeed reduce surface roughness scattering, but there is little room for
improvement as current semiconductor process technologies are quite mature
and yield very clean and smooth interfaces. Even so, it may be helpful to take
precautions during processing to ensure a good interface; this may include ion
implantation through a screen oxide, sacrificial oxidation steps to clean up
surfaces after reactive ion etching, or dry as opposed to wet oxidation
techniques. Decreasing the normal electric field is a more viable option. As
mentioned earlier, the normal electric field can be express

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Double gate MOSFET design the silicon body is on the order of 10nm

To decrease the normal electric field, either the power supply voltage (which
becomes the applied Vgs) must be scaled down or the oxide thickness must be
increased. Lowering of the power supply is already a widespread trend, mainly
due to power dissipation and device reliability concerns. However, this results
in a smaller inversion charge density and thus a smaller current. As such, a trade
off in current drive can be observed between minimization of carrier scattering
and the decrease in inversion charge. There is likely an optimum point for the
choice of supply voltage. Normally, gate oxide thickness is decreased in
advanced transistor technologies to combat short channel effects and to
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improve the ability to “turn off” the transistor. However, a thicker gate oxide
may allow for ballistic transport, which may decrease the effective field,
increase current, and result in an overall advantage. The double-gate MOSFET
structure (Figure 4) is particularly attractive for this option because two gate
electrodes exist to help to control channel conductivity, the gate oxide thickness
need not be as thin to achieve small gate lengths. Additionally, in the double-
gate MOSFET structure, because there are two gate electrodes on opposite sides
of the conduction channel, it is reasonable to assume that the two will have a
cancelling effect on the normal electric field component in the middle of the
silicon body . This should, in turn, reduce surface roughness scattering in the
inversion layer. If indeed the normal electric field component is reduced in
double-gate MOSFET’s, it may be much easier to achieve ballistic-mode
transport in these devices.

MINIMIZING PHONON SCATTERING


Phonons resulting from vibrations in the silicon lattice are principally
controlled by the ambient temperature. Decreasing the operating temperature of
a transistor reduces phonon scattering and increases the carrier transmission
coefficient and thus the likelihood of ballistic transport. Transmission
coefficients as high as 92% have been obtained at liquid nitrogen temperatures
(77K).However, low temperature operation

MINIMIZING IMPURITY SCATTERING


In order to alleviate the impact of impurity scattering, the doping
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concentration in the channel region needs to be low. In a standard transistor


design, because of concerns with the short- channel effect and threshold
voltage control, doping concentrations in the channel need to be very high
(~1018 cm-3). In order to decouple channel doping from these issues, super-
steep retrograde doping profiles or lightly doped epitaxial channel layers need to
be employed. The double-gate MOSFET structure described in Figure 4,
however, already considers the use of a low-doped channel region. Short-
channel effects are controlled using the dual-gate structure, while threshold
voltage is dictated by the work function of gate material. Thus, impurity
scattering can be minimized with this device structure. As previously mentioned,
in transistors operating near the ballistic regime, carrier scattering will likely
dominated by surface roughness mechanisms. Thus, addressing effective normal
electric field as well as Si-SiO2 interface quality will be of utmost concern in
achieving ballistic transport. Furthermore, additional device design issues will
have to be resolved before the full benefits of ballistic transport are realized.
Most importantly, parasitic resistances in the source and drain terminals of the
device due either to shallow source/drain junctions or the thin body region of
the double-gate device will b

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CHAPTER 3

CARBON NANOTUBES – AN OVERVIEW

The remarkable properties of SWNT (single wire nanotube) stems from


the unusual electronic structure of the two dimensional material graphene from
which they are constructed. Graphene is a single atomic layer of graphite
which consists of a 2D honey comb structure of sp² bonded carbon atoms.

Single wire nano tube


It is sometimes called zero band semiconductors since it is semiconducting in
some directions and metallic in the other directions. In a SWNT, the momentum
of the electrons moving around the circumference of the tube is quantized,
reducing the available states to slice through the 2-D band structure. This shown

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in fig 2.

the honey comb structure of grapheme

The CNTFET technology is at an early stage of development. The device


physics is relatively unexplored: it is not clear that how the device operates or
whether devices grown with different structures and techniques operate in the
same way. Most of the times, CNTFETs are categorized in three types as
shown in the figure 2.3

Three possible type of CNTFET

(a) P-channel depletion

(b) P-channel enhancement

(c) Barrier transistor


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DEPLETION MODE P-CNTFET


In this type, the nanotube is uniformly doped and the contacts at the two ends
are ohmic. In such a device, the on-current would be limited by the ‘source
exhaustion’ Id (on) = qplvt, where pl is the hole density per unit length.

MOSFET LIKE CNTFET

In this type of nanotube transistors, the conductance of channel is controlled


by the gate as in a MOSFET. This is supported by the fact that some long
channel CNTFETs Obeys the MOSFET square law theory and no am bipolar
behaviour is observed in these Devices. Some recent CNTFETs that behaves as
MOSFET like devices, have demonstrated performance that is many orders of
magnitude better than current state of-the-art MOSFETs.

SCHOTTY BARRIER CNTFETS

Another possibility is that the CNTFET operates as “Schottky barrier


transistors” in which transistor action takes place primarily by varying the
contact resistance rather than the channel conductance. This is supported by the
observations of am bipolar behaviour in some CNTFETs. The observation of am
bipolar operation in some CNTFETs and the transition of the tube from n- type
top-type indicate that some CNTFETs operate as unconventional Schottky
barrier transistors. In such a device, the gate modulates the transmission
through a Schottky barrier and the transistor action takes place primarily by
varying the contact resistance rather than the channel conductance. In
addition, the electrode geometry is crucial for good device performance.
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AMBIPOLAR BEHAVIOR

The CNTFETs measured in air are unipolar with p type characteristics, i.e. the
tube conducts holes upon applying negative gate voltages and they show no
evidence of electron conduction events very large gate voltages. The origin of
this p-type character of semiconducting SWNT is still not clearly understood.
Several proposals have been made to explain this effect including contact
doping, doping introduced by cleaning or handling the nanotube in oxidizing
acids, or doping by the adsorption of atmospheric oxygen. In principle any of
the above mechanism can influence the transistor characteristics. The device is
said to be am bipolar when it behaves like n-type or p-type depending on the
applied gate voltage i.e. it shows large conduction for both positive and negative
gate voltages

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CHAPTER 4

NANOTUBE INTERCONNECTS QUANTUM IMPEDANCES

The first step towards understanding the high frequency electronic properties
of carbon nanotubes is to understand the passive ac impedance of a 1d quantum
system. In the presence of a ground plane below the nanotube or top gate
above the nanotube, there is electrostatic capacitance between the nano tube and
the metal. Due to quantum properties of 1d systems there are two additional
components to the ac impedance: the quantum capacitance and the kinetic
inductance. Thus the equivalent circuit of a nanotube consists of 3 distributed
circuit elements as shown in fig 1and fig 3.1.

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Geometry for impedance calculation

Circuit dia gram for a Id nanowi re or Nano tube

ELECTROSTATIC CAPACITANCE

The electrostatic capacitance between a wire and a ground plane as shown


infig1 is given by where the approximation holds good to within 1% for h > 2d.
For a typical value if h/d, this wire length can be approximated numerically as

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QUANTUM CAPACITANCE
Because of the finite quantum energy level spacing of electrons in 1d, it costs
energy to add an electron to the system. By equating this energy cost ∆E with an
effective Quantum capacitance, one arrives at the following expression for
capacitance per unit length:

Where h is the Planck’s constant and νF is the Fermi velocity. The fermi velocity
for graphene and also carbon nano tubes is usually taken as νF = 8x 10ˆ5 m/s, so
that numerically,

KINETIC INDUCTANCE

Due to inertia of electrons, the instantaneous velocity lags the instantaneous


electric field in time. This means the current lags the phase, which can be
described as a kinetic inductance. For1d systems we have the following
expression for the kinetic energy per unit length:

CHAPTER 4

TIVE DEVICES AND EQUIVALENT CIRCUIT

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ACTIVE DEVICES: NANOTUBE TRANSISTORS

Atypical nanotube transistor geometry is shown below in fig4.1.

Typical nanotube transistor geometry

The fundamental physical mechanism responsible for transistor action in


nanotube Transistor action in Nano tube transistors is still not completely
understood. One action of the gate may be to modulate the (Schottky barrier)
contact resistance complicating the issue is the question whether the transport is
diffusive or ballistic Experiments indicate that the mean free path in semi
conducting nanotubes at room Temperature is at least 1µm, so that nano tubes
shorter than 1µm may behave as ballistic transistors.

In conclusion, we have presented phenomenological predictions for the ac


performance of nanotube transistors. Based on our calculations, we predict
carbon nanotube transistors may be faster than conventional semiconductor
technologies. There are many challenges that must be overcome to meet this
goal, which can be best be achieved by integration of nano systems.

SMALL SIGNAL EQUIVALENT CIRCUIT

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In fig 4.2, we show the predicted small signal circuit model for a nano tube
transistor

Proposed small-signal circuit model for a nanotube

GATE SOURCE CAPACITANCE

The gate source capacitance is given by

The quantum capacitance is multiplied by 4 because of the band structure


degeneracy

TRANSCONDUCTANCE
The Transconductance is the most critical parameter the underlying
mechanism is the least understood. Transconductance up to 20µS have been
measured using aqueous gate geometry. A Transconductance of 60µS was
recently predicted by simulation.

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DRAIN RESISTANCE

In Fig, gd represents the output impedance of the device, if it does not appear
as an ideal current source. The gd values from various source for nanotube
transistor are 0.03µS Tans S, Verschueren A, Dekker C 1 µS Martel R, Schmidt
T, Shea HR 0.6µS Burke P J

SERIES RESISTANCE

In most conventional transistors the series resistance consists of the


metallization layer and the ohmic contact resistance. We argue that, in nanotube
transistors, the intrinsic contact resistance will be of order the resistance
quantum because of the 1d Nature of the system. At dc, the lowest value of
resistance possible for a carbon nanotube is h/4e″. This is because there are
four channels for conductance in the Landauer-Buttiker formalism, each
contributing h/e″ to the conductance. To date very little experimental work has
been done to measure the ac impedance of ballistic systems. From a
theoretical point of view, Buttiker and Christen have carefully analysed the case
of a capacitive contact to a ballistic conductor (in his case a 2DEG without
scattering) in contact with one dc electrical lead through a quantum point
contact. They found that the ac impedance from gate to lead includes a real
part, equal to half the resistance quantum h/2e″. Since there are channels in
parallel this a contact resistance of h/8e″.There will be an additional imaginary
contribution to the contact resistance due to kinetic inductance on the order of a
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few Nh

PARASITIC CAPACITANCE
The parasitic capacitance is due to fringing electric fields between the
electrodes for the source, drain and gate. While these parasitic capacitance are
generally small, they may comparable to the intrinsic device capacitances and
hence must be considered. In order to estimate the order of magnitude of the
parasitic capacitance, we can use known calculations for the capacitance
between two thin metal films, spaced by a distance w, as drawn in Fig. 5. For
this geometry, if w is 1µm, the capacitance is ~ 10^-16 F/lm of electrode
length. For a length of 1µm, this gives rise to ~10^-16 F. Thus, typical parasitic
capacitances are of the same order of magnitude as typical intrinsic
capacitances.

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CHAPTER 5

LEVANT FREQUENCY AND CUTOFF FREQUENCY

RELEVANT FREQUENCY SCALES

The frequency scales for most important processes: the RC time and the Trans
conductance are estimated.

RC TIME

The most important effect for high frequency performance is the RC time. For
Typical Nanotube geometry of 0.1µm length, C is of order 4aF. R can be as
small as6.25kΩ.Thereforethe RC frequency is given by
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This shows that the speed limit due to RC times intrinsic to a nanotube transistor
very large indeed.

TRANSCONDUCTANCE

The Trans conductance gm over the gate source capacitance Cgs sets another
important Frequency.

Using experimentally measured value of 10µS, this gives

The above estimates indicate that a carbon nano tube transistor could be very
fast, in spite its high impedance. For more realistic estimates of device
performance a small signal equivalent circuit is considered

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CUTOFF FREQUENCY

The estimates of the cut off frequency fT, defined as the frequency at which
the current gain falls to unity are provided in this section. Based on fig 4, fT is
given by

Here p represent parasitic, Using the experimentally measured transconductance


of 10µs, a parasitic capacitance value of 10^-16 F, and a Cgs of4 x 10^-17 F
(appropriate for a 1 lm long tube), we predict a cut off frequency of 8 GHz. For
this value, the parasitic capacitance is the most important contribution. Thus,
minimizing the parasitic capacitance is of prime importance in increasing fT for
nanotube transistors.

SCALING WITH LENGTH


If we assume that the parasitic capacitance can be reduced to negligible Values,
the equation simplifies to

Cgs scales linearly with gate length, and was calculated above. In the ballistic
limit, gm should be independent of gate length. Using the largest measured
trans conductance to date of20µs, this gives rise to the following prediction for
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fT

CHAPTER 6

BEYOND MICROELECTRONICS

Nano electronics is not simply a smaller version of microelectronics; things


change at the nano scale. At the device level, silicon transistors may give way to
new materials such as organic molecules or inorganic nano wires. At the
interconnect level, microelectronics uses long, fat wires, but nano electronics
seeks to use short nano wires. Finally, fundamentally new architectures will be
needed to make use of simple, locally connected structures that are imperfect
and are comprised of devices whose performance varies widely. I have argued in
this paper that 21st century silicon technology is rapidly evolving into a true
nanotechnology. Critical dimensions are already below100 nm. The materials
used in these silicon devices have properties that differ from the bulk. Nano
scale silicon transistors have higher leakage, lower-drive current, and exhibit
more variability from device to device. New circuits and architectures will need
to be developed to accommodate such devices. It matters little whether the
material is silicon or something else, the same issues face any nano electronics
technology. It’s likely that many of the advances and breakthroughs at the
circuits and systems levels that will be needed to make nano electronics
successful will come from the silicon design community. Given that we have a
nano electronics technology and that another 20years of exponential progress in
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silicon technology can be expected (leading to terascale integration, why explore


radically new technologies? One reason, of course, is that 20 years is not a
long time to develop fundamentally new technologies, so that we need to start
now, but there are other reasons. The most compelling practical reason is that
the fabrication and assembly processes and the materials, device, circuit, and
system understanding that we develop by examining radically new technologies
are almost certain to be useful in silicon nanotechnology. Developing an
understanding of how to engineer devices at the nano scale is a good reason to
support nano science research. Another reason is that devices to complement
silicon technology might be discovered. For example, carbon nanotube FETs
could be exquisite single molecule detectors, and single electron device should
be integrated with MOSFETs for high density memory applications. Another
possibility is molecular structures that improve the performance of a CMOS
platform. For example, ballistic CNTs could be high performance interconnects
and efficient at heat removal. Nano wire thermos electric cooling could lower
chip temperature and increase performance. So there are several good reasons to
expect that research on nano electronics will prove to be a good investment. The
successful development of nano electronics will require a partnership between
science and engineering. It was the same for semiconductor technology. The
scientific community developed the understanding of semiconductor materials
and physics and the engineering community used this base to learn how to
design devices, circuits, and systems. Figure 5 summarizes this partnership.
Science works in the nano world with individual atoms, molecules, nano scale
structures and devices, and assembly processes. Systems engineers work in the
macro world on complex systems with tera scale device densities. In the
middle are the device and circuit engineers. They must learn to think and work
at the nano scale to build devices and circuits that can connect to the macro
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world. Their job is to hide the complexity of the nano scale device by packaging
it in a form that systems engineers can use (e.g. a compact circuit model). To
turn the promise of nano science into practical technologies, it is essential that
the systems engineering community be

Fig.6.1: Science engineering and Nano electronics

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CHAPTER 7
CONCLUSION
In conclusion, we have presented phenomenological predictions for the ac
performance of nanotube transistors. Based on our calculations, we predict
carbon nanotube transistors may be faster than conventional semiconductor
technologies. There are many challenges that must be overcome to meet this
goal, which can be best be achieved by integration of nano systems. Modelling
and predictions for nano electronics as interconnects, transistors, and antennas.
It is clear that nano-electronic devices can full fill all three roles, with
outstanding predicted performance. Then we can predict carbon nanotube
transistor may be faster than conventional semiconductor technologies. There
are many challenges that must be overcome to meet this goal, which can be best
be achieved by integration of nano systems. Future work remains to be done
on understanding non-linear- nano-electronic devices for applications such as
mixers and detectors.

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CHAPTER 8
REFERENCES
Burke PJ. An RF circuit model for carbon nanotubes. IEEE Trans
Nanotechnology

P.J. Burke – Carbon nano electronics technology

1. www.cientifica.com
2. Burke PJ. Luttinger liquid theory as a model of the GHz
electrical properties of carbon nanotubes. IEEE Trans Nanotechnology
2002;1(3):129–44.

3. Burke PJ. An RF circuit model for carbon nanotubes. IEEE


Trans Nanotechnology 2003; 2(1):55–8.
4. Ramo S, Whinnery JR, Van Duzer T. Fields and waves in
communications electronics. New York: Wiley; 1994.
5. Li S, Yu Z, Gadde G, Burke PJ, Tang WC. Carbon nanotube
growth for GHz devices. In: Proc 3rd IEEE Conf Nanotechnology, 2003.
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6. Li S, Yu Z, Yen S-F, Tang WC, Burke PJ. Carbon nanotube


transistor operation at 2.6 GHz. Nano Lett, in press.

Avouris Ph, Dresselhaus MS, Dresselhaus G, editors. Carbon Nanotubes:


Synthesis, Structure, Properties, and Applications. Topics in Applied Phys

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