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CHAPTER 1
INTRODUCTION
The phenomenological predictions for the cut off frequency of carbon
nanotube transistors and the predictions of the effects of parasitic capacitances
on AC nanotube transistor performance are presented. The influence of
quantum capacitance, kinetic inductance, and ballistic transport on the high-
frequency properties of nanotube transistors is analyzed. The challenges of
impedance matching for ac Nano-electronics in general, and how integrated
Nano systems can solve this challenge, are presented Nano electronic devices
fall into two classes: tunnel devices and ballistic transport devices. In Tunnel
devices single electron effects occur if the tunnel resistance is larger than h/e″ =
25 KΩ. In Ballistic devices with cross sectional dimensions in the range of
quantum mechanical wavelength of electrons, the resistance is of order h/e″ = 25
KΩ .This high resistance may seem to restrict the operational speed of nano
electronics in general. However the capacitance values and drain source spacing
are typically small which gives rise to very small RC times and transit times of
order of ps or less. Thus the speed may be very large, up to THz range.
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LITERATURE SURVEY
I. we referred following paper for writing this seminar report.
2. In this paper present kinetic inductance, and ballistic transport on the high-
frequency properties of nanotube transistors is analyzed. We discuss the
challenges of impedance matching for ac nano-electronics in general, and show
how integrated Nano systems Burke PJ. “An RF circuit model for carbon
nanotubes”. IEEE Transactions on Nanotechnology 2003:2(1):55–8.
3. Burke PJ. “Luttinger liquid theory as a model of the GHz electrical properties
of carbon
4. that carbon Nano-electronics may be faster than conventional Si, SiGe, GaAs, or
InP semiconductor technologies Nauman Z. Butt, “Carbon-Nanotube Transistors
present by ” McEwen PL, Fuhrer M, Park H. “Single-walled carbon nanotube
electronics”. IEEE Transactions on Nanotechnology 2002;1(1):78-85;
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CHAPTER 2
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Where t is the average scattering time, m* is the carrier effective mass, and vth
is the thermal velocity.
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DEPENDENCE ON TEMPERATURE
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.Only by modelling the random trajectory of each carrier travelling through the
channel can we truly assess the extent of ballistic transport in a MOSFET.
Comparison of scattering length with the device channel length can
nevertheless provide a useful way of ascertaining whether ballistic transport
effects should be considered.
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E max , near the source end of the device. Carriers with a higher energy than E
max can be transmitted over the barrier through the process of thermionic
emission. Carriers with lower energies can travel from source to drain only by
tunneling quantum mechanically through the channel potential barrier. Such
transport phenomena is markedly different from that generally associated with
mobility-limited diffusive transport. As a result, the current-voltage
characteristics of MOSFET’s operating in the ballistic regime will be different.
MOSFET designs (Figure 1.3) due to its superior immunity to detrimental short-
channel effects. This structure, in particular, lends itself to the promotion of
ballistic carrier transport due to its low-doped channel and dual-gate nature. The
following briefly describes some techniques that may be used in the design of
future transistor technologies to minimize carrier scattering, thus promoting
ballistic transport. The primary goal is to reduce the likelihood of scattering
events in the MOSFET inversion layer and increase the mean free path.
Minimizing surface roughness scattering Because of the large electric fields
experienced by carriers in MOSFET inversion layers, scattering is due
predominately to interface roughness. To minimize the impact of this scattering
mechanism, the problem can be attacked from two perspectives: improving the
Si- SiO2 interface quality, and decreasing the normal electric field. The former
will indeed reduce surface roughness scattering, but there is little room for
improvement as current semiconductor process technologies are quite mature
and yield very clean and smooth interfaces. Even so, it may be helpful to take
precautions during processing to ensure a good interface; this may include ion
implantation through a screen oxide, sacrificial oxidation steps to clean up
surfaces after reactive ion etching, or dry as opposed to wet oxidation
techniques. Decreasing the normal electric field is a more viable option. As
mentioned earlier, the normal electric field can be express
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Double gate MOSFET design the silicon body is on the order of 10nm
To decrease the normal electric field, either the power supply voltage (which
becomes the applied Vgs) must be scaled down or the oxide thickness must be
increased. Lowering of the power supply is already a widespread trend, mainly
due to power dissipation and device reliability concerns. However, this results
in a smaller inversion charge density and thus a smaller current. As such, a trade
off in current drive can be observed between minimization of carrier scattering
and the decrease in inversion charge. There is likely an optimum point for the
choice of supply voltage. Normally, gate oxide thickness is decreased in
advanced transistor technologies to combat short channel effects and to
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improve the ability to “turn off” the transistor. However, a thicker gate oxide
may allow for ballistic transport, which may decrease the effective field,
increase current, and result in an overall advantage. The double-gate MOSFET
structure (Figure 4) is particularly attractive for this option because two gate
electrodes exist to help to control channel conductivity, the gate oxide thickness
need not be as thin to achieve small gate lengths. Additionally, in the double-
gate MOSFET structure, because there are two gate electrodes on opposite sides
of the conduction channel, it is reasonable to assume that the two will have a
cancelling effect on the normal electric field component in the middle of the
silicon body . This should, in turn, reduce surface roughness scattering in the
inversion layer. If indeed the normal electric field component is reduced in
double-gate MOSFET’s, it may be much easier to achieve ballistic-mode
transport in these devices.
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CHAPTER 3
in fig 2.
AMBIPOLAR BEHAVIOR
The CNTFETs measured in air are unipolar with p type characteristics, i.e. the
tube conducts holes upon applying negative gate voltages and they show no
evidence of electron conduction events very large gate voltages. The origin of
this p-type character of semiconducting SWNT is still not clearly understood.
Several proposals have been made to explain this effect including contact
doping, doping introduced by cleaning or handling the nanotube in oxidizing
acids, or doping by the adsorption of atmospheric oxygen. In principle any of
the above mechanism can influence the transistor characteristics. The device is
said to be am bipolar when it behaves like n-type or p-type depending on the
applied gate voltage i.e. it shows large conduction for both positive and negative
gate voltages
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CHAPTER 4
The first step towards understanding the high frequency electronic properties
of carbon nanotubes is to understand the passive ac impedance of a 1d quantum
system. In the presence of a ground plane below the nanotube or top gate
above the nanotube, there is electrostatic capacitance between the nano tube and
the metal. Due to quantum properties of 1d systems there are two additional
components to the ac impedance: the quantum capacitance and the kinetic
inductance. Thus the equivalent circuit of a nanotube consists of 3 distributed
circuit elements as shown in fig 1and fig 3.1.
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ELECTROSTATIC CAPACITANCE
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QUANTUM CAPACITANCE
Because of the finite quantum energy level spacing of electrons in 1d, it costs
energy to add an electron to the system. By equating this energy cost ∆E with an
effective Quantum capacitance, one arrives at the following expression for
capacitance per unit length:
Where h is the Planck’s constant and νF is the Fermi velocity. The fermi velocity
for graphene and also carbon nano tubes is usually taken as νF = 8x 10ˆ5 m/s, so
that numerically,
KINETIC INDUCTANCE
CHAPTER 4
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In fig 4.2, we show the predicted small signal circuit model for a nano tube
transistor
TRANSCONDUCTANCE
The Transconductance is the most critical parameter the underlying
mechanism is the least understood. Transconductance up to 20µS have been
measured using aqueous gate geometry. A Transconductance of 60µS was
recently predicted by simulation.
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DRAIN RESISTANCE
In Fig, gd represents the output impedance of the device, if it does not appear
as an ideal current source. The gd values from various source for nanotube
transistor are 0.03µS Tans S, Verschueren A, Dekker C 1 µS Martel R, Schmidt
T, Shea HR 0.6µS Burke P J
SERIES RESISTANCE
few Nh
PARASITIC CAPACITANCE
The parasitic capacitance is due to fringing electric fields between the
electrodes for the source, drain and gate. While these parasitic capacitance are
generally small, they may comparable to the intrinsic device capacitances and
hence must be considered. In order to estimate the order of magnitude of the
parasitic capacitance, we can use known calculations for the capacitance
between two thin metal films, spaced by a distance w, as drawn in Fig. 5. For
this geometry, if w is 1µm, the capacitance is ~ 10^-16 F/lm of electrode
length. For a length of 1µm, this gives rise to ~10^-16 F. Thus, typical parasitic
capacitances are of the same order of magnitude as typical intrinsic
capacitances.
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CHAPTER 5
The frequency scales for most important processes: the RC time and the Trans
conductance are estimated.
RC TIME
The most important effect for high frequency performance is the RC time. For
Typical Nanotube geometry of 0.1µm length, C is of order 4aF. R can be as
small as6.25kΩ.Thereforethe RC frequency is given by
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This shows that the speed limit due to RC times intrinsic to a nanotube transistor
very large indeed.
TRANSCONDUCTANCE
The Trans conductance gm over the gate source capacitance Cgs sets another
important Frequency.
The above estimates indicate that a carbon nano tube transistor could be very
fast, in spite its high impedance. For more realistic estimates of device
performance a small signal equivalent circuit is considered
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CUTOFF FREQUENCY
The estimates of the cut off frequency fT, defined as the frequency at which
the current gain falls to unity are provided in this section. Based on fig 4, fT is
given by
Cgs scales linearly with gate length, and was calculated above. In the ballistic
limit, gm should be independent of gate length. Using the largest measured
trans conductance to date of20µs, this gives rise to the following prediction for
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fT
CHAPTER 6
BEYOND MICROELECTRONICS
world. Their job is to hide the complexity of the nano scale device by packaging
it in a form that systems engineers can use (e.g. a compact circuit model). To
turn the promise of nano science into practical technologies, it is essential that
the systems engineering community be
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CHAPTER 7
CONCLUSION
In conclusion, we have presented phenomenological predictions for the ac
performance of nanotube transistors. Based on our calculations, we predict
carbon nanotube transistors may be faster than conventional semiconductor
technologies. There are many challenges that must be overcome to meet this
goal, which can be best be achieved by integration of nano systems. Modelling
and predictions for nano electronics as interconnects, transistors, and antennas.
It is clear that nano-electronic devices can full fill all three roles, with
outstanding predicted performance. Then we can predict carbon nanotube
transistor may be faster than conventional semiconductor technologies. There
are many challenges that must be overcome to meet this goal, which can be best
be achieved by integration of nano systems. Future work remains to be done
on understanding non-linear- nano-electronic devices for applications such as
mixers and detectors.
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CHAPTER 8
REFERENCES
Burke PJ. An RF circuit model for carbon nanotubes. IEEE Trans
Nanotechnology
1. www.cientifica.com
2. Burke PJ. Luttinger liquid theory as a model of the GHz
electrical properties of carbon nanotubes. IEEE Trans Nanotechnology
2002;1(3):129–44.
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