Module-3

Dr B Lakshmi
SENSE
 Instruction Cycle
• Fetch
– Read the next instruction from memory into the
processor
• Execute
– Interpret the op code and perform the indicated
operation
• Interrupt
– If interrupts are enabled and an interrupt has
occurred, save the current process state and
service the interrupt
 Indirect Cycle
• May require memory access to fetch operands
• Indirect addressing requires more memory
accesses
• Can be thought of as additional instruction
sub cycle
Instruction Cycle with Indirect
Instruction Cycle State Diagram
 Data Flow (Instruction Fetch)
• Depends on CPU design
• In general:

• Fetch
– PC contains address of next instruction
– Address moved to MAR
– Address placed on address bus
– Control unit requests memory read
– Result placed on data bus, copied to MBR, then to IR
– Meanwhile PC incremented by 1
 Data Flow (Data Fetch)
• IR is examined
• If indirect addressing, indirect cycle is
performed
– Right most N bits of MBR transferred to MAR
– Control unit requests memory read
– Result (address of operand) moved to MBR
Data Flow (Fetch Diagram)
Data Flow (Indirect Diagram)
 Data Flow (Execute)
• May take many forms
• Depends on instruction being executed
• May include
– Memory read/write
– Input/Output
– Register transfers
– ALU operations
 Data Flow (Interrupt)

• Simple
• Predictable
• Current PC saved to allow resumption after interrupt
• Contents of PC copied to MBR
• Special memory location (e.g. stack pointer) loaded to
MAR
• MBR written to memory
• PC loaded with address of interrupt handling routine
• Next instruction (first of interrupt handler) can be
fetched
Data Flow (Interrupt Diagram)
 Major Advances in Computers(1)
• The family concept
– IBM System/360 1964
– DEC PDP-8
– Separates architecture from implementation
• Microporgrammed control unit
– Idea by Wilkes 1951
– Produced by IBM S/360 1964
• Cache memory
– IBM S/360 model 85 1969
 Major Advances in Computers(2)
• Solid State RAM
• Microprocessors
– Intel 4004 1971
• Pipelining
– Introduces parallelism into fetch execute cycle
• Multiple processors
 The Next Step - RISC
• Reduced Instruction Set Computer

• Key features
– Large number of general purpose registers
– Use of compiler technology to optimize register
use
– Limited and simple instruction set
– Emphasis on optimising the instruction pipeline
Comparison of processors
 Driving force for CISC
• Software costs far exceed hardware costs
• Increasingly complex high level languages
• Leads to:
– Large instruction sets
– More addressing modes
– Hardware implementations of HLL statements
 Intention of CISC
• Ease compiler writing
• Improve execution efficiency
– Complex operations in microcode
• Support more complex HLLs
 RISC Characteristics
• One instruction per cycle
• Register to register operations
• Few, simple addressing modes
• Few, simple instruction formats
• Hardwired design (no microcode)
• Fixed instruction format
• More compile time/effort
 RISC Pipelining
• Most instructions are register to register
• Two phases of execution
– I: Instruction fetch
– E: Execute
• ALU operation with register input and output
• For load and store
– I: Instruction fetch
– E: Execute
• Calculate memory address
– D: Memory
• Register to memory or memory to register operation
Effects of Pipelining
 Addressing Modes
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack
 Immediate Addressing
Instruction

Opcode Operand
 Immediate Addressing
• Operand is part of instruction
• Operand = address field
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
 Direct Addressing
Instruction

Opcode Address A
Memory

Operand
 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective
address
• Limited address space
 Indirect Addressing
Instruction

Opcode Address A
Memory

Pointer to operand

Operand
 Indirect Addressing (1)
• Memory cell pointed to by address field
contains the address of (pointer to) the
operand
• EA = (A)
– Look in A, find address (A) and look there for
operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
accumulator
 Indirect Addressing (2)
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Multiple memory accesses to find operand
• Hence slower
 Register Addressing
Instruction

Opcode Register Address R

Registers

Operand
 Register Addressing (1)
• Operand is held in register named in address
field
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
 Register Addressing (2)
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
– Requires good assembly programming or compiler
writing
Register Indirect Addressing
Instruction

Opcode Register Address R

Memory

Registers

Pointer to Operand Operand

 Register Indirect Addressing
• EA = (R)
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing
 Displacement Addressing
Instruction

Opcode Register R Address A

Memory

Registers

Pointer to Operand + Operand

 Displacement Addressing
• EA = A + (R)
• Address field hold two values
– A = base value
– R = register that holds displacement
– or vice versa
 Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = A + (PC)
• i.e. get operand from A cells from current
location pointed to by PC
 Base-Register Addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86
 Indexed Addressing
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
– EA = A + R
– R++
Stack Addressing
 Stack Addressing
• Operand is (implicitly) on top of stack
• e.g.
– ADD Pop top two items from stack
and add
Addressing modes
Y=A-B/C+(D*E)
Single bus organization of the data
path
Control Unit with Decoded Inputs
 Control Unit Logic
P and Q are the control signals
 Micro programmed Control
• Control signals are generated by a program
similar to machine language programs
• A sequence of control words (CW)
corresponding to the control sequence of a
machine instruction constitutes the micro
routine
• Micro routines are stored in a special memory
called control store
• Individual control words in this routine are
referred as microinstructions
Organization of micro programmed
control unit
Control Unit microarchitecture
Functioning of Microprogrammed
Control Unit
I/O gating for the registers
Connection and control signals for
MDR
Read operation Move (R1), R2
Execution of complete instruction
Add (R3),R1
Control sequence
Micro instructions