TECHNICAL QUESTIONS

1. IR drop

2. Esd

3. Antenna Effect

4. Matching

5. Triple well

6. Electro migration

7. Latch up

8. Difference between 180nm, 90nm, 65nm and 45nm layouts

9. Shielding

10. Well proximity effect (WPE)

11. Length of diffusion effect (LOD)

1. What is standard cell?

2. What are 7 tracks in STD cell? How will you calculate the height of the std cell?

3. What is the difference between 7 track and 12 track library?

4. Is it possible to make from 12 tracks to 9 track library or visa-versa? What are the issues while
doing this?

5. Draw the NAND and NOR gates?

6. Draw the stick diagram for the NAND and NOR gates?

7. Draw any NAND or NOR layout?

8. What is the difference between lower and higher technology? How will you take care about that?

9. What is scripting? Do you know any other script other than SKILL scripting?

10. What is DFM? How OPC related to DFM?

11. What is pin accessibility? How will you draw the layout if there are more pins?
12. What are the main consideration which has to be take care to start the layout?

13. What is abutment checking? What are the types to check this abutment?

14. What is Electro migration? How it will be taken care in a STD cell layout?

15. What are the types of STD cell libraries? What is the difference between HVT and LVT std cells
apart from the layer?

16. How will you migrate the 90nm STD cell library to 65nm std cell library?

17. How will you draw the good layout? Or what are the main steps to do the better layout?

18. How many STD layout and flops can draw per day?

19. In a flop how will consider clock signals? How will you start initial step to start the layout?

20. What are the other checks you will do for a STD cell layout apart from DRC and LVS?

21. What is LEF? How you will create abstract views?

22. What is PNR? What are the uses of PNR?

23. Why exactly the tracks are for in standard cells?

24. What will you do in the layout if you want to increase the drive in?

25. How will you fix the width of the active if the fingers of transistor are not given?

26. Main differences between analog and digital layouts?

27. What are the things needed to start a standard cell layout?

28. What is the difference between abutment checking and boundary checking?

29. How will you proceed with the layout if the DFM is not given to you?

30. Tell me about the metal usage in standard cell?

Analog & IO :( INTEL) 13/02/2012

1. As technology shrinks what are the issues will u see?

2. What is Latch up?

3. Tell me IO architecture (placement of devices)?

4. How power structure in IO?

5. What is Triple well? Why do we have it?

6. Tell me the fabrication process?

7. What is antenna effect? How will u avoid that?

8. What is ESD? What are the test models?

9. How ESD can occurs b/w two pads?

10.What is interdigitization & commoncentroid? Tell difference b/w

these two?

11.Well proximity issue means what?

1. What is standard cell?
Height is fixed and width varies according to the input gates.

2. What are 7 tracks in STD cell? How will you calculate the height of the
std cell?
Take seven horizontal metal lines for routing,

M1M1

In the above figure we are taking seven similar horizontal metal lines of
minimum width 0.45um and spacing b/w the metal line is 0.5um.
Cell height is calculated as follows:
Cell height = (no of tracks * minimum width of metal line) + (no of tracks –
1) * spacing b/w metal lines i.e.
Cell height = (7*0.45) + (6*0.5) =6.15um.

3. What is the difference between 7 track and 12 track library?

7 Tracks 12 Tracks
1.Less space More space
 2.Compact It is bulk
3.bad performance Good performance
4.Less metal lines so pin accessibility Pin accessibility is easy
is critical
5.Switching speed is slow Switching speed is fast

4. Is it possible to make from 12 tracks to 9 track library or visa-versa? What

are the issues while doing this?
Yes. The issues while doing this are:
 In 7 tracks pin accessibility is very critical compared to 12 tracks.
 Area is less in 7 tracks.
 Routing is complex.
 Switching speed slow in 7 tracks compared to 12 tracks.

5. What is the difference between lower and higher technology? How will
you take care about that?

 In lower technology we will face poly pitch issues; poly has to be placed
on pitch.
 ACLV:Across Chip Line Width Variability
 Power dissipation is more in lower technology
 Compact area in lower technology
 More DRC rules to be followed

6. What is DFM? How OPC related to DFM?

DFM-Design for Manufacturing is provided by customer which contains

some rules for critical blocks

OPC-Optical Proximity Correction. There is one layer in DFM in order to

protect the device from fabrication disorders.

7. What is pin accessibility? How will you draw the layout if there are more
pins?
 Pin accessibility means pin placement.

 First we will place pins where horizontal and vertical grids will co-inside
because due to the PNR tool. This tool will connect the pins in the next
level only if the pins are present at the co-incident point otherwise it will
not recognise that pin.
 Size of a pin must be size of one via. It is helpful for PNR.

8. What is the main consideration which has to be take care to start the
layout?

The main consideration which has to be taken care to start the layout

 Area
 Stick diagram
 Tracks
 DFM
 Pin accessibility
 Manufacturability
 Parasitic effects

9. What is abutment checking? What are the types to check this abutment?

Abutment checking means checking the corners of the standard cells.

Abutment checking can be done using three ways:

1. Take randomly the cells from library and place in a layout view in side
by side and run DRC for that.
2. Take all the cells in library place in horizontal and run DRC
3. By using scripting

10. What are the types of STD cell libraries? What is the difference
between HVT and LVT STD cells apart from the layer?

Types of standard cells are:

1. PMK ( Power Management Kit )
2. HVT (High Voltage )
3. LVT (Low Voltage )
4. High speed

HVT cells are MOS devices with less leakage due to high voltage but they have
higher delay than low voltage where as LVT cells are devices that have less
delay but leakage is high.

11. How will you migrate the 90nm STD cell library to 65nm STD cell library?

Use scripting language or manually or porting

12. How many STD layout and flops can draw per day?

STD layout-5 to 6 and Flops-1 to 2

13. What are the other checks you will do for a STD cell layout apart from DRC
and LVS?

1. Abutment checking
2. Boundary Checking
3. DFM Checks

14. What is LEF? How you will create abstract views?

LEF-Library Exchange Format is an ASCII data format from cadence design

Inc, to describe a standard cell library. It includes the design rules for routing
and the abstract layout of the cells.
LEF file contains the following:

1. Technology:layer,design rule,via-definition,little capacitance

2. Site: site extension
3. Macros: cell descriptions, layout of pins and blockages, capacitance

15. What is PNR? What are the uses of PNR?

PNR-Place and Route.

 Use: Automatic placement and routing

16. Why exactly the tracks are for in standard cells?

1. For routing purpose (it is useful for next level i.e., PNR).

2. It will fix the height of the cell.

17. What will you do in the layout if you want to increase the drive in?

By increasing the no of fingers we can increase the drive in.

18. How will you fix the width of the active if the fingers of transistor are not
given?

By using the below formula the width of the active can be fixed when
finger is not given

No of finger = Total width of the MOS

Max width of the MOS in standard cell

19. Main differences between analog and digital layouts?

Analog Layout Digital Layout

1.Main constraints are area and
matching
2. When you do some signal analog
layout the matching and shielding
Main constraints are clock signals,
data signals, control signals to reduce
the skew problem
In the layout of digital transistor the
speed, the low driving capability and
 should be considered and when you
do some power analog layout the
safe of the device should be
considered.
3.While doing analog layout design
is a art which is more dependent on
designers experience
4.Matching,accurate aspect
ratio(W/L),noise are very important
5.Area consumption is more
5. Here we need both fast switching
speed and high power at high
frequency. So analog design is
difficult when compared to digital
design.
the area optimizations are the key
issues.
Many tools can help while doing
some digital layout
Matching, accurate aspect
ratio(W/L),noise are not very
important
Area consumption is less
Here we need faster switching speed
so sacrifices the power

20. What is the difference between abutment checking and boundary

checking?

Abutment checking is done with many cells taken in a line.

Boundary checking: Here we check the boundary of an individual cell.

21. How will you proceed with the layout if the DFM is not given to you?

Draw a simple inverter layout check DRC & LVS of that layout

22. Tell me about the metal usage in standard cell?

In standard cell layout routing we are using only one metal hence the metal
usage is more. While doing power routing we have to maintain the same
metal width for all standard cells.
IR DROP:

IR drop is a signal integrity effect caused by wire resistance and current

drawn off from the power and ground grids.

V=IR. [Note: Signal integrity or SI is a set of measures of the quality of an

Electrical signal]

 If wire resistance is too high or cell current larger than predicted, an

unacceptable voltage drop may occur.

 Nanometer technology designs are extremely susceptible to IR drop

because power and ground resistivity increases with decreasing
geometries, while the overall power supply voltage decreases. This
results in poor performance and increased noise susceptibility.
  Due to IR drop gates with different voltage levels communicating with
each other across the chip can propagates erroneous data, causing a
malfunction.

Ways to overcome the IR drop issue:

 Increase the Width of the power stripe: This will help in decreasing
the resistance in the path and hence no voltage drop. (But this will
reduce the routing resource in the design. Apply this option only if
you have enough routing resource.)
 Proper power planning: Ensure uniform power distribution throughout
the chip area is key to have minimum IR drop in the design.(provide
reasonable number of horizontal as well as vertical power strips with
appropriate width)
 Add more number of vias it will decreases the resistance of the strip.

TRIPLE WELL:

 The twin (dual) well process includes both n-wells and p-wells built on a
lightly doped substrate that is either p-type or n-type.

 There is yet a third process, called the triple well process. The triple-well
technology comprises a buried n-well layer that isolates the p-well from
the p-substrate.
 Why we need that buried n-well (deep n-well) layer?

 Substrate noise coupling has been a serious problem in analog RF and

mixed signal circuits. The deep n-well in the triple well technology
isolates the p-substrate from the p-well, thus reducing substrate noise
coupling.
 Triple well process also reduces the cross talks in analog circuits.
 In digital CMOS, triple well technology enables low threshold voltage
NMOS transistors to improve circuit speed.
 Triple well structure is more immune to’ Latch up’ than dual well
structure when electrons are injected by n+ diffusion in the p-well.
ELECTROMIGRATION :( EM)

 EM is the gradual displacement of metal atoms in a semiconductor

material.

 It occurs when the current density is sufficiently high to cause the

drift of metal ions in the direction of the electron flow.

 This drifted metal ions may creates voids or hillocks in metal.

 If a void created in metal cause an open in the metal line.

  A hillock leading to a short to the adjacent or overhead metal runs.

Way to avoid EM:

 Increase the width of the metal it will avoids the EM.

 By providing redundant vias we can avoid EM.

WELL PROXIMITY EFFECT:

The MOSFETs fabrication process, which mainly consists of MOSFET

wells, shallow trench isolation (STI), and MOSFET gate formations.

During implants of the n-type transistors, the p-type transistors are covered
by photo resist and vice-versa. When a transistor is located near the edge of
the photo resist, the high-energy ions can scatter from the photo resist edge
and introduce extra doping atoms in the silicon near the well edge. Due to
this phenomenon, the threshold voltage of the transistor can vary depending
on the location and shape of adjacent wells. As the MOSFET gate
approaches the well edge, the doping concentration of the MOSFETS core
area will increase, causing an increase in the threshold voltage. This effect is
called as well proximity effect.
WPE can be avoiding by using the following ways.

 Keep more spacing b/w devices and wells.

 Add dummy devices in the corners of n well.

ANTENNA EFFECT:

During the process of plasma etching, charges accumulate along the metal
strips. The longer the strips are, the more charges are accumulated. IF a
small transistor gate connected to these long metal strips, the gate oxide can
be destroyed. This is called as Antenna Effect.

[Note: plasma etching is type Dry etching] plasma- partially ionized gas
containing an equal number of positive and negative charges, as well as
some other number of none ionized gas particles.

Dry Etching - Substrates are immersed in a reactive gas (plasma). The layer
to be etched is removed by chemical reactions and/or physical means (ion
bombardment). The reaction products must be volatile and are carried away
in the gas stream.

Way to avoid Antenna Effect:

 By making jogging the metal line, which is at least one metal above
the layer to be protected. If we want to remove antenna violation in
metal2 then need to jog it in metal3 not in metal1.( The reason being
while we are etching metal2, metal3 layer is not laid out. So the two
pieces of metal2 got disconnected. Only the piece of metal connected
to gate has charge to gate. When we laydown metal3, the remaining
portion of metal got charge added to metal3).

 Another way of preventing is adding reverse Diodes at the gates.

LOD (Length of Oxide Definition) Effect:

 Local Oxidation of Silicon (LOCOS) has been the standard device

isolation scheme of CMOS technologies.

 While going lower technologies Due to shrinking issues further

Device isolation with LOCOS is no longer practical and an
alternative form of isolation was developed (i, e. STI).
  STI (shallow Trench Isolation): Shallow Trench Isolation is the
device isolation scheme for modern CMOS technologies below
0.25μm.

 STI allows further shrinking, higher device density, flatter surface

topology and has less perimeter sidewall capacitance than LOCOS.

 STI applies mechanical stress to the MOS transistor diffusion. This

effect known as Length of Oxide Definition (LOD) stress effect. It
influences the electrical characteristics of a MOS transistor; it impacts
mobility (μeff), carrier saturation velocity (Vsat), threshold voltage
(Vth) and other second order effects. [LOD=Sa+Sb+L] ‘Sa’ should be
equal to ‘Sb’.

Ways to Reduce the LOD Effect:

 Add dummy devices in the corners of active devices.

 Try to reduce the device fingering.

ESD (Electro Static discharge):

 ESD is one of the most important reliability problems in the integrated

ckt(IC) industry. It causes device failure.
  ESD is a single event, Rapid transfer of electrostatic charge s b/w two
objects. (Usually occurs when two objects at different potential come
into direct contact with each other.
 ESD can also occurs when a high electrostatic field develops b/w two
objects in close proximity.

Note: Static charge is an unbalanced electrical charge at rest. Typically, it is

created by insulating surfaces rubbing together or pulling apart. By that time
one surface gains the electrons while the other surface loses electrons. This
results in an unbalanced electrical condition known as static charge.

When a static charge moves from one surface to another, it becomes ESD.It
can occurs only when the voltage differential b/w the two surfaces is
sufficiently high to breakdown the dielectric strength of the medium
separating the two surfaces.

 When a static charge moves it becomes a current that damages or

destroys gate oxide, metallization, and junctions.
 ESD can occurs in any one of 4 ways;

 A charged body can touch an IC

 A charged IC can touch a grounded surface
 A charged machine can touch an IC or
 An electrostatic field can induced a voltage across a dielectric
which is sufficient to break it down.
There are 3 major test methods are widely used in the industry today to
describe uniform method for establishing ESD.

1. Human body model

2. Machine model
3. Charged device model

Human body model: This model is to represent a charge from a human

finger into a pin of a ckt package.

Machine model: The machine model simulates a machine discharging

accumulated static charge through a device to ground.

Charged device model: The CDM simulates charging or discharging events

that occurs in production equipment and processes. Potential for CDM ESD
events occurs when there is metal to metal contact in manufacturing. The
CDM addresses the possibility that a charge may reside on a lead frame or
package and discharge through a pin that subsequently is grounded; causing
damage to sensitive devices in the path .the discharge current is limited only
by the parasitic impedance and capacitance of the device.

EDS protection:

 Electrostatic discharge can avoid by using ESD protection Diodes.

LATCH UP in CMOS technology:

 Latch up is a parasitic effect in CMOS technology, this is a PNPN

parasitic structure formed by at least two coupled bipolar transistors.
 In a CMOS circuit at least one parasitic PNP and at least one parasitic
NPN bipolar transistors, normally in blocking state, with a very high
impedance, are present. The formation of the main two parasitic
bipolar transistors (one lateral and another vertical) connected in
positive feedback loop.
  When a transitory voltage/current overshoot/undershoot at an
input/output node occurs, PNPN structure can be turned on and a low
impedance path between VDD and VSS can be formed. This low
impedance state can produce either a momentary or a permanent loss
of circuit functioning.

How latch up occurs?

 In presence of some either current or voltage overshoot/undershoot in

an I/O pad, some electrons (holes) can be injected to the P-well (N
well). Un-recombined electrons (holes) are collected in the well
(substrate) by the reverse biased P-well/N-well junction to form
majority carriers current. If this current is large enough, it can produce
an ohmic drop in a parasitic emitter/base junction by RW (RS) which
can turn on the VPNP (LNPN) transistor. Then, the collector current
of VPNP (LNPN) injected to the base of LNPN (VPNP) can form a
positive feedback loop which can generate high currents and burn up
or cause either a momentary or a permanent loss of circuit
functioning.
Latch up triggering modes:

1. Overshoot/Undershoot:
When voltage in a p+ I/O node is higher than a fixed N well voltage, holes
are injected to the N-well. Then they are collected by the reverse biased P-
substrate/N-well junction and produce a ohmic drop in the P-substrate. If
Ohmic drop is high enough; it can forward bias the n+/P substrate junction
and turn on the LNPN transistor. If no protection techniques have been
taken, the parasitic SCR would be turned on.
 2. Avalanching:
P-substrate/N-well junction should be inversely biased, if this voltage
increases considerably, an avalanching current across RS and RW can be
present. For a process without either epitaxial layer or buried layers,
conduction is on the surface.

3. Punch through:
If a n+ diffusion is near to N-well, an increase in inverse bias of P-
substrate/N-well junction can join the depletion regions with voltages
smaller than avalanching voltages. As the N-well voltage increases, the
depletion regions can spread into closely spaced n+ diffusions, and a
Punch through current across N-well can turn on the VPNP transistor.

4. Parasitic field devices:

In field thick oxide regions exist parasitic MOS transistors formed by
interconnection lines over field thick oxide. If voltage in the lines and
trapped charges is high enough to invert a field region, a parasitic channel
across two regions with the same polarity can be formed (for example a
parasitic channel across n+ and N-well and a parasitic channel across p+
and P-substrate), which can inject current across RW or RS and cause voltage
drops that forward bias a parasitic emitter/base junction.

Latch up prevention methods:

Guard ring structures. Guard rings are diffusions which decouple the
parasitic bipolar transistors. There are two guard rings structure types, guard
rings for minority carriers and guard rings for majority carriers connected to
VDD and VSS metal lines. The guard rings for minority carriers are used to
collect minority carriers before they are collected in an inversely biased
P substrate/ N-well junction and flow as majority carriers. The guard rings
for majority carriers decouple the bipolar transistors minimizing voltage
drops created for majority carriers current.

Multiple well/substrate contacts. Majority carriers current flow across well

and substrate whose brings voltage drops that can turn on a bipolar
transistor. So it is necessary minimize the resistance to reduce voltage drop.
This can be done putting multiple well/substrate contacts each 5-10
Transistors or each 25-100 μm.
Lightly doped epitaxial layer on a highly doped substrate and retrograde
wells will avoid the latch up.

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