2017 IEEE 7th International Advance Computing Conference (IACC)

Design of Low Power Multiplier Using CNTFET

Dr. Rajendra Prasad Somineni Shaik Mohammed Jaweed
Associate Professor, ECE, PG student
VNR VJIET, ECE, VNR VJIET,
Hyderabad, India Hyderabad., India.
rajendraprasad_s@vnrvjiet.in jaweedmd12@gmail.com

Abstract— Multiplication is an essential vital role in arithmetic
operations. In fact, multiplication is allotted on operations like
Multiply and Accumulate (MAC). The exaggerate form of Braun
multiplier is the Baugh-Wooley multiplier. This work proposes
the design of Low-power Baugh-Wooley Multiplier with CMOS
full adder with different topologies like 10T, 14T, 17T as well as
with CNTFET full adders using different topologies like 10T,
14T, 17T. All circuits are designed and simulated using HSPICE
Tool.
Index Terms— Baugh-Wooley multiplier, CNTFET, HSPICE
Tool.
technologies. The coaxial structure is shown in Fig.1 (b)
magnifies the coupling between nanotube surface and gate
electrode, therefore inducing more channel charge at given
bias than further calculations. This rectifies that coupling is
desirable at decreasing the short-channel effects that invasion
technologies such as CMOS has the drawback appliance
aspects. The parameters like channel length (Lch), pitch, gate
width (Wgate) and the number of tubes could alter
performance in CNTFET. The CNT diameter is determined by
the threshold voltage of CNFET [2].

I. INTRODUCTION
The need for low power and high speed multiplier circuits
has increased in present synopsis, as they are the major element
in most of the digital systems and many circuits. Low power
transistors fabrication is realizes to get low power multipliers.
In-depth analysis is going for fabrication of transistors with low
power, high speed and small area. The transistors have been
scaled down to reduce the power consumption and area. The
channel material is same for all these scaling methods. The Fig. 1(a). Planar CNTFET
power can be decreased in the multiplier circuit either using
different types of adders topologies. In this paper, the
multiplier is designed with CMOS full adder and also with
CNTFET full adders.
II. THE CARBON NANOTUBE FET
The Carbon nanotubes are totally made up of carbon with
caliber around a nanometer. A CNT is a twisted tube of
Carbon atoms looks like as a honeycomb layout. CNTFET as
three terminals dwelling of a semiconducting nanotube lead
two contacts i.e., drain as well as source are pretence to be as a
carrier channel, which is electrically switched on or switched
off by virtue of gate i.e., represented as third contact. At Fig. 1(b). Coaxial structure of CNTFET
present, there are many classifications of CNTFETs had
fabricated, but there are two major classification of CNTFET The carbon nanotube materials are determined as potential
and they are planar CNTFET and coaxial CNTFET. This devices to substitute silicon in low-power, high-speed material
planar and coaxial structure depend on simple fundamental channels. Channel length of a CNTFET can be scaled down to
and led by added phenomena such as ballistic transport, 5 nanometers before tunneling at room temperature results in
phonon scattering and 1D density of states (DOS) [1]. undesirable leakage currents. Diameter of a CNTFET is
identical to arrangement of the number of tubes.
The Planar CNTFET is shown in Fig.1 (a) is integrate the
majority of component fabricated, generally due to the allied
uniformity and balanced compatibility with present fabrication

978-1-5090-1560-3/17 $31.00 © 2017 IEEE 556

DOI 10.1109/IACC.2017.111
 III. ADDERS B. 14T Full Adder

A full adder is a combinational circuit which adds two
binary numbers with a carry input. The logical function of a
full adder is given as in eq.1 and eq.2.
Sum = Aْ Bْ Cin …………………. (1)
Cout = (AْሻǤ‹൅ǤǥǥǥǥǥǥǤǤሺʹሻ
(i) 14T CMOS Full Adder
A 1-bit 14T CMOS full adder is designed with CMOS
transistors and transmission gates. The CMOS 14T full adder
circuit is as shown in Fig. 4.

In this paper present the full adder cell designed with

different topologies like 10 Transistors, 14 Transistors and 17
Transistors by using CMOS MOSFET's as well as with
CNTFET's.

A.10T Full Adder

(i) 10T CMOS Full Adder

In this section, 1-bit 10T CMOS full adder is designed by
using 10 CMOS transistors [3]. It is a fundamental component
of full adder. Figure 2 shows the 10T CMOS full adder.
Fig. 4. 14T CMOS Full Adder

(ii) 14T CNTFET Full Adder

A 1-bit 14T CNTFET full adder shown in Fig. 5 is designed
with CNTFET’s and transmission gates. By using CNTFET’s
full adder shows the better results in terms of power dissipation
and delay.

Fig. 2. 10T CMOS Full Adder

(ii) 10T CNTFET Full Adder

The 1-bit CNTFET full adder shown in Fig. 3 is designed
by using 10 CNTFET’s. The circuit is designed for smaller
area, low power dissipation and less delay [4].

Fig. 5. 14T CNTFET Full Adder

C. 17T Full Adder

(i) 17T CMOS Full Adder

A 1-bit CMOS 17T full adder shown in Fig. 6 is designed
by CMOS transistors and with Transmission gates to get
minimum power dissipation and delay.
Fig. 3. 10T CNTFET Full Adder

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 Fig. 6. 17T CMOS Full Adder

(ii) 17T CNTFET Full Adder

The 1-bit 17T CNTFET’s full adder shown in Fig. 7 is
designed with CNTFET’s and transmission gates. It is designed
to get low power dissipation and delay. Fig. 8. Schematic circuit of a 4x4-bit Baugh-Wooley multiplier

V. SIMULATION RESULTS

All the CMOS and CNTFET full adder circuits and

multiplier circuits explained above are designed and simulated
using Synopsys HSPICE tool [7] at 32 nm technology with
0.9V supply. All the simulation results are shown in Fig. 9 and
10. Design comparisons in terms of power dissipation and
delay are tabulated in table I.

Fig. 7. 17T CNTFET Full Adder

IV. MULTIPLIER

The exaggerate form of Braun multiplier is the Baugh-

Wooley multiplier. It is designed to outfit multiplication of
both signed and unsigned operands, which are characterized by
2’s number system [5]. Partial products are arranged in such a
way that the negative signs are carried to the final step, which
in turn magnifies the uniformity of multiplication array.

The architecture of Baugh-Wooley multiplier is shown in

Fig. 8. This architecture is designed with CMOS and CNTFET Fig. 9. Full Adder output waveform
as well as with different full adder topologies like 10T, 14T
and 17T. In Baugh-Wooley multiplier it required n(n-1)+3 full
adders.

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 Baugh-Wooley 81.07uw 4.09
10. multiplier using
CNTFET full adder
10T

Baugh wooley 101.1uw 4.39

11. multiplier using
CNTFET full adder
14 T

Baugh wooley
105.48uw 5.171
12. multiplier using
CNTFET full adder
17 T

VI. CONCULSION

Low-power Baugh-Wooley Multiplier with CMOS full

adder with different topologies like 10T, 14T, 17T as well as
with CNTFET full adders using different topologies like 10T,
14T, 17T is designed. Baugh-Wooley Multiplier with CNTFET
10T full adder shows the effective performance result in terms
of power dissipation and delay.
Fig. 10. Output waveform of Baugh-Wooley multiplier
VII. REFERENCES

[1] Rajendra Prasad Somineni, B K Madhavi and K Lal

TABLE I. COMPARISON OF ALL THE DESIGNS Kishore, “Design of 32nm Forced Stack CNTFET SRAM
Cell for Leakage Power Reduction,” IEEE International
Conference on Computing, Electronics and Electrical
Technologies (ICCEET-2012), Nagercoil, India, March 21-
Sl. Design Power Delay (ns) 22, 2012, pp. 629-633.
no dissipation
[2] Rajendra Prasad Somineni, B K Madhavi and K Lal
1. CMOS Full Adder 0.139nw 9.01 Kishore, “A CNTFET SRAM Cell Design at 32nm
10T
Technology for Low Leakage-Power,” IEEE 4th
2. CMOS Full Adder 1.22nw 11.81
14 T
International Conference on Electronics Computer
3. CMOS Full Adder 1.36nw 11.82
Technology (ICECT-2012), Kanyakumari, India, April 6-8,
17T 2012, pp.298-302.
4. CNTFET Full 0.0681nw 5.12 [3] Fayed and M. A. Bayoumi,“A low-power 10 transistor full
Adder 10 T adder cell for embedded architectures,” in Proc. IEEE Int.
5. CNTFET Full 0.283nw 6.47 Symp. Circuits Syst., 2001, pp.226–229.
Adder 14T [4] Navi K, Sharifi Rad R, Moaiyeri M H, Momeni A. A Low-
6. CNTFET Full 0.38nw 6.68 Voltage and Energy-efficient Full Adder Cell Based on
Adder 17T Carbon Nanotube Technology. Nano Micro Letters.
7. Baugh-Wooley [5] C. R. Baugh and B. A. Wooley,”A Two’s Complement
Multiplier Using Parallel Array Multiplication Algorithm”, IEEE
CMOS Full Adder 166.61uw 5.09 Transactions on computers.
10T [6] PramodiniMohanty., ―An Efficient Baugh-Wooley
8. Baugh-Wooley Architecture for both Signed & Unsigned Multiplicationǁ
Multiplier Using International Journal of Computer Science & Engineering
167.71uw 5.17
CMOS Full
Technology (IJCSET).
Adder 14 T
[7] Stanford University CNFET Model website,
http://nano.stanford.edu/model.php?id=23.
9. Baugh-Wooley 167.87uw 5.25
Multiplier Using
CMOS Full Adder
17T

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