Data Sheet

Next Generation
1-Pass Test Synthesis
DFT Compiler

Overview
DFT Compiler — Synopsys next-generation 1-pass design-for-test (DFT) synthesis solution — delivers DFT transparently within
Synopsys’ logical and physical synthesis flow with fastest time to results. DFT Compiler’s integration with Design Compiler®
and Physical Compiler® ensures DFT with seamless optimization of area, power, and timing constraints, and predictable timing
closure of physically optimized scan designs. DFT Compiler enables designers to conduct in-depth testability analysis at the
register transfer level (RTL), to implement the most effective test structures at the hierarchical block level, and, if necessary, to
automatically repair test design rule checking (DRC) violations at the gate-level.

Key Features/Benefits AutoFix

1-Pass DFT Synthesis ■ Enables automatic repair of test DRC violations
■ Shortens the design cycle, eliminating at the gate-level
design iterations and schedule risks Rapid Scan Synthesis™ technology
■ Increases productivity, accounting for ■ Enables rapid implementation of the most effective
testability early in the design test structures at the hierarchical block level
■ Creates STIL protocol file automatically
for input to TetraMAX® ATPG Unified Design Rule Checker
■ Enables RTL or gate-level test DRC and fault
RTL Test DRC coverage validation
■ Ensures fast, accurate testability assurance ■ Links test DRC analysis with Design Vision graphical
at the RT level user interface
■ Delivers feedback on testability violations ■ Uses the same TetraMAX® Automatic Test Pattern
in source-code browser Generation (ATPG) engine that is used for chip-level
■ Enables multimillion-gate capacity ATPG sign-off

Hierarchical scan synthesis using test models

■ Enables multimillion-gate capacity

RTL
Design Compiler Design Constraints:
Designer Fix Timing, Area,
Optional
Violation
Report
RTL Test DRC Power, Test
1-Pass Test Synthesis
Automatic
DRC Violation Fix
ATPG-Ready Test
Netlist Protocol
Figure 1: 1-Pass DFT Synthesis Flow with RTL TestDRC and AutoFix.
1-Pass DFT Synthesis
In Synopsys 1-Pass DFT Synthesis, scan logic is synthesized
directly from the RTL to testable gates with full optimization of
synthesis design rules and constraints. This means that all the
necessary test requirements have been specified prior to the
synthesis process. It creates a gate-level implementation that is
fully scannable and meets all design constraints and process
technology rules, including test. The final design that comes out
of synthesis is “ATPG-ready” with all test-logic verified and scan-
design rules checked, leading to very high and predictable test
coverage results. The implementation of DFT directly within the
synthesis environment allows problems to be found and fixed
earlier in the design cycle, thus avoiding ‘schedule-killing’ design
flow iterations. DFT Compiler also generates the Test protocol in
STIL format that feeds directly into TetraMAX ATPG.
RTL TestDRC
With traditional design methodologies, test-related problems
might not show up until late in the design cycle. Fixing testability
violations at the gate-level negatively impacts overall design
productivity.
RTL TestDRC is designed to enable the designer create “test-
friendly” RTL that can then be easily synthesized in the
1-Pass DFT synthesis environment. The primary function of RTL
TestDRC is to provide feedback on the testability of the design
during the pre-synthesis stage. The module designer invokes the
RTL TestDRC feature on the RTL module prior to synthesis to
verify a comprehensive set of pre-scan DRC rules. The designer
has the option to fix the violations in the RTL source code based
on the feedback. This enables the designer to account for RTL
Schematic showing
Line where violations occured where violations occured
RTL DFT Compiler
Physical Compiler
Physical
Scan Synthesis
Synthesis
Library
Route
ATPG TetraMax® ATPG
Verification
Figure 2: DFT GUI showing RTL TestDRC violations and schematic.
testability early in the design process. The feedback on violations
can be viewed through a browser in the Design Vision graphical
user interface.
A majority of rules checked by RTL TestDRC are pre-scan DRCs
that comprehensively cover the following set of violations,
■ Violations that prevent scan insertion (e.g., uncontrollable clock
or asyn-chronous set/reset to a flip-flop)
■ Violations that prevent data capture (e.g., clock signal drives
data pin of flip- flop)
■ Violations that reduce fault coverage (e.g., combinational
feedback loops)
AutoFix
While RTL TestDRC enables designers to identify violations at
the RT level, the designer has also the option to let the AutoFix
capability fix these violations at the gate level during the synthesis
stage, while meeting timing constraints. AutoFix focuses primarily
on the controllability of clocks and asynchronous set/reset signals,
since these are some of the most common testability problems.
After DRC violations, such as lack of controllability of clocks and
asynchronous set and reset signals are detected, the designer
uses the AutoFix capability to automatically insert test logic at the
gate level to fix these violations. It ensures that the netlist is test-
able and ready for ATPG. Since AutoFix is integrated within
1-Pass DFT synthesis, the testability fixes have minimal or no
impact on the overall timing and area constraints of the design.
The figure below shows an example circuit with uncontrollable
clock and asynchronous reset inputs to a bank of flip-flops.
 Address
RTL

RTL DFT Compiler DFT Compiler

Physical Compiler RTL Test DRC Clock
Physical
FigureScan Synthesis
3: Automatic repair of scan rule violations Synthesis / Quick Testmod
Scan Replacement

RTL Route
Address, Data

D Q
Gate-Level DRC
DFT Compiler D Q
CP
RTL Test DRC Clock Embedded CP
Memory
Synthesis / Quick
Scan Replacement ATPG
Testmode
TetraMax® ATPG
Testmode
Rapid Scan Stitching
Gate-Level DRC D Q D Q

CP CP

Verification
Rapid Scan Stitching

TetraMAX ATPG
D

CP
Q
TetraMAX ATPG
Figure 4: Shadow Logic DFT for an Embedded Memory. Figure 5: Rapid Scan Synthesis Flow.

These are gross DRC violations, which will drastically reduce the
test coverage.
AutoFix has also been extended to support the testing of shadow-
logic around embedded memory modules. Using this capability,
called Shadow-LogicDFT, the designer can synthesize testability
logic at the memory module I/O to enhance the controllability and
observability of the shadow-logic around the embedded memory
module. The DFT driven placement capability in Physical Compiler
places the newly inserted testability logic closer to the respective
ports to minimize congestion.
Rapid Scan Synthesis
Rapid Scan Synthesis technology can be used where the full
optimization capabilities of 1-Pass DFT Synthesis is not desired
to implement a quick prototype of the scan architecture.
This capability enables the rapid implementation of scan chains
and DFT logic to create correct-by-construction scan chains both
in the logical as well as physical environments to generate a scan
netlist to be handed over to ATPG for an early estimate of test
coverage or test pattern count.
Rapid San Synthesis enables faster turn around times both for
scan replacement as well as for stitching scan chains. The other
benefits of this technology is that the existing logic is not optimized,
i.e. upsized or downsized to meet timing, area or physical constraints,
which is sometimes desired since some of the optimization if
preferred in the physical design during place and route.
Hierarchical Scan Synthesis with Test Models
To handle the test synthesis of large designs at the chip level some
level of abstraction is required for the System/Chip Integrator to
make it possible to implement as well as reduce design time by
reducing iterations to achieve both timing and DFT closure. By
bringing key technology to abstract the DFT information in the
form of a test-model along with timing and placement information
in the logical and physical synthesis domains helps the designer
make fundamental decisions to architect the test structures very
early on and enables quick hierarchical test implementation of
multi-million gate designs that require lesser memory and significantly
improves run-time performance.
Synopsys has pioneered to take advantage of the proposed CTL
standard to abstract scan and other test related information into a
test-model, which is created during scan synthesis with DFT
Compiler and is completely transparent to the user [Figure: 6].
The user can then write out the test-model, which has only the test
relevant information along with the full-gate netlist information as
is done in a typical bottom-up flow. At the top-level, only test-models
are read into memory along with the top-level netlist and scan
stitching is performed without having to read in all the gate-level
information of the sub-modules. This capability to read in test-
models and perform a top-level scan DRC along with balanced
scan-stitching significantly improves the capacity as well as
performance of large designs.
 RTL

RTL DFT Compiler

Design Compiler Design Constraints: Physical Compiler
x Timing, Area,
Violation
Report
RTL Test DRC Power, Test Physical
Scan Synthesis
1-Pass Test Synthesis Synthesis
Library
Route
Automatic
DRC Violation Fix
ATPG TetraMax® ATPG

ATPG-Ready Test
Netlist Protocol Verification

Figure 6: Hierarchical Scan Synthesis with Test Models. Figure 7: The Integrated DFT Compiler and Physical Compiler Flow.

Integration with Physical Compiler for 1-Pass Scan Ordering
DFT Compiler is also now integrated into Physical Compiler to
provide 1-Pass scan chain positioning and ordering with minimal
additions to the existing DFT flow. This means that Physical
Compiler will ensure that each scan flop is connected to its
nearest neighbor based on location. DFT Compiler uses the
physical placement information and employs a constraint-driven
scan-ordering algorithm to determine the scan chain order.
This capability also enhances the seamless flow between DFT
Compiler and TetraMAX ATPG by delivering an optimized scan
ordered netlist to the ATPG tool, thereby completely eliminating
the need for reordering ATPG vectors (see figure7).
Netlist/RTL Interface
DFT Compiler supports the popular industry standards Verilog
and VHDL

The other advantage of using DFT compiler within Physical

Compiler is that scan chains are also partitioned based on
physical information. The tight integration of scan synthesis
within Physical Compiler enables designers to achieve,

■ Faster timing closure with testable designs

■ Decrease overall routing congestion
■ Minimized timing violations related to scan routing

The other benefits of implementing DFT in the physical domain

with DFT Compiler enables new logic introduced for test like lock-
up latches, wrapper logic etc to be placed closer to their driver
cells to minimize congestion and improve routability.

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©2004 Synopsys, Inc. 09/04.KF.04-12701