1. What is the role of ISR?

A. An interrupt is an unplanned diversion after executing an instruction on an event.

Diversion is from
the task current sequence of instructions A to another sequence of instructions B, which services
another task. The sequence of these codes B is called an interrupt service routine.
An ISR is a routine, which executes because of the interrupt from a source other than the
foreground program A undergoing execution of a signal interrupt from the foreground program A.
The ISR B may be required to first push the A parameters on to the stack, for example, the PSW,
accumulator, other SFRs and registers or memory addresses. Any byte at an addressed location or
register may also be saved in case the ISR is likely to change it during execution.
The ISR return instruction executes as follows:
a. Restores the PC at the stack and re-adjusts the stack pointer.
2. Restores the interrupt structure. Make it identical to the one at the interrupt and service of the
ISR.
3. Check another pending interrupt service(s). If yes, initiate another servicing action(s).
4. If no, start executing the foreground A or the routine left earlier on the interrupt.
ISR B must also restore in the LIFO way the saved parameters by the pops from the stack.
Any byte of an addressed location or register that was saved within the ISR must be restored by the
ISR before the RETI instruction. The RETI also restores PC-like on RET in a called routine. These
actions restore all the previous states of the variables and flags in the registers, so that the
foreground program functioning does not affect.

2. Differentiate between Harvard and Princeton Memory Architectures.

A.
HARVARD Architecture PRINCETON Architecture
1. It has distinct memory address space 1. It has a common memory address space
for the program and data memory. for the program and data memory.

B. 2. It h 2. It has separate instructions &2. It has no separate instructions& hence no

hence separate control signals for data transfers
C. separate control signals for between these two memories.
data transfers
D. from these two memories.
3. It is fast in operation. 3. It is slower.

3. Explain RTC. What are the main functions of RTCs?

A. An MCU is said to have a real time clock device if it can make or have one of the timers nonstop
and no reset and load- disabled state. The interrupts from this timers, once enabled, cannot be
disabled. The timer overflow interrupts now acts like a clock that ticks at regular intervals. Timer
overflow means transition from its all1s to all 0s output state. If the timer does not stop, it repeatedly
interrupts at constant intervals and it gets inputs from an internal clock continuously after
appropriate scaling by a certain factor. Scaling here means division by a factor, say, 2, 4, 16, or 64.
The word, real time is used because it never stops and cannot be reset.
Real time clock is an important resource in a micro controller because using this, an OS
 sets the system clock and schedules the tasks and time-delay functions. It is an on chip device made
from the timer working in non-reset, non-loadable and non-stop mode. The interrupts from this
timer are the real time clock ticks, which also update time information at certain memory addresses.

4. Explain the following organizations of 80196

a) i/o b) memory c)interrupt
Ans:
Addressable space

The addressable memory space of the 80c196 consists of 64k bytes. However, not all
these addresses are available to the user. Addresses 0000H through 00FFH and 1FFEH
through 207FH are reserved for special purposes. All other locations can be used for either
program or data storage, or for memory-mapped I/O.

FFFFH +-------------------------+
| |
| External memory or I/O |
| |
4000H +-------------------------+
| Internal ROM/EPROM or |
| external memory or I/O |
2080H +-------------------------+
| Reserved |
2040H +-------------------------+
| 8 interrupt vectors |
2030H +-------------------------+
| ROM/EPROM security key |
2020H +-------------------------+
| Reserved |
2019H +-------------------------+
| Chip Configuration byte |
2018H +-------------------------+
| Reserved |
2014H +-------------------------+
| 10 interrupt vectors |
2000H +-------------------------+
| Port 3 and port 4 |
1FFEH +-------------------------+
| External memory or I/O |
0200H +-------------------------+
| 80c196KC internal RAM |
0100H +-------------------------+
| Registers and SFRs |
0000H +-------------------------+
80c196 addressable space

Registers (internal RAM)

Locations 00H through OFFH contain the 232 general registers and the 24 SFRs - Special
Function Registers. The RALU can operate on any of these 256 internal register
locations, but code cannot be executed from them. If attempt is made to execute
instructions from locations 00H through OFFH, the instructions will be fetched from
external memory. This section of external memory is generally used by the Intel
development tools.

Locations 018H through OFFH are the general registers. These locations can be accessed as
byte, word ou double-word registers, and can be essentially considered as 232
accumulators.

Locations 018H and O19H contain the stack pointer. Operations to the stack cause it to be
built down and the stack pointer is pre-decremented, so the stack must be initialized by
the user program to 2 bytes above the highest stack location. The stack pointer must
point to a word (even) address.

Special Function Registers (SFRs)

Locations 00H through O17H are the I/O control registers or SFRs. All of the peripheral
devices of the 80c196 except ports 3 and 4 are controlled through these registers. SFR
functions are controlled through 3 windows. Switching between the windows is done
using the WSR - Window Select Register located at address 014H. SFR windows other
than WSR = 0 are out of the scope of this course.

Some of the Special Funtion Registers have different meanings if read from or written to.

Reserved memory locations

Locations 1FFEH and O1FFFH are used for Ports 3 and 4 respectively. Many reserved and
special locations are in the memory area between 2000H and 2080H. The 18 interrupt
vectors, the chip configuration byte and the security key are located in this area. All the
addresses marked Reserved in this area have to be programmed with value 0FFH. 2080H
is the normal program start address. A reset interrupt restarts the program at address
2080H.

External memory

There are several modes of system bus operation on the 80c196. The standard bus mode
uses a 16-bit multiplexed address/data bus. Other bus modes include an 8-bit mode and a
mode in which the bus size can be dynamically switched between 8-bits and 16-bits. In
addition, there are several options available on the type of bus control signals which make
an external bus simple to design.

In the standard mode, external memory is addressed through lines AD0-AD15 which form
a 16-bit multiplexed bus. The idealized bus timings are represented below :

Standard mode idealized bus timings

The ALE - Address Latch Enable signal provides a strobe for flip-flops (e.g. 74x373s) to
demultiplex the bus by latching the address. Demultiplexed address signals will be called
MA0-MA15.

The data returned from external memory must be on the bus and stable for a specified
setup time before the rising edge of !RD (Read). The rising edge of !RD signals the end of
the sampling window. Writing to external memory is controlled with the !WR (Write) pin.
Data is valid on AD0-15 on the rising edge of !WR. At this time data must be latched by
the external system.

In standard 16-bit mode, the external memory is composed of two parallel 8-bit memory
banks. Since a given address selects one byte, the 16-bit data bus has to be reconstructed
from the low-order byte located at the even address, and the high-order byte located at the
odd address (see Figure).

The !BHE signal is provided for 16-bit bus accesses. Together with MA0, this signal allows
to select either the low-order byte, the high order-byte, or both bytes during a 16-bit bus
access :

Memory bank selection

!BHE A0 selected bank

0 0 high order + low order

0 1 high order only
1 0 low order only

Actually, when a block of memory is decoded for reads only, which is typically the case
of EPROMS, the system does not have to decode !BHE and MA0 : the 80c196 will discard
the byte it does not need. But for systems that write to external memory, separate write
strobes must be generated for both the high and low bytes of memory.
 5. Write about 16/32 bit ARM instruction set.
Ans: The ARM architecture is such that the 32 bit ARM instruction set and 16 bit Thumb
instruction subset both can be used. The instruction set extends to provide support for
Java acceleration (Jazelle). Instruction set also extends to provide support for security-
coding features.

32/16-bit ARM instruction set

Like a RISC, the ARM has a large number of registers and instructions of fixed length.
Each instruction is of 32bit in the ARM instruction set and there are sixteen registers, r0
to r15 with r15 as PC.

Like the RISC instruction set with load and store architecture, instructions are such that
the variables and memory addresses must first be loaded into the registers and then
operations performed using the registers and then the result should be stored in the
memory. Absolute addressing and direction addressing instructions are not present in the
ARM as length of each instruction is 32-bit. Absolute address can be computed in a
register by arithmetic addition or subtraction using the PC address from r15 and offset
between current instruction, a pseudo instruction ADR r, addr, where addr are lower 12-
bit for the 32-bit address. Implementation of the ADR pseudo instruction is by
implementing instruction SUB r, r15, #&byte_offset, where 12-bit byte_offset is
Address_r15 and r15 has the current program counter at a 32-bit address.

Addressing modes that are present in the ARM instruction set are as follows.

1. Register Addressing: All operands are within the register itself. For example, MOV r1, r2
and MVN r1, r2 instruction. These mean (r1)←(r2) and (r1)←NOT(r2), move r2 or
complement of r2 bits into r1. AD r1,r2,r3 adds the source operands r2 and r3 bits and
execution result is at the destination operand r1,
2. Immediate Addressing: Second source operand can be immediate operand. Immediate
operand is of fewer-bits. For example, 8 bits in case of an ADDGT instruction, which
adds if the conditional test is successful, 12-bits in case of an ADD with no condition
tests. ADD r6, r7, #8 adds r7 and 8 and the result is in r6.
3. Indirect Base and Indexed Addressing: It is the major mode for load-store architecture as
direct absolute addressing is not provided. The following are the types of indirect
addressing modes. In all the types the assumption is all 16 msbs are 0.
a. A byte or half-word or word address is pointed by the indirect address in a GPR.
LDR r1, [r2] instruction loads r1 from the memory address pointed by r2. If r2
is 1000 1000 1000 1000, then r1 will load the 32 bits from memory address
1000 1000 1000 1000. The r2 and r3 remain unchanged.
b. A byte or half-word or word is pointed by the indirect address obtained by
subtracting two registers of GPR set. LDR r1, (r2’,-r3) instruction loads r1 from
the memory address, which is as per r2-r3. (If r2 is 1000 1000 1000 1000 and r3
 is 1000 1000 0000 0000, then r1 will load the 32 bits from r2-r3= 0000 0000
1000 1000. The r2 and r3 remain unchanged).
c.A byte or half-word or word address is pointed by the indirect base address by
adding GPR with an offset as immediate operand. This mode is indirect
addressing by base plus 12-bit byte_offset (like base relative or index relative in
80x86 processor). LDR r4, [r5, #9] instruction loads r4 from the memory
address pointed by r5+9. (If base address at r5 is 0000 0000 1000 1000, then r4
will load the 32 bits from memory address 0000 0000 1000 1001 0001. The r5
remains unchanged). STR (r5, #&0C), r4 instruction stor r4 32-bits to the
memory address pointed by r5+12.
d. There is an indirect addressing mode by index plus offset with auto indexing.
LDR r4, [r5], #8 instruction loads r4 from the memory address pointed by r5
and then adds the offset 8 to r5. The r5 remains unchanged for next time use of
r5. This is called auto post indexing.