Вы находитесь на странице: 1из 5

IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

Design Methodologies and Circuit


Optimization Techniques for Low Power
CMOS VLSI Design
Dr.B.T.Geetha1 ,B.Padmavathi2 V.Perumal
Associate Professor1,Assitant Professor2 Associate Professor3. Department of CSE
Department of ECE Saveetha Engineering College
Jeppiaar Maamallan Engineering College Chennai,India.
Chennai,India
dr.geetha.bt@gmail.com

Abstract— Low power is the real test for late hardware circuits. In the zone of small scale controlled battery worked
businesses. Control scattering is an essential thought as far as compact applications, for example, mobile phones, the
execution and area for VLSI Chip outline. Control administration objective is to keep the battery lifetime and weight sensible and
procedures are for the most part used to configuration low power bundling cost low. Scaling of CMOS gadgets has empowered
circuits and frameworks. Insights demonstrate that 40% or the semiconductor business to take care of its demand for
considerably higher rate of the aggregate power utilization is higher execution and higher coordination densities. However as
because of the leakage of transistors. This rate will increment with
the component measure gets to be distinctly littler, in light of
innovation scaling unless streamlining methods are acquainted
with bring leakage inside points of confinement. This paper
short direct lengths it brings about expanded sub-threshold
concentrates on circuit improvement and plan mechanization leakage current through a transistor when it is off condition.
strategies to fulfill this target. It additionally portrays many issues Another purpose behind expanded sub-threshold leakage
with respect to circuit outline at building, legitimate and gadget current is that, transistors can't be turned off totally. Henceforth
levels and exhibits different procedures to beat the previously leakage control dissipiation has turned into a vital bit of the
mentioned issues. The initial segment of the paper gives a diagram aggregate power utilization for silicon innovations. The
of primary wellsprings of leakage current in CMOS transistor. significant three plan parameters are power, speed and area. In
The second part of the paper depicts various circuit streamlining CMOS VLSI circuits, control dissipation is basically because
procedures for controlling the standby leakage current. Some
of the three essential elements: dynamic, static and short out. A
leakage current lessening procedures like rest approach; stack
approach, and lector strategy are talked about for planning
few enhancement strategies have been proposed for leakage
CMOS entryways which fundamentally chops down the leakage current lessening. One essential thing in CMOS VLSI circuit
streams. The benefits of lector method are it doesn't require any configuration is to lessen the power dissipation while keeping
extra control and observing hardware, in this way constraining up the superior of the circuit. The edge voltage must be scaled
the range increment and furthermore the power dissipation in to keep up the execution of the circuit. In VLSI circuit outline
dynamic state when contrasted with different systems and it the power utilization has turned into an essential issue. In this
doesn't influence the dynamic power which is the significant manner the real test in versatile framework configuration is to
confinement with the other leakage diminishment strategies, is diminish the power utilization of coordinated circuits through
likewise examined in this paper.
outline improvements. Various strategies have been proposed
Keywords- VLSI, Power consumption, Dynamic power, by scientists to take care of the power utilization issue. In any
case, there are no influences to meet trade-off between power,
Clock gating, lector method etc
postponement and region .Appropriate systems must be picked
that fulfils the application and item needs. At last, for better
I. INTRODUCTION execution, no battery worked frameworks, for example,
In the previous decades, the real test for the VLSI architect was workstations, set-beat PCs and interactive media computerized
region, execution, cost and power utilization. As of late, in any flag processors, the general objective of force minimization is
case, this has started to change and, progressively control to lessen framework cost (cooling, bundling and vitality
utilization is being given practically identical weight to region utilization) while guaranteeing long haul gadget unwavering
and speed contemplations. The thoughts for lessening power quality. These diverse necessities impacts how control
utilization vary from application to application and circuits to improvement is managed and how much the planner will
bargain in cost or execution to get bring down power
dissipation.

978-1-5386-0814-2/17/$31.00 ©2017 IEEE

1759
IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

II. SOURCES OF POWER DISSIPATION A. Junction leakage


When we perceived power utilization as a plan limitation, At the point when a transistor is off, the junction leakage
Power per MHz is normally utilized as a recurrentation of a happens from the source or deplete to the substrate through the
segment. Electric current is not steady amid operation and turned around one-sided diodes. This leakage current has two
pinnacle power is a critical concern. The gadget will principle parts: one is minority bearer dissipation close to the
breakdown because of electro migration and voltage drops edge of the exhaustion locale; the other is because of electron-
regardless of the possibility that the normal power utilization is opening pair era in the consumption district of the turnaround
low. The condition for the normal power utilization is given as one-sided junction. In the event of an inverter with low
information voltage, the NMOS is OFF, the PMOS is ON, and
Pavg = Pdynamic + Pshort + Pleakage + Pstatic the yield voltage is high. Thus the deplete to-substrate voltage
of the OFF NMOS transistor is equivalent to supply voltage.
So the aggregate normal power utilization relies on upon
This causes leakage current from the deplete to the substrate
Dynamic power utilization, Short-circuit control utilization,
through the turned around one-sided diode.
Leakage control utilization and static power utilization. The
leakage current is controlled by the manufacture innovation,
B. Gate-induced drain leakage
which comprises of turn around inclination current in the
The door instigated deplete leakage current, is the deplete to-
parasitic diodes shaped amongst source and deplete
substrate leakage created by high field impact in the deplete
dissipiations and the mass district in a MOS transistor and in
junction of MOS transistors. At the point when the deplete of a
addition the sub threshold current that emerges from the
reversal charge that exists at the door voltages beneath the edge NMOS is one-sided at the supply voltage (VDD) and the door
voltage. The short out current which is because of the DC way is one-sided at either zero or negative voltage, an exhaustion
locale is framed under the entryway and deplete cover district.
between the supply rails amid yield moves and the charging
This causes noteworthy band bowing in the deplete permitting
and releasing of capacitive burdens amid rationale changes.
electron gap combine era because of torrential slide
The short out and leakage streams in CMOS circuits can be
made little with appropriate circuit and gadget outline augmentation. A profound exhaustion condition is made as the
procedures. The fundamental wellspring of force scattering is openings are quickly cleared out to the substrate. In the mean
the charging and releasing of the junction capacitances. time electrons are gathered by the deplete, bringing about
Exchanging movement is a measure for the quantity of Gate Induced Drain Leakage current.
entryways and their yields that change their bit an incentive
amid a clock cycle. To flip between rationale zero and rationale C. Sub-threshold leakage
one can released and charged the junction capacitor. The Sub-threshold leakage is the current that streams between the
electric current that streams amid this procedure causes source and deplete of a MOSFET. At the point when a
dynamic power dissipation Pdynamic. The dynamic power is transistor is working in the powerless reversal district, that is,
rely on the capacitive yield stack Cout and the supply voltage for entryway to-source voltages beneath the limit voltage. This
Vdd and recurrence of clock flag. is brought about because of the diffusion current of the
minority carriers in the channel for a MOS gadget. The sub-
Pdynamic = K Cout Vdd2 f threshold leakage current is much bigger than the other leakage
current segments. This is mostly as a result of the moderately
K is the average number of positive transitions during one low VT in cutting edge CMOS gadgets.
clock cycle and f the clock frequency. By reducing the power
supply will have a larger effect on saving power, taking into IV. LEAKAGE CONTROL IN ACTIVE MODE
consideration that typically Pdynamic is responsible for 80% of
Pavg. A. Multiple threshold cells
To manage the leakage issue, multi limit CMOS circuit, which
III. SOURCES OF STATIC LEAKAGE POWER has both high and low edge transistors in a solitary chip can be
DISSIPATION utilized. Sub limit leakage current is stifled by the high edge
1. Reverse-biased junction leakage current (Irev) transistors while low edge transistors are utilized to accomplish
2. Gate induced drain leakage (Igidl) the superior. However utilization is constrained to utilizing low
3. Sub-threshold (weak inversion) leakage (Isub) VT transistors, with addition rates on the request of 20% or less
since the standby power is much bigger for low VT transistors
contrasted with the high VT transistors. The dynamic power

1760
IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

part or the outline size is not unfavourably influenced since the power supply and ground. Amid standby mode, rest transistors
TOX and entryway lengths are same for high and low VT are killed, along these lines making the virtual way between the
transistors. The disadvantage of this strategy is that variety power supply and the ground. It is important to have rest
because of doping is uncorrelated between the high and low transistor with high limit esteem else it will have high leakage
limit transistors and additional cover steps acquire a procedure current. This innovation is actualized with a few sorts of
cost. transistors with various VT values. Transistors with a low VT
are utilized to actualize the rationale, while high VT gadgets
B. Long channel devices are utilized as rest transistors.

There is VT move off because of short channel impact. B. Sub-threshold power reduction techniques
Consequently dynamic leakage of CMOS entryways can be
diminished by expanding their transistor channel lengths. Sub-limit leakage current is turning into the essential
However the entryway capacitance increments for longer wellspring of force dissipiation in CMOS beneath 90nm.
transistor lengths used to accomplish high edge transistors. Subsequently power is supplanting different components like
This negatively affects the execution and element control execution and silicon zone in planning CMOS circuits.
dissipation. Long channel inclusion has comparative or lower
prepare cost contrasted and various limit voltages taken as the 1. Conventional CMOS technique.
size increment instead of the veil cost. The disadvantage of this
system is that the dynamic power dissipation of the up-sized
In this method reciprocal CMOS circuit is utilized that has a
entryway builds relative to the compelling channel length
NMOS pull down system to interface with "0" (GND) and
increment. Consequently movement variable of the influenced
PMOS pull up system to associate with the yield to "1" (VDD).
entryways must be low to spare the circuit control scattering.
It is a fundamental approach that is utilized for the most part in
V. STANDBY MODE LEAKAGE REDUCTION all methods. Fig 2 demonstrates the piece outline.
TECHNIQUE
Most electronic frameworks invest significant energy in a
standby state. Thus battery life stays sit out of gear for long
stretch aside from when being used and depletes off a large
portion of the power, which thus decreases the battery life.
Hence battery life can be spared by closing it down from the
supply when not being used.

A. Multi-threshold CMOS technique


Fig 2. Conventional CMOS circuit structure
In this procedure, high edge voltage transistor is associated in
arrangement with the power supply and existing PMOS and 2. . Stack technique:
NMOS arrangement circuit to make a virtual ground and a
virtual power supply as appeared in the fig. 1 Another strategy for leakage control diminishment is stack
approach, that depends on the way that characteristic stacking
of MOSFET help to lessen the leakage current. At the point
when two transistors associated in arrangement are killed
together, instigated turn around predisposition between the two
transistors causes in the decrease of sub-limit leakage current.
However isolated transistors increment defers essentially
restricting the execution. Fig.3 demonstrates the circuit
schematic for the same.

Fig.1 Power gating circuit

In dynamic express, the rest transistor is ON, encouraging


typical operation as there is an immediate way between the

1761
IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

VI. SYSTEM DESIGN


Framework level low power plan systems ought to be most
encouraging for decreasing vitality utilization. Two systems are
meant in this segment.

A. HW/SW Partitioning
The MicroPP Plus will be an installed framework with two
processor centres, a controller and a DSP. Administrations can
Fig.3 Stack technique circuit structure
be actualized either in programming running on these centers,
3. Modified lector technique. or in committed equipment. In our plan stream this will be
chosen amid the progression of hardware software dividing.
The essential thought behind LECTOR procedure for leakage This procedure has awesome impact on framework control.
current lessening depends on the successful stacking of This is shown in the accompanying case: Specific equipment is
transistors in the way from supply voltage to ground. This for the most part more productive. 330mW are expended to
depends on the idea that "a state with more than one transistor play out an expansion utilizing a SPARClite processor centre
OFF in a way from supply voltage to ground is less cracked in a commendable innovation (0.32mm/1.8V/16.8 MHz). A
contrasted with a state with just a single transistor OFF in any custom viper in a similar innovation expends just 2mW or
supply to ground way. Fig.4 demonstrates the circuit schematic more extra correspondence overhead.
for the LECTOR method. Between hubs N1 and N2 two LCTs
(leakage control transistor) are currented. The entryway B. Integration of Chip Components
terminal of each LCT is controlled by the wellspring of the Actualizing frameworks utilizing current day innovation brings
other. Henceforth called self controlled stacked transistors. As about third or a greater amount of aggregate power being
LCTs are self controlled, no outside circuit is required. In this expended at the chip's information/yield (I/O) ports. The bigger
manner the restriction with the rest transistor system has been capacitances of chip's limits contrasted with inner doors and
overcome. The leakage current is diminished in light of the fact higher voltages are the explanation behind this perception.
that the currentation of LCTs builds the resistance of the way Common qualities for inner capacitances dwell around 10's of
from VDD to ground. In this strategy, two LCTs were included femtofarads, where I/O pins achieve measurements of 10's of
each CMOS entryway, a PMOS added to the draw up system microfarads. These days supply voltages for chip cores have a
and a NMOS added to the draw down system and the door tendency to be lower then 2.0V. In mechanical frameworks not
terminal of one LCT is controlled by the wellspring of the all segments of an outline may be best in class and require
other. Accordingly one of the LCTs is constantly close to its higher voltages or specialized limitations require them. Still,
cut-off area of operation for any offered contribution to the these distinctive parts need to impart over their I/O. This makes
CMOS entryway. This gives extra resistance in the way from double voltage frameworks (bring down voltage for the centers
supply voltage to ground consequently diminishing the sub- – higher voltage for I/O) very normal.
threshold leakage current, thusly the static
power. VII. CONCLUSION

The leakage current turns out to be more basic in compact


frameworks with profound sub-micron and nanometre
advancements, where battery life is of essential concern.
Dealing with leakage power is an incredible test in nanometre
scale innovations since sub-limit leakage control gets to be
distinctly good to element control utilization. The upside of
Lector system is that as it doesn't require any extra control and
checking circuits it doesn't influence the dynamic power. A low
voltage/low limit innovation and circuit configuration
approach, focusing on supply voltages around 1 Volt and
working with decreased edges.
Fig.4 Lector CMOS gate

1762
IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

• Low power interconnect, utilizing propelled


innovation, lessened swing or diminished action
approaches.
• Dynamic power administration systems, changing
supply voltage and execution speed as per movement
estimations. This can be accomplished by parcelling
the plan into sub-circuits whose vitality levels can be
freely controlled and by shutting down sub-circuits
which are not being used

References

[1]. Anjana R, Ajay kumar somkuwar, "Analysis of sub threshold leakage


reduction techniques in deep sub micron regime for CMOS VLSI
circuits"

[2]. Farzan Fallah and Massoud Pedram, " Standby and Active Leakage
Current Control and Minimization in CMOS VLSI Circuits".

[3]. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, Kluwer
Academic, Publishers, 1998.

[4]. Kanika Kaur and Arti Noor, “Strategies & methodologies for low power
vlsi designs: a review” International Journal of Advances in Engineering
& Technology, May 2011. ISSN: 2231-1963.

[5]. K.Srilaxmi, Y. Syamala and A. Suvir Vikram, "Static power


optimization using dual sub- threshold supply voltages in digital CMOS
VLSI circuits", International Journal of VLSI design & Communication
Systems (VLSICS), Vol. 4, No. 5, October 2013.

[6]. K.R.N.karthik, M.Nagesh Babu, V.NarasimhaNayak, S.Rajeswari and


Dr. FazalNoorbasha, "Cadence Design of Leakage Power Reduction
Circuit in CMOS VLSI Design ", International Journal of Engineering
Research and Applications, Vol. 3, Issue 2, March - April 2013, pp. 738
741.

[7]. Luca Benini, Giovanni De Micheli, Enrico Macii, "Designing Low-


Power Circuits : Practical Recipes

[8]. Massoud Pedram Design Technologies for Low Power VLSI.


Department of EE-Systems University of Southern California Los
Angeles, Encyclopedia of Computer Science and Technology, 1995.

[9]. W.C.Athas, L. J. Svensson, J.G.Koller, N.Thartzanis and E. Chou. "


Low-Power Digital Systems Based on Adiabatic-Switching Principles. "
IEEE Transactions on VLSI Systems, 2(4)398407:, December 1994.

[10]. Sonam Rathore, "Low Leakage Power SRAM Design Using Lector
Technique In Various CMOS Technology", International Journal of
Advanced Research in Computer Science and Software Engineering,
Volume 4, Issue 6, June 2014, pp. 279 - 284.

1763