SIM 2011 – 26th South Symposium on Microelectronics 149

Digital Logic Cancellation Block for a Cascade Feed-Forward

Sigma-Delta Analog-to-Digital Converter

Paulo César C. de Aguirre, Felipe C. Lucchese, Lucas Teixeira, Crístian Müller and
César Augusto Prior
{paulocomassetto, felipelucchese, lucasteixeira, cristian.muller}@mail.ufsm.br,
cesar.prior@ieee.org

Grupo de Microeletrônica – Gmicro

Universidade Federal de Santa Maria - UFSM

Abstract
This paper presents the characterization and synthesis results for a hardware implementation of a
reconfigurable digital logic cancellation circuit auxiliary for multi-mode Σ∆ modulator that is capable to
perform the analog-to-digital conversion for GSM, CDMA and WLAN standards. The Σ∆ modulator
reconfigures its mash topology and building blocks in order to adapt the performance to the diverse standard
specifications. The necessary integration and cancellation at three modulators output for baseband signal
processing was designed in high level Matlab/Simulink and coded with VHDL for synthesis intended to
prototyping in CMOS process.

1. Introduction
The evolution of band-base analog-digital conversion in telecommunications systems and signal
processing lead with multi-mode capability of standards, comes from the 2G systems with high quality services
for 3G systems, which include global system for mobile communications (GSM) and a wide-band code division
multiple access system (WCDMA) to wireless systems that incorporate both Wireless Local Area Networks
(WLAN) and cellular capability. Typical triple-mode base-band architecture and the required bandwidth to deal
with GSM, CDMA and WLAN signals are shown in Fig.1 and Tab.1, respectively. In this context a multi-mode
cascaded Σ∆ architecture have been reported in [1] whose wide programmability range of input frequency and
dynamic range descends from modulator order programmability. Another reconfigurable Σ∆ modulator for a
triple standard receiver has been introduced in [2] where a feedback path from the last to the third stages is done
in order to further suppress the quantization noise power. Yet another multi-standard sigma-delta ADC has been
explored in [3].
To allow the multi-mode cascade Σ∆ architecture a reconfigurable digital logic cancellation circuit is
needed. This circuit is responsible for the modulators output signal processing in order to adapt the cascade
architecture performance to diverse standard specifications. The development, hardware implementation and
synthesis results of this reconfigurable architecture using two different technologies are presented.
The paper is organized as follows. Section 1 is the introduction. Section 2 focuses on selecting the
appropriate architecture for the multi-standard specifications. Section 3 describes a logic cancellation function.
Section 4 provides the implementation and simulation results. Finally, Section 5 concludes the paper.

Fig. 1 – Typical Triple-mode base-band Architecture.

150 SIM 2011 – 26th South Symposium on Microelectronics

Tab.1 - Requirements for baseband

Standard Frequency (MHz) Chanel Banwidth Dynamic Range
GSM 890-915(Tx) - 935-960(Rx) 200kHz 80dB
WCDMA 1850-1910(Tx) - 1920-1980(Rx) 5MHz 60dB
WLAN 2401-2473 20MHz 50dB

2. The overall circuit topology

A proposed cascaded second order single bit Σ∆ modulator 2-2-2 structure is shown in Fig. 2. In order to
adapt the system modulator performance to GSM, CDMA and WLAN standard specifications the cascade
topology and the logic cancellation block can be reconfigured to provide a second, fourth and sixth order
system modulator. A Matlab/Simulink whole system simulation was performed and the simulation results
shown that these bandwidth requirements, presented in Tab. 1, can be achieved at a frequency of 160 MHz and
with the coefficients showed in Tab. 2.

1 1
z −1 z −1

1 1
z −1 z −1

1 1
z −1 z −1

Fig. 2 – Mash Triple-mode SD modulator Architecture.

The system is composed for three second-order Σ∆ analog-to-digital converters based in a low distortion
topology that was presented in [5]. The GSM output mode is directly obtained at the first stage output and the
Eq. (1) presents the system transfer function:
(1)

The CDMA mode, Eq. (4), is obtained with a fourth order system modulator. The system second stage
output is given by:
(2)

Where,
(3)
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Tab. 2 – Coefficients of Σ∆ mash 2-2-2 architecture

Coefficients g1/g1b/w1/s1/g2/w2/s2 g3/g4/w3/w4/s3/s4
GSM 0.5 4
WCDMA 0.5 4
WLAN 0.5 4

Then,
(4)

To cancel this output and obtain the transfer function for a fourth order modulator based in 2-2 cascade
structure, Eq. (5):
(5)

The logic cancellation block must perform the transfer functions Eq. (6) and Eq. (7):

(6)

(7)

Similarly, for the WLAN mode, a sixth order system modulator is needed. The third stage output (Eq. (8)),
the transfer function for a sixth order modulator (Eq. (8)) and the operations to be performed by the logic
cancellation block (Eq. (10) and Eq. (11)) are, respectively:
(8)

(9)

(10)

(11)

The digital logic cancellation architecture block diagram is shown in Fig. 3 and its functionalities are
explained in Section 3.

3. The Logic Cancellation Circuit

The logic cancellation circuit operates at a 160 MHz frequency, 6.25 ns period, and it is composed for three
kinds of functions: Gain, Delay and Differentiator. This block, illustrated previously in Fig. 2, is simplified in
Fig. 3. The Y2, Y4, and Y6 are single bit inputs and the Y(OUT) is a ten bit array output.

2
 1 
 
 z 

2
 z −1
 
 z   1 
2

 
 z 

4
 z −1 
 
 z 

Fig. 3 – Logic Cancellation Circuit.

The H1(z) function implements a two clock cycle delay in the Y2 signal. The H2(z) function executes in a
single clock cycle one gain and two differential operations. In the first operation a gain of 4 is applied at the Y2
152 SIM 2011 – 26th South Symposium on Microelectronics

input and this signal is the input of the first of two differentiators where the previous signal is subtracted from
the actual signal in each differentiator operation. Adding the outputs of H1(z) and H2(z) the CDMA bandwidth
output is achieved.
The additional blocks H3(z) and H4(z) are necessary for the WLAN bandwidth output. The H3(z) block
implements a two clock cycles delay in the CDMA signal and the H4(z) implements a gain of 16 at the input
Y3 and executes four differentiator operations, all in the same clock cycle. Hence, to reach the WLAN
bandwidth the H3(z) and H4(z) functions must be added.
To choose the modulator order output needed by the user a simple multiplexer is presented at the digital
cancellation block output.

4. Implementation and Simulation Results

The designed digital architecture was described in VDHL and synthesized for two different technologies:
Altera Stratix II EP2S60F672C3N FPGA and X-FAB XC06 5V CMOS Process, using Quartus II and Synopsys
Design Compiler tools, respectively.
Tab. 3 shows the synthesis results for the entire developed module considering maximum frequency
operation and hardware consumption (number of DLRs and ALUTs for FPGA and logic cell number for
standard cells).
Tab. 3 – Synthesis Results
Stratix II EP2S60F672C3N X-FAB XC06 (0.6µm)
Frequency #ALUTs #DLRs Frequency #Logic Cells # NAND2 Equivalent Gates
575.04 MHz 35 36 195.7 MHz 254 604

In order to compare the architecture in high level (Matlab/Simulink) and hardware design (VHDL design)
the stimulus injected by the testbench in the DUT were the same applied in the high level block. The same
verification environment was used to validate the synthesized circuits. These stimulus were obtained from the
three outputs of a mash sigma-delta AD converter structure simulated in Simulink, see Fig. 2.

5. Conclusions
This paper showed the design, validation and synthesis results of a digital logic cancellation architecture
for a cascade Σ∆ AD converter. To achieve the CDMA and WLAN standard modes operation the quantization
noise in the operation frequency range must be reduced. It is provided by the increment of the system
modulator order.
The frequency requirement of the digital architecture, 160 MHz, was achieved for X-FAB XC06 standard
cells technology.
It was observed that the circuit power consumption can be reduced both in the analog and digital circuits
disabling modules when not needed.
The future works in the project will be the creation of a digital reconfigurable filter that will cover the three
standard operation modes of the proposed system modulator and the power consumption reduced disabling
analog and digital blocks when they are not being used.

6. References
[1] B. R. Jose, J. Mathew, P.Mythili and D. K. Pradhan, “A Multi-Mode Sigma-Delta ADC for
GSM/WCDMA/WLAN Applications”, J Sign Process Syst (2011) 62:117–130, DOI 10.1007/s11265-
008-0326-z.
[2] Andrea Xotta, Andrea Gerosa and Andrea Neviani, “A Multi-Mode Σ∆ Analog-to-Digital Converter for
GSM, UMTS and WLAN,” IEEE International Symposium on Circuits and Systems (ISCAS 2005),
May 2005, vol.3, pp. 2551-2554.
[3] Ling Zhang, Vinay Nadig and Mohammed Ismail, “A High Order Multi-Bit Σ∆ Modulator for Multi-
Standard Wireless Receiver”, IEEE International Midwest Symposium on Circuits and Systems
(MWSCAS 2004.) June , vol.3, pp. 379-382.
[4] B. Jalali-Farahani, and M. Ismail, “A Low Power Multi-Standard Sigma-delta ADC for
WCDMA/GSM/Bluetooth Applications,” IEEE Northeast Workshop on Circuits and Systems (NEWCAS
2004), June 2004, pp.241-243.
[5] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC
topology,” Electronics Letters , June 2001, vol. 37, no. 12, pp. 737-738.