Answer key – Model exam

Part A
1. What are the flags available in 8085 processor?
Various flags are : S (Sign flag), Z (Zero flag), AC (Auxiliary carry flag), P (Parity flag),
CY (Carry flag).
2. What are the interrupts available in 8085?
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.
3. Differentiate CALL instruction from JUMP instruction.
A JMP instruction permanently changes the program counter. A CALL instruction leaves
information on the stack so that the original program execution sequence can be resumed
4. Explain the function of CMP instruction.
CMP: - (compare register or memory with accumulator) The contents of the
operand register or memory are M compared with the contents of the accumulator.
Both contents are preserved . The result of the comparison is shown by setting the
zero flag of the PSW.
5. What is the significance of PSEN and EA pin in 8051 microcontroller?
Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a
signal from the external program memory. Pin 30 − This is EA pin which stands for
External Access input. It is used to enable/disable the external memory interfacing.

6. What are the main features of 8051 microcontroller?

 8-bit CPU.
 16-bit Program Counter.
 8-bit Processor Status Word (PSW)
 8-bit Stack Pointer.
 Internal RAM of 128bytes.
 Special Function Registers (SFRs) of 128 bytes.
 32 I/O pins arranged as four 8-bit ports (P0 - P3)
Two 16-bit timer/counters : T0 and T1.
7. Draw the command word format of 8255 in I/O mode.
 8. Name any two types of ADC.
Dual slope ADC.
Successive approximation ADC.
9. What is use of PSW register?
The program status word (PSW) register is an 8-bit register.It is also referred to as the flag
register. Although the PSW register is 8 bits wide, only 6 bits of it are used by the 8051.The
two unused bits are user-definable flags. Four of the flags are called conditional flags,
meaning that they indicate some conditions that result after an instruction is executed. These
four are CY (carry), AC (auxiliary carry), P (parity), and OV (overflow).As seen from
below figure, the bits PSW.3 and PSW.4 are designated as RS0 and RS1 as register
selection bit, respectively, and are used to change the bank registers.The PSW.5 and
PSW.l bits are general-purpose status flag bits and can be used by the programmer for any
purpose. In other words, they are user definable. See below Figure for the bits of the PSW
register
10. List out difference between MOV and MOVX instructions.
The MOV instruction moves data bytes between the two specified operands. The MOVX
instruction transfers data between the accumulator and external data memory.

PART-B
11(a) Explain with a neat block diagram, the architecture of 8085 microprocessor.

Control Unit
Generates signals within uP to carry out the instruction, which has been decoded. In reality
causes certain connections between blocks of the uP to be opened or closed, so that data goes
where it is required, and so that ALU operations occur. Arithmetic Logic Unit The ALU
performs the actual numerical and logic operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc.
Uses data from memory and from Accumulator to perform arithmetic. Always stores result of
operation in Accumulator.
Registers
The 8085/8080A-programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the
program counter. They are described briefly as follows. The 8085/8080A has six general-
purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the
figure. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit
operations. The programmer can use these registers to store or copy data into the registers by
using data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register
is used to store 8-bit data and to perform arithmetic and logical operations. The result of an
operation is stored in the accumulator. The accumulator is also identified as register A.
Flags
The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and
their bit positions in the flag register are shown in the Figure below. The most commonly
used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data
conditions.
Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit
register. The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the next
byte is to be fetched. When a byte (machine code) is being fetched, the program counter is
incremented by one to point to the next memory location Stack Pointer (SP)
General Purpose Registers
uP requires extra registers for versatility. Can be used to store additional data during a
program. More complex processors may have a variety of differently named registers.

(b)(i) Explain the interrupt structure of 8085 microprocessor.

INTERRUPTS OF 8085
An external device, initiates the hardware interrupts of 8O85 by placing an appropriate signal
at the interrupt pin of the processor. The processor keeps on checking the interrupt pins at the
second T -state of last machine cycle of every instruction. If the processor finds a valid
interrupt signal and if the interrupt is unmasked and enabled, then the processor accepts the
interrupt. The acceptance of the interrupt is acknowledged by sending an INTA signal to the
interrupted device.
The processor saves the content of PC (program Counter) in stack and then loads the vector
address of the interrupt in PC. (If the interrupt is non-vectored, then the interrupting device
has to supply the address of ISR when it receives INTA signal). It starts executing ISR in this
address. At the end of ISR, a return instruction, RET will be placed. When the processor
executes the RET instruction, it POP the content of top of stack to PC. Thus the processor
control returns to main program after servicing interrupt. The hardware interrupts of 8085 are
TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
Further the interrupts may be classified into VECTORED / NON-VECTORED and
MASKABLE / NON-MASKABLE INTERRUPTS.
VECTORED INTERRUPT
In vectored interrupts, the processor automatically branches to the specific address in
response to an interrupt.
NON-VECTORED INTERRUPT
But in non-vectored interrupts the interrupted device should give the address of the interrupt
service routine (ISR).
The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has
to supply the address of ISR after receiving interrupt acknowledge signal.
MASKABLE & NON-MASKABLE INETRRUPTS
The hardware vectored interrupts are classified into maskable and non-maskable interrupts. •
TRAP is non-maskable interrupt
RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt. Masking is preventing the interrupt
from disturbing the main program. When an interrupt is masked the processor will not accept
the interrupt signal. The interrupts can be masked by moving an appropriate data (or code) to
accumulator and then executing SIM instruction. (SIM - Set Interrupt Mask). The status of
maskable interrupts can be read into accumulator by executing RIM instruction (RIM - Read
Interrupt Mask). All the hardware interrupts, except TRAP are disabled, when the processor
is resetted. They can also be disabled by executing Dl instruction. (Dl-Disable Interrupt).
When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST 5.5,
RST 6.5 and RST 7.5 are disabled by DI instruction and upon hardware reset).
To enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-
Enable Interrupt). The type of signal that has to be placed on the interrupt pin of hardware
interrupts of 8085 are defined by INTEL.
The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal
has to make a low to high transition and then it has to remain high until the interrupt is
recognized. • The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5,
the interrupt signal has to make a low to high transition an it need not remain high until it is
recognized.
The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts the
interrupting signal should remain high, until it is recognized.

(ii) Draw the timing diagram for I/O read and write machine cycles.
 11. (a) Explain the addressing modes of 8085 microprocessor with example for each.

ADDRESSING MODES OF 8085

Every instruction of a program has to operate on a data.
The method of specifying the data to be operated by the instruction is called Addressing.
The 8085 has the following 5 different types of addressing.
1. Immediate Addressing 2. Direct Addressing 3. Register Addressing 4. Register
Indirect Addressing 5. Implied Addressing

1. Immediate Addressing:
In immediate addressing mode, the data is specified in the instruction itself. The data will be
a part of the program instruction.
EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H.
2. Direct Addressing:
In direct addressing mode, the address of the data is specified in the instruction. The data will
be in memory. In this addressing mode, the program instructions and data can be stored in
different memory.
EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator;
SHLD 3000H
3. Register Addressing:
In register addressing mode, the instruction specifies the name of the register in which the
data is available.
EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.
4. Register Indirect Addressing:
In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. Here the data will be in memory and the address
will be in the register pair.
EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B.
5. Implied Addressing:
In implied addressing mode, the instruction itself specifies the data to be operated.
EX. CMA - Complement the content of accumulator; RAL

(b) Write an 8085 assembly language program to multiply two numbers in memory locations
2200 and 2201. Store the product in memory locations 2300 and 2301.

2000 LHLD 2200 H←2200, L←2201

2003 XCHG H↔D, L↔E
2004 MOV C, D C←D
2005 MVI D 00 D←00
2007 LXI H 0000 H←00, L←00
200A DAD D HL←HL+DE
200B DCR C C←C-1
200C JNZ 200A If Zero Flag=0, goto 200A
200F SHLD 3050 H→2300, L→2301
 2012 HLT

13.(a) Explain with a neat diagram the architecture of 8051 microcontroller.

Following diagram is 8051 Microcontroller architecture . Let us have a look at each part or
block of this Architecture of microcontroller.

Central Processor Unit (CPU)

As we know that the CPU is the brain of any processing device of the microcontroller. It
monitors and controls all operations that are performed on the Microcontroller units.
The User has no control over the work of the CPU directly . It reads program written in
ROM memory and executes them and do the expected task of that application.

Memory

Microcontroller requires a program which is a collection of instructions. This program tells

microcontroller to do specific tasks. These programs require a memory on which these can be
saved and read by Microcontroller to perform specific operations of a particular task. The
memory which is used to store the program of the microcontroller is known as code memory
or Program memory of applications. It is known as ROM memory of microcontroller also
requires a memory to store data or operands temporarily of the micro controller. The data
memory of the 8051 is used to store data temporarily for operation is known RAM memory.
8051 microcontroller has 4K of code memory or program memory,that has 4KB ROM and
also 128 bytes of data memory of RAM.
BUS

Basically Bus is a collection of wires which work as a communication channel or medium for
transfer of Data. These buses consists of 8, 16 or more wires of the microcontroller. Thus,
these can carry 8 bits,16 bits simultaneously. Hire two types of buses that are shown in below

 Address Bus
 Data Bus

Address Bus: Microcontroller 8051 has a 16 bit address bus for transferring the data. It is
used to address memory locations and to transfer the address from CPU to Memory of the
microcontroller. It has four addressing modes that are

 Immediate addressing modes.

 Bank address (or) Register addressing mode.
 Direct Addressing mode.
 Register indirect addressing mode.

Data Bus: Microcontroller 8051 has 8 bits of the data bus, which is used to carry data of
particular applications.

Oscillator

Generally, we know that the microcontroller is a device, therefore it requires clock pulses for
its operation of microcontroller applications. For this purpose, microcontroller 8051 has an
on-chip oscillator which works as a clock source for Central Processing Unit of the
microcontroller. The output pulses of oscillator are stable. Therefore, it enables synchronized
work of all parts of the 8051 Microcontroller.

Input/Output Port

Normally microcontroller is used in embedded systems to control the operation of machines

in the microcontroller. Therefore, to connect it to other machines, devices or peripherals we
require I/O interfacing ports in the microcontroller interface. For this purpose
microcontroller 8051 has 4 input, output ports to connect it to the other peripherals

Timers/Counters

8051 microcontroller has two 16 bit timers and counters. These counters are again divided
into a 8 bit register. The timers are used for measurement of intervals to determine the pulse
width of pulses.

(b)Explain the I/O ports and their functions of 8051 microcontroller.

Port 0

Port-0 can be used as a normal bidirectional I/O port or it can be used for address/data
interfacing for accessing external memory. When control is ‘1’, the port is used for
address/data interfacing. When the control is ‘0’, the port can be used as a bidirectional I/O
port.
PORT 0 as an Input Port

Let us assume that control is ‘0’. When the port is used as an input port, ‘1’ is written to the
latch. In this situation both the output MOSFETs are ‘off’. Hence the output pin have floats
hence whatever data written on pin is directly read by read pin.

PORT 0 as an Output Port

Suppose we want to write 1 on pin of Port 0, a ‘1’ written to the latch which turns ‘off’ the
lower FET while due to ‘0’ control signal upper FET also turns off as shown in fig. above.
Here we wants logic ‘1’ on pin but we getting floating value so to convert that floating value
into logic ‘1’ we need to connect the pull up resistor parallel to upper FET . This is the reason
why we needed to connect pull up resistor to port 0 when we want to initialize port 0 as
an output port .

If we want to write ‘0’ on pin of port 0 , when ‘0’ is written to the latch, the pin is pulled
down by the lower FET. Hence the output becomes zero.

When the control is ‘1’, address/data bus controls the output driver FETs. If the address/data
bus (internal) is ‘0’, the upper FET is ‘off’ and the lower FET is ‘on’. The output becomes
‘0’. If the address/data bus is ‘1’, the upper FET is ‘on’ and the lower FET is ‘off’. Hence the
output is ‘1’. Hence for normal address/data interfacing (for external memory access) no pull-
up resistors are required.Port-0 latch is written to with 1’s when used for external memory
access.

PORT 1

Port-1 dedicated only for I/O interfacing. When used as output port, not needed to connect
additional pull-up resistor like port 0. It have provided internally pull-up resistor as shown in
fig. below. The pin is pulled up or down through internal pull-up when we want to initialize
as an output port. To use port-1 as input port, ‘1’ has to be written to the latch. In this input
mode when ‘1’ is written to the pin by the external device then it read fine. But when ‘0’ is
written to the pin by the external device then the external source must sink current due to
internal pull-up. If the external device is not able to sink the current the pin voltage may rise,
leading to a possible wrong reading.
PORT 2:

Port-2 we use for higher external address byte or a normal input/output port. The I/O
operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for
external memory access.

Here again due to internal pull-up there is limited current driving capability.

PORT 3:

Following are the alternate functions of port 3:

P3.0—–RXD

P3.1—– TXD

P3.2—– INT0 BAR

P3.3—– INT1 BAR

P3.4—– T0
P3.5—– T1

P3.6—– WR BAR

P3.7—– RD BAR

It works as an IO port same like Port 2 as well as it can do lots of alternate work which are
discuss above. Only alternate function of port 3 makes its architecture different than other
ports.

14.(a)With neat diagram, explain the architecture and features of 8279 Keyboard display
controller.
I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D is
low. Its data buffer interfaces the external bus of the system with the internal bus of the
microprocessor. The pins A0, RD, and WR are used for command, status or data read/write
operations.

Control and Timing Register and Timing Control

This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation of
the circuit.

Scan Counter

It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the
keyboard and display.

In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is
directly transferred to the sensor RAM along with SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed
key is entered into the RAM as per their sequence. The status logic generates an interrupt
request after each FIFO read operation till the FIFO gets empty.

In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded
with the status of their corresponding row of sensors into the matrix. When the sensor
changes its state, the IRQ line changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word currently
read/written by the CPU to/from the display RAM.

(b) Draw the block diagram of 8255 (PPI) and explain its various operating modes.
 The parallel input-output port chip 8255 is also called as programmable peripheral
input- output port. The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher
capability microprocessors.

It has 24 input/output lines which may be individually programmed in two groups of twelve
lines each, or three groups of eight lines. The two groups of I/O pins are named as Group A
and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit
port and another subgroup of four lines or a 4-bit port.

Thus Group A contains an 8-bit port A along with a 4-bit port. C upper. The port A lines are
identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly,
Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits
PC0- PC3. The port C upper and port C lower can be used in combination as an 8-bit port C.
Both the port C are assigned the same address. Thus one may have either three 8-bit I/O ports
or two 8-bit and two 4-bit ports from 8255. All of these ports can function independently
either as input or as output ports. This can be achieved by programming the bits of an internal
register of 8255 called as control word register (CWR). This buffer receives or transmits data
upon the execution of input or output instructions by the microprocessor. The control words
or status information is also transferred through the buffer.

15.(a) Explain the washing machine control using 8051 and write a program for the same.
AT89S51 microcontroller is used to control the process of washing cycle and to drive the
external output devices such as water inlet valve, wash motor, water drain valve. The control
strategy program for AT89S51 microcontroller is implemented by using assembly language.
The objectives of this development are to design a simple control system using low cost
microcontroller, to construct the functions of system using simple control system. The main
abstraction of this research is to improve control and software systems of microcontroller
based process simple control system in Electronics

Washing machines are a common feature today in the Indian household. The most important
utility a customer can derive from a washing machine is that he saves the effort he/she had to
put in brushing, agitating and washing the cloth. Most of the people wouldn’t have noticed
(but can reason out very well) that different type of cloth need different amount of washing
time which depends directly on the type of dirt, amount of dirt, cloth quality etc. The
washing machines that are used today (the one not using fuzzy logic control) serves all the
purpose of washing, but which cloth needs what amount of agitation time is a business which
has not been dealt with properly. In most of the cases either the user is compelled to give all
the cloth same agitation or is provided with a restricted amount of control. The thing is that
the washing machines used are not as automatic as they should be and can be. This
paperaims at presenting the idea of controlling the washing tim e using fuzzy logic control.
The paper describes the procedure that can be used to get a suitable
washing time for different cloths. The process is based entirely on the principle of taking non-
precise inputs from the sensors, subjecting them to fuzzy arithmetic and obtaining a crisp
value of the washing time. It is quite clear from the paper itself that
this method can be used in practice to further automate the washing machines. Never the less,
this method, though with much larger number of input parameters and further complex
situations, is being used by the giants like LG and Samsung.
Problem Definition When one uses a washing machine, the person generally select the length
of wash time based on the
amount of clothes he/she wish to wash and the type and
degree of dirt cloths have. To automate this process, we use sensors to detect these
parameters i.e. volume of clothes, degree and type of dirt). The wash time is then determined
from this data. Unfortunately, there is no easy way to formulate a precise mathematical
relationship between volume of clothes and dirt and the length of wash time required.
Consequently, this problem has remained unsolved until very recently. Conventionally,
people simply set wash times by hand and from personal trial and error experience. Washing
machines were not as automatic as they could be. The sensor system provides external input
signals into the machine from
which decisions can be made. It is the controller's responsibility to make the decisions and to
signal the outside world by some form of output. Because the input/output relationship is not
clear, the design of a washing machine controller has not in the past lent itself to traditional
methods of control design. We address this design problem using fuzzy logic. Fuzzy logic
has been used because a fuzzy logic controlled washing machine controller gives the correct
wash time even though a precise model of the
input/output relationship is not available.

(b)Explain the different types of instructions set used in 8051 microcontroller.

 PART-C (1*15=15 Marks)
16.(a) Explain the interfacing concept of analog to digital conversion with 8085
microprocessor.
DC 0809

The ADC0808, ADC0809 data acquisition component is a Monolithic CMOS device with an
8-bit analog-to-digital converter,8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive approximations the conversion
technique. The converter features a high impedance chopper stabilized comparator, a 256R
voltage divider with analog switch tree and a successive approximation register.

INTERFACING ADC 0809 WITH 8085

8085 microprocessor it doesn’t have an On chip ADC to accept the digital input, it will not
accept analog input, so we need a ADC to process the analog signal. For interfacing ADC
0809 we require 8 data lines.

So ADC 0809 is an 8 bit ADC has 8 channels works on successive approximation conversion
technique

(b) Explain how to control a stepper motor using 8051 microcontroller with a neat
interfacing diagram and assembly program.
Stepper motor.

Stepper motor is a brush less motor which converts electrical pulses into mechanical rotation.
As the name indicates it rotates in steps according to the input pulses. A stepper motor
usually have a number of field coils (phases) and a toothed rotor. The step size of the motor is
determined by the number of phases and the number of teeth on the rotor. Step size is the
angular displacement of the rotor in one step. If a stepper motor has 4 phases and 50 teeth, it
takes 50×4=200 steps to make one complete rotation. So step angle will be 360/200=1.8°.

The stepper motor we are using has 4 poles and a 1/64 reduction gear mechanism for
increasing torque. The step angle of the motor is 5.64°. But when considering the reduction
gear, the step angle of the output shaft is 5.64/64°. The internal schematic of the stepper
motor is given below.

The stepper motor is rotated by switching individual phases ON for a given time one by one.
The sequence is given in the graph below.
The circuit diagram for interfacing stepper motor to 8051 is shown above. P1.0, P1.1,
P1.2 and P1.3 pins are used for controlling the phases A1, A2, A3 and A4 of the stepper
motor respectively. ULN2003 is used for driving the individual phases of the stepper motor.
ULN2003 is a darlington transistor array used for driving high current loads such as relays
and motors. ULN2003 has 8 individual channels each with 1A capacity. The channels can be
paralleled to increase the current capacity. Each channels are fitted with individual
freewheeling diodes. The ULN2003 is operated in current sinking mode. Each channel is
activated by giving a logic LOW at the corresponding input. For example if we make pin 1
of ULN2003 LOW, phase A1 of the stepper motor gets switched ON.

Program.
A1 EQU P1.0
A2 EQU P1.1
A3 EQU P1.2
A4 EQU P1.3
ORG 00H
MOV TMOD,#00000001B

MAIN:
CLR A1
ACALL DELAY
SETB A1

CLR A2
ACALL DELAY
SETB A2
CLR A3
ACALL DELAY
SETB A3

CLR A4
ACALL DELAY
SETB A4
SJMP MAIN
DELAY:MOV R6,#1D
BACK: MOV TH0,#00000000B
MOV TL0,#00000000B
SETB TR0
HERE2: JNB TF0,HERE2
CLR TR0
CLR TF0
DJNZ R6,BACK
RET
END

The program first clears P1.0 for activating phase 1 (A1) of the stepper motor. This condition
is maintained for 65mS and then P1.0 is set for deactivating phase 1 of the motor. Then the
same process is repeated for the port pins P1.1 to P1.3 and the entire cycle is repeated over
and over to make the motor rotate in the clockwise direction.

Timer 0 of the microcontroller is configured in Mode1 for producing the 65mS delay. 65mS
is the width of each control pulse.