CS221 Digital Design Techniques School of Computer Science

Course Outline
Introduction [1] – PWN
CMOS circuit design [3] – EWH(2)/PWN(1)
Layout [2] – EWH
CMOS fabrication [2] – EWH
Scaling [2] – EWH
Power, speed and space compromises [2] – EWH
Circuit simulation [1] – EWH
Sequential system design using ASM charts [3] – PWN
Implementation choices & digital design with programmable
logic devices [3] – PWN
System design for arithmetic operations [3] – PWN
Examples Classes [2] – EWH/PWN

http://www.cs.manchester.ac.uk/Study_subweb/Ugrad/coursenotes/CS2212/

These lectures are concerned with the physical layout of a CMOS circuit.

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 CS221 Digital Design Techniques School of Computer Science

Lectures 5 and 6:Layout

Lecture aims

• to understand the requirements for design rules

• to understand stick diagrams
• to translate simple circuit designs to layout

The main aims of this lecture are to compare circuit level and logic level
simulation and to understand the requirements of a simple circuit simulation
netlist. The requirements of circuit models and the need to extract parameters
from the circuit schematic and layout will also be discussed.

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Layout Design Rules

• Designs are represented by geometries on

specific layers
• Each layer in the layout represents a process
during manufacture
• Design rules set the limitations on the layout
geometries
• They are a consequence of the methods
used to manufacture the devices

We will now look at the layout of our devices in more detail and look at how we
can develop a set of scaleable design rules. We represent the stages in
manufacture as a set of layers in the design process. Each layer has a set of
geometries (polygons etc) which represent the features to be reproduced at that
stage of the process.

It is clear that we must have a set of minimum feature sizes for each layer and a
set of values for minimum spacing between features on each layer and between
features on different layers. These are our layout design rules. The values for
these minimum sizes depend on the particular process being used to manufacture
the chip.

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Layout Layers

• Modern CMOS processing is complex

• Need to abstract out a basic set of conceptual
layout levels
– Two different substrates (n-well, p-well)
– Active regions for drain and source
– Transistor gate electrodes
– Interconnection paths
– Interlayer contacts

Modern CMOS processes involve many layers. Some of which can remain
hidden from the design engineer and some of which are critical in the design
process.

In order to simplify the problem for the layout design we abstract out a basic set
of conceptual layout levels. Any one level could involve several processes in the
manufacture of the devices. The main layers required in our abstract layout levels
are given above. Two substrates for the two types of transistor to be produced are
required. These can represent separate n and p – wells or could represent a n-well
in an p-substrate. We then need to define the active regions for our drain and
source connections. Following this we must have gate electrodes defined in
poly(silicon). Finally we need interconnection paths in metal and interlayer
contacts.

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Layer Representation

The layers may be represented as:

– A suitable colour scheme
– Varying shading or stipple patterns
– Varying line styles
– A combination of the above

There are various ways we can represent the layers. You will see this if you look
a different books on VLSI design. The methods used depend on whether a colour
scheme is used or fill patterns or line styles. In some cases a mixture of these is
used to improve clarity.

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Typical n-Well CMOS layers

LAYER COLOUR SYMBOLIC
N-well Brown
Thin-oxide Green N-transistor
Poly Red Polysilicon
P+ Yellow P-transistor
Metal1 Light Blue Metal1
Metal2 Tan Metal2
Contact-cut, Black Contact
Via
Metal3 Grey Metal3
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A typical set of layers for a simple n-well CMOS process is given above for
illustration. The basic layers are present as discussed previously. Most modern
CMOS processes involve more layers, but have the same fundamental layers as
described here.

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 CS221 Digital Design Techniques School of Computer Science

CMOS Inverter Layout

n - well
VDD
diffusion (Active)
λ grid source of pull-up poly(silicon)
threshold implant
gate of pull-up
p+ diffusion
drain of pull-up metal 1 to
diffusion/poly
Vin Vout contact cut
drain of pull-down metal 1
gate of pull-down
metal 2 to metal 1
source of pull-down contact cut
metal 2
VSS

Here we show the layout of a simple inverter. Both p- and n-channel devices have
the same minimum sized transistor. The layout is placed on a grid with a
dimension equal to the minimum resolution of the process (λ). Since any feature
has two opposite edges that need to be resolved, the minimum feature size is 2λ.
The length of the transistor channel is equal to this minimum size and is the width
of the polysilicon used to define the gate.

Note that metal1 is used to connect power to source of pull-up and source to
ground of pull-down device. Metal1 also forms the output connection from the
source of the pull-up and the drain of the pull-down. Note also the substrate and
n-well connections to VSS and VDD respectively.

It is also important to overlap the active regions with the gate poly by at least 2λ
to prevent any drain-source short circuits.

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Design Rules and Minimum features

• Minimum feature size 2λ – defined by resolution

of process
• Need smallest dimension to be length of
transistor channel
• Width of poly defines length of transistor channel
• Thus min. width of poly should be 2λ
• For smallest transistor L = 2λ
• Current carrying capacity determined by width W
= 3λ for min area device

The minimum sized transistor will always have its channel length at the
minimum feature size. The width of the channel is usually constrained to be 1.5
times the channel length for a minimum area transistor.This allows for at least λ
spacing from contact cuts and metalisation to active edge for contact to the active
area. This spacing allows the alignment between these layers to be maintained
within the resolution of the process.

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MOSIS Scaleable Design Rules

Lambda
Rule Description
SCMOS SUBM DEEP
1.1 Minimum width 10 12 12
Minimum spacing between
1.2 9 18 18
wells at different potential
Minimum spacing between
1.3 6 6 6
wells at same potential
Minimum spacing between
1.4 wells of different type (if 0 0 0
both are drawn)

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Stick Diagrams

• Abstract out design rules

• Orientation and relative position
• No actual dimensions
• Need to add transistor sizes
• Provides a simple method for design
compaction
• Some CAD systems have a sticks like input

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Stick diagrams give spacial positions and orientation without actual dimensions.
We thus abstract away the layout design rules. We can start with the circuit
layout and use sticks to produce the transistors. We can then look for ways of
reorienting the transistors to make design more compact and save on
interconnect. It is then only necessary to flesh out the sticks in accordance with
the layout rules and the chosen transistor dimensions to obtain the layout.

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 CS221 Digital Design Techniques School of Computer Science

Inverter stick diagram

Vdd Well contact
s
Vdd Key

g 1/1 1/1 Contact Cut

p-device
Metal1 to
d Metal2 Cut
a q a q Metal 1
d
n-device
g Metal 2
1/1
1/1 Active
s
Vss Poly
Vss N well
Substrate contact
There is no space metric (dimensions) thus no layout
design rules.

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In order to translate from circuits to the layout required on each process layer we
go via an intermediate form called stick diagrams. The stick diagram indicates
the features required on the conducting layers and the connections between them.
The example given is for a simple inverter. Transistorareas are denoted by
diffusion (green) which indicates the doped (n or p) semiconductor ACTIVE
region. PMOS transistors are differentiated from NMOS by a surrounding black
dashed line which denotes the n-well required to make the p-channel device (n
type substrate) and the distinct implant it requires to set its threshold voltage.

The polysilicon (red) gate is physically above the active diffusion area and
separated from it by the thin oxide layer. Poly and diffusion can connect to the
metal1 layer (blue) above them via the contact cuts (black squares) which
represents a hole through the thick oxide layer that separates them. Metal 1 flows
into this hole to make the connection. The output is normally on metal1. The
power and ground are in metal2 (dashed tan) and cannot connect directly to the
active regions. They are connected via metal1. It is a good idea to mark the
transistor W/L dimensions on the stick diagram. Note only make very short
connections in poly and diffusion – massive performance penalty if longer lines
are used in these layers.

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Flesh out stick diagram

n - well
VDD
diffusion (Active)
λ grid source of pull-up poly(silicon)
threshold implant
gate of pull-up
p+ diffusion
drain of pull-up metal 1 to
diffusion/poly
Vin Vout contact cut
drain of pull-down metal 1
gate of pull-down
metal 2 to metal 1
source of pull-down contact cut
metal 2
VSS
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We can now flesh out the stick diagram to produce the layout, but must obey the
design rules. These rules ensure that the features you specify are fabricated and
will not cause open or short circuits. Layout design rules are usually specified in
terms of l, the fabrication process resolution. In general, min. size of feature on
any layer may be 2l x 2l, but upper layers may be 3l x 3l because of the increased
surface roughness for these layers. Min. distance between featurs on a layer tends
to be 2l. Overlap of conducting materials with a contact cut tends to be l all round
to ensure adequate contact area. Polysilicon external to gate area is separated
from diffusion by 2l to avoid parasitic capacitance and extends 2l beyond gate
area to avoid drain-source shorts.

Typical values of l are 0.1mm or less for cutting edge commercial processes.
Although the rules for different manufacturers are similar there is always some
re-working of layout required when designs are ported between silicon vendors.

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 CS221 Digital Design Techniques School of Computer Science

Sticks layout exercise

Draw a circuit diagram for a complex CMOS gate which
performs the following logic function:

Q = A.C +B

Now draw the stick diagram for this gate.

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Alternative layout
Well contact
Key
Vdd
Contact Cut
1/1

Metal 1
a q
Metal 2
1/1 Active
Poly
Vss
N well
Substrate contact

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The main advantage of using stick diagrams is that alternative layouts can be
examined quickly.

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Actual Layout - Inverter

A protection diode is placed
on the gate here.

Allows selection of oxide

This is a local interconnect layer
thickness providing the source and drain
connections only
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The actual layout for a modern process can be more complex. Here is an inverter
laid out in the process you use in the laboratory exercise. Note the protection
diode which is needed in this process for all gates to prevent damage from static
during processing. Note also there is an extra mask layer that allows the optional
definition of a different oxide layer thickness. This is used for 3.3V devices. The
local interconnect layer (lil) is a tungsten layer which allows easy local
connections for Vdd and Vss to the active regions. It can also be used for p to n
device drain connections.

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Actual Layout – NOR2x2

Drive strength 2
Inputs 2

M3 M4 Vdd
M4

M3
Z
Z M2
M1 A
M1
Jogs M2
B
Vss

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This is a highly optimised gate and as such the layout is much more difficult to
follow. Notice the use of 45 degree jogs on the gates to increase the equivalent
transistor width.

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Actual Layout – AND2

Inverter

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Draw the circuit diagram and mark on the transistors – then label up the layout.

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Actual Layout – Complex gate

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What is the function of this gate?

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Actual Layout – Complex gate

Z
A B
B C

A + B.C

Parallel gates are drive strength 2 devices

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What is the function of this gate?

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 CS221 Digital Design Techniques School of Computer Science

Example complex gate stick layout

Vdd
Key
Vdd Contact Cut
a
c b Metal1 to
Metal2 Cut
b
Metal 1
d
a q
q Metal 2
a
b
c Active
c
d Poly
d
Vss
Vss
N well

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Possible solutions to sticks layout problem

Vdd Vdd

a
c a
q
b q
b
q
a
b c a c
b
c Vss

Vss Minimises poly wire

Simplest solution interconnect

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