UNIT IV:

Modeling of Sequential
Circuits

CpE 425 Digital Systems Design 1

 Unit Outline
● Commonly used sequential circuit constructs
● Sequential circuits in Verilog
● Comparison between combinational and sequential circuit
descriptions

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Latches, Flip-flops and Registers
● Use of same behavioral construct, but change in sensitivity
list.
● All sequential circuits must have clock signal.
● Latches and flip-flops differ in the clock sensitivity.
– Latches are level-sensitive (positive or negative level)
– Flip-flops are edge-sensitive (positive/rising or negative/falling
edge)
● If D and Q are more than 1 bit wide, they are usually called
registers and are edge-sensitive

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Positive-level D Latch

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Testbench for D Latch

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Results

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 Positive-edged D Flip-flop
See the difference in the sensitivity
list

If negative-edged
triggered:

always @ (negedge Clk)

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Compare Waveforms
Positive-level triggered D Latch

Positive-edged triggered D Flip-flop

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 Exercise
● Create the following flip-flop types:
– JK Flip-flop (use case statements)
– T Flip-flop (use if statements)

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 Reset
● It is common practice to have a reset signal for easy
initialization.

● Reset signal is usually low-asserted (active-low) by

convention.

● Synthesis tools usually have strict format flip-flops.

● Two types: synchronous and asynchronous resets

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Synchronous vs. Asynchronous

See the difference in the sensitivity list

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Compare Waveforms
Synchronous (Active Low) Reset

Asynchronous (Active Low) Reset

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 Enable
● Many circuits require a
flip-flop/register to hold a
value for more than a clock
cycle, controlled by an
enable signal.

● In Verilog,
incompletely-specified if-else
and case statements produce
a latch.

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Incorporating Logic

A 0
D Q Q
B 1 nReset

Sel

nReset Clk

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Blocking vs. Non-blocking
c D Q y
a x

Clk

c
D Q y
a
D Q
b x

Clk

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 Combinational vs. Sequential
● Clearly identify which parts of your circuit are
combinational and which parts are sequential.

● For combinational circuits, always completely specify

conditional statements (to avoid inferring a latch).

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Combinational vs. Sequential

c
a y

b x

c D Q y
a x

Clk

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 Exercise
1.) Write a description for an
8-bit shift register that has a
serial input Sin and output Sout.
It also has 8 parallel inputs, Din
(7 downto 0). It is
synchronously loaded from these
inputs when its Load input is
asserted (active high). It also has
a synchronous active low reset
input nReset. When its ShiftR
input is asserted (active high), it
shifts its contents one position to
the right at the next positive
edge at its Clk input.
CpE 425 Digital Systems Design
2.) Write a description of a 4-bit
up counter named counter4.
The counter increments on a
positive clock edge only if its
active low enable (nE) is
asserted. If its cntby2 input is
asserted (active high), the
counter increments by 2;
otherwise, it increments by 1. If
the counter overflows, it
continues to count starting from
0000. The counter has an
active-low asynchronous reset
(nReset).
18
 References
● Introduction to HDL, USC-PIIC Workshop Manual
● M. Morris Mano and Michael D. Ciletti, “Digital Design with
an Introduction to the Verilog HDL”, 5th edition
● www.asic-world.com

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