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Fujitsu MB90F387S

16-bit MCU
An Introduction: I/O Control
About MB90385 Series

• MB90387/387S/F387/F387S/MB90V495G

• general-purpose high-performance 16-bit micro


controllers designed for process control of
consumer products, which require high-speed
real-time processing
About MB90385 Series
• inheriting the architecture of F2MC (Fujitsu Flexible
Microcontroller) family, employs additional
instruction ready for high-level languages,
expanded addressing mode, enhanced multiply-
divide instructions and enriched bit-processing
instructions

• 32-bit accumulator achieves processing of long-


word data (32 bits)

• High performance RISC CPU


Peripheral Features
• 8/10-bit A/D converter

• UART (SCI)

• 8/16-bit PPG timer

• 16-bit input-output timer (16-bit free-run timer,


input capture 0, 1, 2, 3 (ICU))

• CAN controller
Features
• Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL clocks) is allowed among


frequency division by two on oscillation clock, and 

multiplication of 1 to 4 times of oscillation clock (for 4-MHz
oscillation clock, 4 MHz to 16 MHz).

• Operation by sub-clock (8.192 kHz) is allowed.

• Minimum execution time of instruction: 62.5 ns (when


operating with 4-MHz oscillation clock, and 4-time multiplied
PLL clock).
Features
• 16 Mbyte CPU memory space

• 24-bit internal addressing

• Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator


Features
• Instruction system compatible with high-level language (C
language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

• Increased processing speed

• 4-byte instruction queue

• Powerful interrupt function with 8 levels and 34 factors


Features
• Automatic data transfer function independent of CPU

• Expanded intelligent I/O service function (EI2 OS): Maximum of 16


channels

• Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock, subclock,


time-base timer and clock timer only)

• Clock mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode


Features
• Process

• CMOS technology

• I/O port

• General-purpose input/output port (CMOS output) :

• MB90387S, MB90F387S : 36 ports (including 4 high-current output ports)

• Timer

• Time-base timer, clock timer, watchdog timer: 1 channel

• 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels

• 16-bit reload timer: 2 channels


Features
• Timer

• 16-bit input/output timer

• 16-bit free run timer: 1 channel

• 16-bit input capture: (ICU): 4 channels

• Interrupt request is issued upon latching a count value of 16-bit free run timer by
detection of an edge on pin input.

• CAN controller: 1 channel

• Compliant with Ver2.0A and Ver2.0B CAN specifications

• 8 built-in message buffers

• Transmission rate of 10 Kbps to 1 Mbps (by 16 MHz machine clock)

• CAN wake-up
Features
• UART (SCI): 1 channel

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is


available

• DTP/External interrupt: 4 channels, CAN wakeup: 1channel

• Module for activation of expanded intelligent I/O service


(EI2OS), and generation of external interrupt.

• Delay interrupt generator module

• Generates interrupt request for task switching.


Features
• 8/10-bit A/D converter: 8 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time: 6.125 μs (at 16-MHz machine


clock, including sampling time)

• Program patch function

• Address matching detection for 2 address pointers.


■ PIN ASSIGNMENT

Package & Pin-out (TOP VIEW)

P42/SOT1
P41/SCK1
X1A/P36*
X0A/P35*

P40/SIN1
P44/RX
P43/TX
AVSS

P33
P32
P31
P30
48
47
46
45
44
43
42
41
40
39
38
37
AVCC 1 36 P17/PPG3
AVR 2 35 P16/PPG2
P50/AN0 3 34 P15/PPG1
P51/AN1 4 33 P14/PPG0
P52/AN2 5 32 P13/IN3
P53/AN3 6 31 P12/IN2
P54/AN4 7 30 P11/IN1
P55/AN5 8 29 P10/IN0
P56/AN6 9 28 X1
P57/AN7 10 27 X0
P37/ADTG 11 26 C
P20/TIN0 12 25 VSS
13
14
15
16
17
18
19
20
21
22
23
24
P21/TOT0
P22/TIN1
P23/TOT1
P24/INT4
P25/INT5
P26/INT6
P27/INT7
MD2
MD1
MD0
RST
VCC

(FPT-48P-M26)
Package: FT-48P-M26
MB90385 Series
Pin Description
■ PIN DESCRIPTION
Circuit
Pin No. Pin name Function
type
1 AVcc  Vcc power input pin for A/D converter.
2 AVR  Power (Vref+) input pin for A/D converter. Use as input for Vcc or lower.
P50 to P57 General-purpose input/output ports.
3 to 10 E Functions as analog input pin for A/D converter. Valid when analog
AN0 to AN7
input setting is “enabled.”
P37 General-purpose input/output ports.
11 D Function as an external trigger input pin for A/D converter. Use the pin by
ADTG
setting as input port.
P20 General-purpose input/output ports.
12 D Function as an event input pin for reload timer 0. Use the pin by setting as
TIN0
input port.
P21 General-purpose input/output ports.
13 D Function as an event output pin for reload timer 0. Valid only when output
TOT0
setting is “enabled.”
P22 General-purpose input/output ports.
14 D Function as an event input pin for reload timer 1. Use the pin by setting as
TIN1
input port.
P23 General-purpose input/output ports.
15 D Function as an event output pin for reload timer 1. Valid only when output
TOT1
setting is “enabled.”
P24 to P27 General-purpose input/output ports.
16 to 19 D
INT4 to INT7 Functions as external interrupt input pin. Use the pin by setting as input port.
13 D Function as an event output pin for reload timer 0. Valid only when output
TOT0
setting is “enabled.”
P22 General-purpose input/output ports.
14 D

Pin Description
Function as an event input pin for reload timer 1. Use the pin by setting as
TIN1
input port.
P23 General-purpose input/output ports.
15 D Function as an event output pin for reload timer 1. Valid only when output
TOT1
setting is “enabled.”
P24 to P27 General-purpose input/output ports.
16 to 19 D
INT4 to INT7 Functions as external interrupt input pin. Use the pin by setting as input port.
20 MD2 F Input pin for specifying operation mode. Connect directly to Vss.
21 MD1 C Input pin for specifying operation mode. Connect directly to Vcc.
22 MD0 C Input pin for specifying operation mode. Connect directly to Vcc.
23 RST B External reset input pin.
24 Vcc  Power source (5 V) input pin.
25 Vss  Power source (0 V) input pin.
Capacitor pin for stabilizing power source. Connect a ceramic capacitor of
26 C 
approximately 0.1 µF.
27 X0 A Pin for high-rate oscillation.
28 X1 A Pin for high-rate oscillation.
P10 to P13 General-purpose input/output ports.
29 to 32 D Functions as trigger input pins of input capture channels 0 to 3. Use the
IN0 to IN3
pins by setting as input ports.
(Continued)

7
Pin Description
MB90385 Series

(Continued)
Circuit
Pin No. Pin name Function
type
P14 to P17 General-purpose input/output ports. High-current output ports.
33 to 36 G Functions as output pin of PPG timers 01 and 23. Valid when output
PPG0 to PPG3
setting is “enabled.”
P40 General-purpose input/output port.
37 D
SIN1 Serial data input pin for UART. Use the pin by setting as input port.
P41 General-purpose input/output port.
38 D Serial clock input pin for UART. Valid only when serial clock input/output
SCK1
setting on UART is “enabled.”
P42 General-purpose input/output port.
39 D Serial data input pin for UART. Valid only when serial data input/output set-
SOT1
ting on UART is “enabled.”
P43 General-purpose input/output port.
40 D Transmission output pin for CAN. Valid only when output setting is
TX
“enabled.”
P44 General-purpose input/output port.
41 D Transmission output pin for CAN. Valid only when output setting is
RX
“enabled.”
42 to 45 P30 to P33 D General-purpose input/output ports.
X0A* Pin for low-rate oscillation.
46 A
P35* General-purpose input/output port.
X1A* Pin for low-rate oscillation.
47 A
P36* General-purpose input/output port.
48 AVss  Vss power source input pin for A/D converter.
* : MB90387, MB90F387 : X1A, X0A
MB90387S, MB90F387S: P36, P35
MB90385 Series

Block Diagram
■ BLOCK DIAGRAM

X0,X1 Clock CPU


RST F MC-16LX core
2
X0A,X1A
control circuit

Clock timer
16-bit
Time-base timer free-run timer

Input
capture IN0 to IN3
RAM (4ch)

16-bit
ROM/FLASH
PPG timer

Internal data bus


PPG0 to PPG3
(2ch)

Prescaler
RX
CAN TX
SOT1
SCK1 UART1
SIN1
DTP/External INT4 to INT7
interrupt
AVcc
AVss 8/10-bit A/D 16-bit TIN0,TIN1
AN0 to AN7 converter (8ch) reload timer
(2ch) TOT0,TOT1
AVR
ADTG
■ MEMORY MAP
MB90385 series allows specifying a memory access mode “single chip mode.”

Memory Map
1. Memory allocation of MB90385
MB90385 series model has 24-bit wide internal address bus and up to 24-bit bus of external address bus.
A maximum of 16 Mbyte memory space of external access memory is accessible.
2. Memory map
(with ROM mirroring
function enabled)

000000H Peripheral
0000C0H
000100H RAM area
Register
Address #1

003800H Extension IO
area
004000H
ROM area
(FF bank image)
010000H

FE0000H
ROM area*
FF0000H
ROM area
FFFFFFH

Model Address #1
MB90V495G 001900 H
MB90F387/S 000900 H
MB90387/S 000900 H

: Internal access memory


: Access disallowed
* : On MB90387/S or MB90F387/S, to read “FE0000H” to “FEFFFFH” is to read out
“FF0000H” to “FFFFFFH”.

Note : When internal ROM is operating, F2MC-16LX allows viewing ROM data image on FF bank at upper-level of
00 bank. This function is called “mirroring ROM,” which allows effective use of C compiler small model.
F2MC-16LX assigns the same low order 16-bit address to FF bank and 00 bank, which allows referencing
MB90385 Series

■ I/O MAP
I/O Map
Register Read/
Address abbreviation Register Resource Initial value
Write
000000H (Reserved area) *
000001H PDR1 Port 1 data register R/W Port 1 XXXXXXXXB
000002H PDR2 Port 2 data register R/W Port 2 XXXXXXXXB
000003H PDR3 Port 3 data register R/W Port 3 XXXXXXXXB
000004H PDR4 Port 4 data register R/W Port 4 XXXXXXXXB
000005H PDR5 Port 5 data register R/W Port 5 XXXXXXXXB
000006H
to (Reserved area) *
000010H
000011H DDR1 Port 1 direction data register R/W Port 1 00000000B
000012H DDR2 Port 2 direction data register R/W Port 2 00000000B
000013H DDR3 Port 3 direction data register R/W Port 3 000X0000B
000014H DDR4 Port 4 direction data register R/W Port 4 XXX00000B
000015H DDR5 Port 5 direction data register R/W Port 5 00000000B
000016H
to (Reserved area) *
00001AH
8/10-bit
00001BH ADER Analog input permission register R/W 11111111B
A/D converter
00001CH
to (Reserved area) *
000025H
000026H SMR1 Serial mode register 1 R/W 00000000B
000027H SCR1 Serial control register 1 R/W, W 00000100B
For more
SIDR1/
of the I/O Map, see data sheet
Serial input data register 1/ Serial UART1 page 15
000028H R, W XXXXXXXXB
SODR1 output data register 1
000029H SSR1 Serial status data register 1 R, R/W 00001000B
MB90385 Series

■ I/O MAP
I/O Map
Register Read/
Address abbreviation Register Resource Initial value
Write
000000H (Reserved area) *
000001H PDR1 Port 1 data register R/W Port 1 XXXXXXXXB
000002H PDR2 Port 2 data register R/W Port 2 XXXXXXXXB
000003H PDR3 Port 3 data register R/W Port 3 XXXXXXXXB I/O Data
000004H PDR4 Port 4 data register R/W Port 4 XXXXXXXXB Registers
000005H PDR5 Port 5 data register R/W Port 5 XXXXXXXXB
000006H
to (Reserved area) *
000010H
000011H DDR1 Port 1 direction data register R/W Port 1 00000000B
000012H DDR2 Port 2 direction data register R/W Port 2 00000000B I/O Port
000013H DDR3 Port 3 direction data register R/W Port 3 000X0000B Direction
000014H DDR4 Port 4 direction data register R/W Port 4 XXX00000B Registers
000015H DDR5 Port 5 direction data register R/W Port 5 00000000B
000016H
to (Reserved area) *
00001AH
8/10-bit
00001BH ADER Analog input permission register R/W 11111111B
A/D converter
00001CH
to (Reserved area) *
000025H
000026H SMR1 Serial mode register 1 R/W 00000000B
000027H SCR1 Serial control register 1 R/W, W 00000100B
For more
SIDR1/
of the I/O Map, see data sheet
Serial input data register 1/ Serial UART1 page 15
000028H R, W XXXXXXXXB
SODR1 output data register 1
000029H SSR1 Serial status data register 1 R, R/W 00001000B
Interrupt Sources
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
MB90385 Series

EI2OS Interrupt vector Interrupt control register


Interrupt source Priority*3
readiness Number Address ICR Address
Reset × #08 08H FFFFDCH   High
INT 9 instruction × #09 09H FFFFD8H   ↑
Exceptional treatment × #10 0AH FFFFD4H  
CAN controller reception
× #11 0BH FFFFD0H
completed (RX)
CAN controller transmission ICR00 0000B0H*1
completed (TX) / Node status × #12 0CH FFFFCCH
transition (NS)
Reserved × #13 0DH FFFFC8H
ICR01 0000B1H
Reserved × #14 0EH FFFFC4H
CAN wakeup ∆ #15 0FH FFFFC0H
ICR02 0000B2H*1
Time-base timer × #16 10H FFFFBCH
16-bit reload timer 0 ∆ #17 11H FFFFB8H
ICR03 0000B3H*1
8/10-bit A/D converter ∆ #18 12H FFFFB4H
16-bit free-run timer overflow ∆ #19 13H FFFFB0H
ICR04 0000B4H*1
Reserved × #20 14H FFFFACH
Reserved × #21 15H FFFFA8H
ICR05 0000B5H*2
PPG timer ch0, ch1 underflow × #22 16H FFFFA4H
Input capture 0-input ∆ #23 17H FFFFA0H
ICR06 0000B6H*1
External interrupt (INT4/INT5) ∆ #24 18H FFFF9CH
Input capture 1-input ∆ #25 19H FFFF98H
ICR07 0000B7H*1
PPG timer ch2, ch3 underflow × #26 1AH FFFF94H
External interrupt (INT6/INT7) ∆ #27 1BH FFFF90H
ICR08 0000B8H*1
Clock timer ∆ #28 1CH FFFF8CH
Reserved × #29 1DH FFFF88H
Input capture 2-input ICR09 0000B9H*1
For more of the Interrupt
Input capture 3-input
× Sources,
#30 1E see data sheet page 23
FFFF84 H H

Reserved × #31 1FH FFFF80H


ICR10 0000BAH*1
I/O Control
• To send and receive signals through the I/O
ports, the registers involving the control of the
GPIO ports shall be configured.

• The following example will show how to


configure a port and send/receive a signal.

• For more information about the electrical and DC


characteristics of the I/O ports, see page 58 of
the data sheet
Configuring GPIO
• There are 5 GPIO ports in the MB90F387S. Each
port has 8 pins and it follows the convention Pxy
where x is the GPIO port number and y is the
pin/bit number. Therefore P10 is Port 1 pin/bit 0.

Port 1
7 6 5 4 3 2 1 0

P10
Configuring I/O
• Registers

• PDR (Port Data Register) - readable/writable register to I/O store


data

• DDR (Data Direction Register) - controls the direction of each of


the port’s pins

PDRx
7 6 5 4 3 2 1 0

DDRx
7 6 5 4 3 2 1 0

- where x is the port number


Registers are the memory areas to control microcomputer operation and retain microcomputer
operation status. Writing data to, and reading data from registers enables you to control the
CPU and peripheral functions of the microcomputer. Here, the term peripheral functions

Configuring I/O
means the functions of the I-O ports, timers, and A/D converter incorporated in the
microcomputer.

- For input setting, this register is used to check the input level
bit 7 6 5 4 3 2 1 0
of each pin (value read from the bit corresponding to each
PDR1 register
pin: 0 [low-level input] or 1 [high-level input]).
IO_PDR1.byte
- For output setting, this register is used to set the output level
Pin name P17 P16 P15 P14 P13 P12 P11 P10
of each pin (value written to the bit corresponding to each
pin: 0 [low-level output] or 1 [high-level output]).
bit 7 6 5 4 3 2 1 0
DDR1 register - This register is used to specify whether each port (pin) is

IO_DDR1.byte used for input or output (value written to the bit

Pin name P17 P16 P15 P14 P13 P12 P11 P10 corresponding to each pin: 0 [input] or 1 [output]).

Example of P10 setting


Input setting (DDR1 bit0 = 0) Output setting (DDR1 bit0 = 1)
PDR1 bit0 When 0 is read Low-level input When 0 is written Low-level output
When 1 is read High-level input When 1 is written High-level output

Figure 2.6 Explanation of registers to control the output from P10 to P14
LED and the LED is off. In the case of (b) in Figure 2.5, the signal output from pin P10 is at
the low level. Therefore, a current flows through the LED, and the LED goes on. The

Exercise
switch in the microcomputer can be operated by a program that controls the microcomputer.

Figure 2.4 Actual circuit diagram


Configure the P10-P14 to output and P16-P17 as input.

DDR1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Blinking LED
Configure I/O Ports

LED OFF

DELAY

LED ON

DELAY
Exercise

• Write a detailed flow chart based on the figure


on the previous slide.

• To assign value to a register use the following


format: REG <- 0xA2 (hexadecimal)

• Do not detail the delay routine.


Assignment Readings

• Read the Hardware Manual of the Fujitsu I/O


Configuration