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Published in IET Generation, Transmission & Distribution
Received on 4th March 2011
Revised on 8th August 2011
doi: 10.1049/iet-gtd.2011.0189

ISSN 1751-8687

Improved phase-locked loop for robust and fast

tracking of three phases under unbalanced
electric grid conditions
M.E. Meral
Department of Electrical and Electronics Engineering, Yuzuncu Yıl University, Van, Turkey
E-mail: emeralm@yahoo.com

Abstract: Modern electric power transmission and distribution systems need accurate phase information on three-phase grid
voltages and/or currents. Conventional three-phase synchronous reference frame-based phase-locked loop (SRF-PLL) is
generally sufficient for phase tracking during balanced operating conditions. However, SRF-PLL becomes inadequate when
unbalance exists in the three-phase input signal. Because, unbalance in input signal set causes a double-frequency ripple and
as a result, an ideal output signal cannot be obtained. Previous studies have focused on improving the SRF-PLL performance
by removing this ripple with using delayed signals methods such as delayed signal cancellation (DSC)-PLL methods. Although
these methods give ideal output signals, a certain time delay is occurred. In this study, an effective method DIF-PLL based on
adding another signal, which has reverse polarity ripple is proposed for obtaining ideal output signal and fast tracking of phase
angle. Performance of the DIF-PLL is compared with the performances of SRF-PLL and DSC-PLL methods. The performances
of these methods are also examined for the presence of the harmonics. The results show that the proposed method has a better
three-phase tracking performance than the others under balanced and unbalanced electric grid conditions.

1 Introduction
Most of the electric power system voltage and/or current
signals are in the form of three phase sinusoidal signals. A
set of three-phase signals is balanced when the three signals
have equal magnitudes and 120 phase-displacements,
otherwise they are unbalanced [1]. Modern power-
electronic-based applications used in power transmission
and distribution systems need accurate phase information on
the grid voltages and/or currents. Because, phase detecting
take an important role in providing a reference phase
signals synchronised with the AC power system for
controlling of all AC/DC or DC/AC converters used in
these applications. Examples of such applications are
flexible AC transmission system (FACTS) devices, high-
voltage DC (HVDC) power transmission systems, custom
power (CP) devices for distribution systems and various
power-electronic converter topologies for electrical drives,
etc. The phase-detecting procedure for these applications is
given in Fig. 1.
To achieve phase detecting, there are many different
methods that can be employed [2–4]. The simplest is zero-
crossing method [5]. This method finds the zero-crossing
points of the voltage/or currents in order to determine the
phase information. However, this technique is not
satisfactory because the phase information can only be
detected at each half-cycle, which considerably slows its
performance. Even if they are better than the zero-crossing
method, methods based on low-pass filters, space vector
filters [6], Kalman filters [7] or the Fourier transforms [8] do
not have the best performance under distorted supply
conditions [9]. Phase-looked loop (PLL) technique based on
the synchronous reference frame (SRF-PLL), is the most
comprehensive method under distorted supply conditions [10].
The conventional SRF-PLL is a closed-loop control system
that drives error signal to zero when the phase angle it
generates is equal to the phase angle of the input signal [9].
The basic scheme of such a PLL is shown in Fig. 2. Based
on a feedback structure, the PLL structure comprises a
phase detector, loop filter and voltage-controlled oscillator.
The simplicity of this structure makes this synchronisation
method the most widely accepted solution for analogue and
digital implementations.
The SRF-PLL is generally sufficient for removing
distortion during balanced operating conditions. However,
this method becomes inadequate when unbalance exists in
the three-phase input signal [11]. Because, unbalance in the
three-phase input signal set causes a double-frequency
ripple in the error signal [12]. Owing to this ripple, the
produced unit sine/cosine output signals have not got an
ideal sinusoidal form. Various papers in the literature have
focused on improving the SRF-PLL by removing this
ripple. In [13], delayed signal cancellation (DSC) technique
is used to remove the double-frequency ripple. In [14], a
moving average filter (MAF) is added to the SRF-PLL
algorithm for removing the ripple. The basic idea of both of
these methods is adding time-delayed signal/signals to the
original error signal. Although these methods give ideal

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signals [16] caused by unbalanced conditions are analysed
in this section:
The unbalanced three-phase utility signals (pu) can be
given as follows

Sa = ∂ sin(ua )
Sb = ∂(1 + b) sin(ua − 2p/3) (1)
Sc = ∂(1 + g) sin(ua + 2p/3)

where ∂ is the peak value of sinusoidal signals, b and g are the

constants expressing increased or decreased values on phases,
and ua is the original phase angle of three-phase signal set.
These signals can be written in the stationary frame
Fig. 1 Phase-detecting procedure for power-electronic based using (23)
applications 
2 1
Sa = ∂ sin(ua ) − (1 + b) sin(ua − 2p/3)
3 2

1
− (1 + g) sin(ua + 2p/3)
2
 √ (2)
2 3
Sb = ∂ 0 + (1 + b) sin(ua − 2p/3)
3 2
√ 
3
− (1 + g) sin(ua + 2p/3)
2

Fig. 2 Basic scheme of a PLL After simplification procedures

 
output sine signals, because of the added time-delaying g+b b−g
signals, a certain time delay occurred [10]. However, as an Sa = ∂ sin(ua ) + ∂ sin(ua ) + √ cos(ua )
6 2 3
alternative moving average method is proposed in [15] and   (3)
an MAF is used in the process to extract angular frequency. g+b b−g
Sb = −∂ cos(ua ) − ∂ cos(ua ) + √ sin(ua )
In this paper, an effective method based on adding 2 2 3
another signal that has reverse polarity ripple to the original
ripple of the error signal is proposed for an ideal output If (3) is applied to (25), (4) can be obtained.
sine signal and fast tracking of phase angle. The details of
the conventional SRF-PLL, the improved SRF-PLL   
methods: the delaying signal methods and the proposed b+g b−g
Sd = sin(ua ) + sin(ua ) + √ cos(ua ) ∂ cos(up )
method are given in below sections. As an important 6 2 3
benefit to researchers concerned with the stationary and   
synchronous frames, the conditions of ab and dq signals in b+g b−g
case of fault caused to unbalance signals are presented. The − cos(ua ) + cos(ua ) + √ sin(ua ) ∂ sin(up )
2 2 3
performances of the presented methods are also examined
  
for the presence of the harmonics in the grid voltages/ b+g b−g
currents. Sq = − sin(ua ) + sin(ua ) + √ cos(ua ) ∂ sin(up )
6 2 3
  
2 Analysis for unbalanced utility conditions b+g b−g
− cos(ua ) + cos(ua ) + √ sin(ua ) ∂ cos(up )
For the control of various applications and devices used in 2 2 3
transmission and distribution systems, reference frame (4)
transforms have been developed. By using these transforms,
it is possible to express the three-phase signals with another Where, up is the phase angle produced by PLL. If the
reference frames such as stationary and synchronous. The assumption that the phase-angle tracking error of PLL is
basics of the reference frame transforms and equations for very small is taken into account (up  ua), after
these transforms (19) – (25) are presented in the Appendix simplification procedures, the (5)
section.
In practice, the three-phase voltages or currents are not  
b−g b+g
balanced because of various factors such as power system Sd = 0 + ∂ √ cos(2ua ) − sin(2ua )
faults, unbalanced three-phase loads, etc. The unbalanced 2 3 6
utility waveforms cause various types of the calculation/    
b+g b−g b+g
detection errors in the PLL system, which degrade the Sq = −∂ 1 + − ∂ √ sin(2ua ) + cos(2ua )
3 2 3 6
control performance of the utility interface devices such as
power-electronic converters. The errors of ab and dq (5)

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If general trigonometric equations are taken into account

   
b−g 2 b+g 2
Sd = 0 + ∂ √ +
2 3 6
× {cos(2ua ) cos(uu ) − sin(2ua ) sin(uu )}
⎛ 
 2  2 (6)
b + g b − g b + g
Sq = −∂ − ∂⎝ −∂ √ +
3 2 3 6

× {sin(2ua ) cos(uu ) + cos(2ua ) sin(uu )}

 √
where, uu = tan−1 1/ 3 (b + g/b − g) . After some
simplification procedures (5) can be written as in (7)

   
b−g 2 b+g 2
Sd = 0 + ∂ √ + cos(2ua + uu )
2 3 6
   
  
b+g b−g 2 b+g 2
Sq = −∂ −∂ −∂ √ + sin(2ua + uu )
3 2 3 6 Fig. 4 Block diagrams of the improved SRF-PLLs
(7) a MAF-PLL and DSC-PLL methods in the literature
b Proposed DIF-PLL method

As seen from (6), Sd ¼ 0 and Sq ¼ 2∂ (negative peak value)

under balanced conditions. The summing terms of
(7 containing b, g, cos(2ua) and sin(2ua) represent the error
caused by unbalancing. It should be noted that ua ¼ wt and
the errors have 2w frequency ripples (100 Hz for 50 Hz
utility). There is 908 phase difference between ripples of
d and q signals.
3 Conventional phase locked loop method:
SRF-PLL
In the conventional SRF-PLL method, three-phase signal set
(this set may be obtained from three-phase voltages or
currents measurements) is converted from its natural abc
frame to the stationary ab frame with Clarke
transformations [17] and then processed by a PLL to
tracking three-phase angle and frequency.
The d component of the dq signal, representative of the error
signal, is then regulated to zero through the use of a proportional
integral (PI) controller of PLL. When the SRF-PLL generates a
phase angle that is equal to the phase angle of the input signal,
error signal becomes zero [14, 18]. The schematic diagram of a
conventional SRF-PLL is shown in Fig. 3.
4 Improved SRF-PLLs
The conventional SRF-PLL works well under balanced
electric grid conditions but during unbalance, its
performance becomes poorer because of ripple, which
analysed previous section. For an effective control of a
power device using PLL, the negative effects of unbalancing
on control signals should be removed. Various methods have
already been proposed in literature for accurate phase-angle
tracking under unbalanced conditions. These methods aimed
to eliminate double-frequency ripple of control signal. The
details of the methods reported in the literature and the
proposed method are given in following subsections.
4.1 Improved SRF-PLLs using time-delayed signals
There are two general approaches in the literature focused on
improving the SRF-PLL performance by removing the
double-frequency ripple. Both of these methods use time-
delayed signals to remove the ripple. Simplified block
diagram for both of the improved PLLs using time-delaying
signals is given in Fig. 4a.
In [13], the DSC technique is used to improve performance
of SRF-PLL (DSC-PLL) under unbalanced three-phase grid
conditions. If three phases are unbalanced in a 50 Hz
system then the 100 Hz ripples will appear in d- and q-axes
along with the DC quantities and cause erroneous
estimation of the phase angle of the three-phase signal set.
In this method, the d signal without ripple is calculated as
in (8)
1
Stds2(k+1) = (Sd(k) + Sd(k−Nd) ) (8)
2

Fig. 3 Block diagram of the conventional SRF-PLL method

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Table 1 Parameters for all PLL models
balanced three-phase Va ¼ 1/08, Vb ¼ 1/21208 and
voltages, pu Vc ¼ 1/1208
gains for PI regulator Kp ¼ 0.015 and Ki ¼ 0.5
where Nd is equal to fs/2fr; fs and fr are the sampling
frequency and frequency of ripple, respectively. Thus, the d
signal not containing ripple is obtained by adding the signal
at sample to the signal at sample that is delayed by 1/2 of the
ripple period.
Another improved method is MAF-based PLL (MAF-PLL)
method for the removing ripple [14]. If a classical low-
pass filter is used to remove the ripple, the system
response becomes slower. However, with the usage
of an MAF, faster system response and better attenuation
can be achieved according to a PLL using the low-pass
filter.
Transfer function of an MAF is discrete time domain can
be given by (9). If the signal containing 100 Hz component
and is sampled at a rate of 500 Hz and at every
computational instant average of five samples (delayed one
sample each other) is calculated then output would not
Fig. 5 Results for startup: (1) SRF-PLL error, (2) DSC-PLL error, (3) DIF-PLL error, (4) SRF-PLL output, (5) DSC-PLL output and
(6) DIF-PLL output
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contain 100 Hz ripple [14].
Stds1 (z) 1
= H(z) = (1 + z−1 + z−2 + · · · + z−4 ) (9)
Sd (z) 5
4.2 Proposed improved SRF-PLL
Block diagram of the proposed new SRF-PLL is depicted in
Fig. 4b. The proposed method is based on adding another
signal, which has reverse polarity ripple to the original
ripple of the d signal. It may be taken into account that a
reverse polarity ripple can be produced by 1808 phase
shifting for sinusoidal signals. But such a method will be
causing to time delay. In addition, for distorted sinusoidal
signals this method will not give accurate results. In this
paper, an improved SRF-PLL method using differentiating
(DIF-PLL) is proposed for removing the ripple.
Assume that, for an unbalanced three-phase signal set, Sd
and Sq signals are as following (similar to the (7))
Sd = K cos(2wt + uu )
(10)
Sq = C − K sin(2wt + uu )
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where C is a constant and K is a coefficient as given in (7).
The derivative of Sq is found as

dSq
= −K2w cos(2wt + uu ) (11)
dt

If (10) and (11) are taken into account, with the following
operation, the ripple of the d signal can be eliminated

1 dSq
Sdif = Sd + =0 (12)
2w dt

As can be seen from (12), the error signal does not contain the
ripple.
The discrete time procedure of the proposed PLL method is
explained through following steps:
† Transform the three-phase signal set of Sa(k) , Sb(k) and Sc(k)
to ab frame and obtain; the signals Sa(k) and Sb(k) .
† Transform the signal set from ab frame to dq frame and
obtain the signals Sd(k) and Sq(k) .
† Find the derivative of Sq(k) , add to Sd(k) and obtain Sdif(k):

1 (Sq(k) − Sq(k−1) )
Sdif (k) = + Sd(k) (13)
2w(k−1) Ts

Fig. 6 Results for single phase-to-ground fault: (1) SRF-PLL † Subtract Sd0 from Sdif(k) , find the error signal Serr(k) and use
error, (2) DSC-PLL error and (3) DIF-PLL error the error as input of the PI regulator to calculate the change in

Fig. 7 Results for phase-to-phase fault: (1) SRF-PLL error, (2) DSC-PLL error, (3) DIF-PLL error, (4) SRF-PLL output, (5) DSC-PLL output
and (6) DIF-PLL output

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Fig. 8 Frequency and phase signals for SRF-PLL, DSC-PLL and DIF-PLL methods
the angular frequency
Dw(k) = kp Serr (k) + ki Ts Serr (k)
Fig. 9 Results for phase-to-phase fault in case of presence of
harmonics: (1) SRF-PLL error, (2) DSC-PLL error and (3) DIF-
PLL error
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† Add the reference angular frequency w0 and obtain angular
frequency w(k)
(14) w(k) = Dw(k) + w0 (15)
† Use integrator and obtain estimated phase angle up(k)
up(k) = up(k−1) + Ts w(k−1) (16)
† Use integrator and obtain estimated phase angle up(k)
up(k) = up(k−1) + Ts w(k−1) (17)
† Use the Sa(k+1) , Sb(k+1) and up(k) obtained from above
procedure to calculate Sd(k+1) and Sq(k+1)
Sd(k+1) = cos(up(k+1) )Sa(k+1) + sin(up(k+1) )Sb(k+1)
(18)
Sq(k+1) = −sin(up(k+1) )Sa(k+1) + cos(up(k+1) )Sb(k+1)
5 Phase-tracking performances of classical
and improved SRF-PLLs
In this section, several simulation results are presented in
order to verify the analysis reported in the previous sections
and to compare of the presented PLLs. The compared
methods are the proposed PLL method (DIF-PLL), the
improved PLL method (DSC-PLL) and the conventional
PLL method (SRF-PLL).
These results were obtained from simulation models of the
presented PLLs created in PSCAD/EMTDC which is a fast
and accurate power system simulation software for the design
and verification of all types of power systems and power
system control. The parameters used in the simulation
models are given in Table 1. Except the start-up of the PLLs,
the DSC-PLL and the MAF-PLL methods have similar
performances (the DSC-PLL has better performance for
start-up). Therefore only the results of the DSC-PLL and the
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conventional SRF-PLL are used to compare with the proposed
DIF-PLL method in order to avoid too many simulation results.
5.1 Startup of PLLs
The startup case is presented in order to evaluate the phase-
locking process. The results for error signals (error of d
signal) and PLL outputs related with this case are given in
Fig. 5. These results show that, as stated in (7), the steady-
state error is zero for balanced conditions. With the error
signal results, it is possible to observe that the settling time
of the DIF-PLL is smaller than the settling time of the
DSC-PLL. The DSC-PLL method has longer settling time.
Same observations can be obtained with the results of
output signals.
5.2 Unbalancing caused by single phase-to-
ground fault
In order to evaluate the performances of the PLLs under
unbalanced conditions, firstly a single phase-to-ground fault
considered.
At t1 ¼ 500 ms, the phase B voltage decreases to 50% of
nominal (b ¼ 20.5 and g ¼ 0). The fault ends at
t2 ¼ 700 ms. Error signal results related with this case are
given in Fig. 6. As can be seen from this figure, the error
signal has the double-frequency ripple during unbalancing
Fig. 10 Frequency and phase signals for SRF-PLL, DSC-PLL and DIF-PLL methods and input three-phase signals
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with the SRF-PLL method. The DSC-PLL method provides
an improvement, but there are still small control errors at
starting and ending times. The proposed DIF-PLL method
maintains the error signal at zero level.
5.3 Unbalancing caused by phase-to-phase fault
The performances of the PLLs in the case of unbalancing
caused by phase-to-phase fault are shown in this case. At
t3 ¼ 805 ms, the phase B and phase C voltages decrease to
45% of their nominal (b ¼ 20.55 and g ¼ 20.55) and
phase shift occur between these voltages. The results for
error signals and PLL output are given in Fig. 7.
According to results shown in Fig. 7, it is possible to
observe that the output of the SRF-PLL is not an ideal sine
signal. The DSC-PLL has an ideal signal after the settling,
but there is a time delay for settling. During this delay
period, the DSC-PLL output can not give desired results.
The DIF-PLL method has better results. The results show
that, the proposed method has almost an ideal output sine
signal.
Phase and frequency signals obtained with SRF-PLL,
DSC-PLL and DIF-PLL are shown in Fig. 8. As seen from
this figure, the signals obtained with SRF-PLL are affected
negatively by the unbalancing. Phase shift and frequency
fluctuations are occurred in signals. In the DSC-PLL
method, the phase and frequency signals are delayed to
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Table 2 Time periods for the settling of the error signal
Cases Time periods for the settling of
error signal Serr, ms
SRF-PLL DSC-PLL DIF-PLL
startup of PLLs 80 140 80
unbalancing caused by single (ripple) 45 –50 0–5
phase-to-ground fault
unbalancing caused by (ripple) 115–120 0–5
phase-to-phase fault
arrive to actual values. However, the signals of the proposed
SRF-PLL are not affected by the unbalancing.
5.4 Effects of harmonics to performances of the
PLLs
The cause of the voltage/current harmonics can be considered
as the non-linear loads or the non-linearities of the devices
used for measurements. In [16], the utility voltages with
harmonics are analysed and it is reported that the voltage/
current harmonics causes the error of PLL control signals
with the frequency components of 6w, 12w, which is the
multiples of six of the utility frequency. For example, the
value of the Sd signal is 0 and the value of the Sq signal is
2∂ (negative peak value) under normal conditions. When
utility signal contains fifth to seventh harmonics, these
signals will have contained cos(6ua) components.
In order to test the performances of the PLLs in case of
harmonics, the three-phase signals are assumed with 5.0%
THD (fifth harmonics that is 4.5% of fundamental and
seventh harmonics that is 2.2% of fundamental) in this
case. At t3 ¼ 805 ms, the phase A and phase C voltages
decrease to 45% of their nominal with phase shift. The
results in case of presence of the harmonics are shown in
Figs. 9 and 10.
In Fig. 9, the error signal results related with this case are
given. As seen from this figure, error signal of the
conventional PLL method has 6w frequency ripples because
of harmonics at normal conditions. The proposed method is
much less affected by harmonics. At normal conditions,
DSC-PLL does not affect the harmonics, but it is affected
by harmonics at fault condition.
Three-phase input signals, phase detecting and frequency
signals obtained with SRF-PLL, DSC-PLL and DIF-PLL
are shown in Fig. 10. The frequency signals of the all
methods negatively affected by the harmonics in case of
unbalanced fault. The other results are similar to the results
in Fig. 8. As a result, in case of presence of the harmonics,
it can be said that the DSC-PLL has a better performance
than the DIF-PLL at normal conditions, but the proposed
DIF-PLL method has a better performance under
unbalanced electric grid conditions.
5.5 Numerical results for the simulation cases
In Table 2, time periods of settling for the simulated cases are
given. The time period results show that the DIF-PLL method
has a faster tracking performance.
6 Conclusion
A new improved PLL for fast and robust tracking of the
three-phase voltages and/or currents under unbalanced grid
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conditions has been presented in this paper. The phase-
tracking errors caused by unbalancing have been analysed
comprehensively. The design considerations of the
conventional PLL and the improved PLLs as the solutions
of errors caused by unbalancing have been described.
Finally, the performances of presented PLLs have been
compared. The performances of these methods are also
examined for the presence of the harmonics. For the
unbalanced conditions, the results show that the DSC-PLL
method has a better performance than SRF-PLL, but its
settling time is longer at the start-up stage. In general, it can
be concluded that the proposed PLL method is faster than
the DSC-PLL and is robust than the SRF-PLL for all the
cases. The proposed PLL method has a better performance
than the others under balanced and unbalanced grid
conditions and it can be used modern power transmission
and distribution system devices such as FACTS, HVDC,
and various versions of power flow controllers.
7 References
1 Karimi-Ghartemani, M., Karimi, H.: ‘Processing of symmetrical
components in time-domain’, IEEE Trans. Power Syst., 2007, 22,
pp. 572–579
2 Song, H., Nam, K.: ‘Instantaneous phase-angle estimation algorithm
under unbalanced voltage-sag conditions’, Proc. Inst. Electr. Eng.,
2000, 147, pp. 409– 415
3 Yazdani, D., Bakhshai, A., Joos, G., Mojiri, M.: ‘A nonlinear adaptive
synchronization technique for grid-connected distributed energy
sources’, IEEE Trans. Power Electron., 2008, 23, pp. 2181– 2186
4 Yazdani, D., Mojiri, M., Bakhshai, A., Joos, G.: ‘A fast and accurate
synchronization technique for extraction of symmetrical components’,
IEEE Trans. Power Electron., 2009, 24, pp. 674–684
5 Singh, B., Al-Haddad, K., Chandra, A.: ‘A review of active filters for
power quality improvement’, IEEE Trans. Ind. Electron., 2001, 46,
pp. 960–971
6 Li, Y.W., Wu, B., Xu, D., Zargari, N.R.: ‘Space vector sequence
investigation and synchronization methods for active front-end
rectifiers in high-power current-source drives’, IEEE Trans. Ind.
Electron., 2008, 55, pp. 1022–1034
7 Cardoso, R., Camargo, R.F., Pinheiro, H., Grundling, H.A.: ‘Kalman
filter based synchronization methods’, IET Trans. Gener. Transm.
Distrib., 2008, 2, (4), pp. 542– 555
8 Lavopa, E., Zanchetta, P., Sumner, M., Cupertino, F.: ‘Real-time
estimation of fundamental frequency and harmonics for active shunt
power filters in aircraft electrical systems’, IEEE Trans. Ind. Electron.,
2009, 56, pp. 2875– 2884
9 Liccardo, F., Marino, P., Raimond, G.: ‘Robust and fast three-phase PLL
tracking system’, IEEE Trans. Ind. Electron., 2011, 58, (1),
pp. 221–231
10 Eren, S., Karimi-Ghartemani, M., Bakhshai, A.: ‘Enhancing the three-
phase synchronous reference frame PLL to remove unbalance and
harmonic errors’. Proc. IEEE Industrial Electronics, 35th Annual
Conf., 2009, pp. 437–441
11 Karimi-Ghartemani, M., Iravani, M.R.: ‘A method for synchronization
of power electronic converters in polluted and variable-frequency
environments’, IEEE Trans. Power Syst., 2004, 19, pp. 1263– 1270
12 Eren, S., Karimi-Gharteman, M., Bakhshai, A.: ‘Enhanced frequency-
adaptive phase-locked loop for distributed power generation system
applications’. Presented at the World Wind Energy Conf., Kingston,
Canada, 2008
13 Awad, H., Svensson, J., Bollen, M.J.: ‘Tuning software phase-locked
loop for series-connected converters’, IEEE Trans. Power Deliv.,
2005, 20, pp. 300–308
14 Ghoshal, A., Vinod, J.: ‘A method to improve PLL performance under
abnormal grid conditions’. Presented at the National Power Electronics
Conf., Bangalore, India, 2007
15 Salamah, A.M., Finney, S.J., Williams, B.W.: ‘Three-phase phase-
locked loop for distorted utilities’, IET Trans. Electr. Power Appl.,
2007, 1, (6), pp. 937 –945
16 Chung, S.K.: ‘Phase-locked loop for grid-connected three-phase power
conversion systems’, IET Trans. Electr. Power Appl., 2000, 147, (3),
pp. 213–219
17 Akagi, H., Kanazawa, Y., Nabae, A.: ‘Generalized theory of the
instantaneous reactive power in three-phase circuits’. Proc. IEEJ Int.
Power Electronics Conf., 1983, pp. 1375–1386
159
& The Institution of Engineering and Technology 2012
www.ietdl.org
18 Arruda, L.N., Silva, S.M., Filho, B.J.C.: ‘PLL structures for utility As a result
connected systems’. Proc. IEEE 36th Industry Applications Conf.,
2001, pp. 2655–2660 ⎡ ⎤
    Sa
19 Analog Devices Inc.: ‘ADSP-reference frame conversions’, available at: Sa 2 1 √1/2
 −1/2
√ ⎣ Sb ⎦
http://www.analog.com, 2002 = (23)
Sb 3 0 3/2 − 3/2
Sc
8 Appendix
In the space vector diagram, the axes of the space vector plane
It is possible to transform the three-phase (abc) system to an are stationary. Meanwhile the space vectors of the voltage
equivalent two-phase (ab) representation [19] and/or current rotate about these axes at a rate equal to the
angular frequencies of the corresponding phase quantities.
2 If instead a new reference frame is defined where the axes
Sab = [Sa + a.Sb + a2 .Sc ] (19) are made to rotate at the same rate as angular frequency of
3 the phase quantities, the space vector in this frame can be
given by
Sab = Sa + jSb (20)
Sdq = Sab e−ju = (Sa + jSb ){cos(u) − j sin(u)} = Sd + jSq
where, Sa , Sb and Sc are the time-dependent three-phase
signals (voltage or current) and a is a vector operator that (24)
produces vector rotation of angle 2p/3 and is defined as
This may also be written in matrix form as (park
a = e j2p/3 = cos(2p/3) + j sin(2p/3) (21) transformation)
    
Sd cos(u) sin(u) Sa
The transformation from three-phase to two-phase quantities = (25)
(Clarke transformation) can be written in matrix form as Sq −sin(u) cos(u) Sb

⎡ ⎤ where, the real component of the space vector in this

    S
Sa 2 1 cos(2p/3) cos(4p/3) ⎣ a ⎦ new reference frame is the direct axis component Sd while
= Sb (22) the imaginary component is called the quadrate axis
Sb 3 0 sin(2p/3) sin(4p/3)
Sc component Sq .

160 IET Gener. Transm. Distrib., 2012, Vol. 6, Iss. 2, pp. 152 –160
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-gtd.2011.0189