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1, JANUARY 2003 43

Full-CMOS 2-GHz WCDMA Direct Conversion

Transmitter and Receiver
Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park,
Kyeongho Lee, Deog-Kyoon Jeong, and Wonchan Kim

Abstract—This paper presents a full-CMOS transmitter and This paper is organized as follows. In Section II, the proposed
receiver for 2.0-GHz wide-band code division multiple access with direct conversion architecture is described and its problems and
direct conversion mixers and a dc-offset cancellation scheme. The proposed solutions are discussed. Section III describes various
direct conversion scheme combined with a multiphase sampling
fractional- prescaler alleviates the problems of the direct building blocks and circuits used to build the chip. Section IV
conversion transmitter and receiver. Digital gain control is merged shows experimental results from a 0.35- m CMOS implemen-
into the baseband filters and variable-gain amplifiers to optimize tation, and Section V concludes the paper.
the linearity of the system, reduce the noise, and improve the
sensitivity. Variable-gain amplifiers with dc-offset cancellation
loop eliminate the dc-offset in each stage. The chip implemented II. SYSTEM ARCHITECTURE
in 0.35- m CMOS technology shows the experimental results
of 6 dBm maximum output power with 38-dB adjacent channel The block diagram of the transmitter using the multiphase
power rejection ratio at 1.92 MHz, 50-dB dynamic range, and reduced frequency conversion architecture is shown in Fig. 1.
363-mW power consumption in the transmitter. The receiver The transmitter is composed of a 10-b digital-to-analog con-
shows 115.4 dBm sensitivity, a 4.0-dB noise figure, and a verter (DAC), a baseband filter with a tuning circuit, a vari-
dynamic range of 80-dB with 396-mW power consumption. able-gain amplifier (VGA), a quadrature upconverter, a pream-
Index Terms—Adjacent channel power rejection ratio (ACPR), plifier, and a frequency synthesizer. The 10-b DAC receives 10-b
dc-offset, direct conversion, fractional- prescaler, mixer, data from the baseband modem and operates at 32.768 mega
receiver, transmitter, wide-band code-division multiple access samples per second (Msps) performing four-time oversampling.
The baseband filter is tuned to a 3.84-MHz cutoff frequency by
the tuning circuit. The variable-gain amplifier is controlled dig-
I. INTRODUCTION itally by the baseband modem. The high-pass filter (HPF) sup-
press the dc-offset due to baseband circuits. The quadrature up-
R ECENTLY, CMOS RF integration has been widely
explored in the wireless communication area to save
cost, power, and chip area. The direct conversion architecture,
converter which is composed of two six-phase mixers receives
650-MHz-band 12-phase LO signals (LO[0:11]) from the fre-
rather than a more conventional super-heterodyne, has been quency synthesizer and receives I/Q baseband signals from the
an attractive choice for single-chip integration because of its VGAs. The quadrature upconverter offers the same function-
many advantages. However, the direct conversion architec- ality as the conventional one receiving a single-phase 2.0-GHz
ture has several fundamental problems to solve in achieving LO signal. The converter generates a 2.0-GHz modulated signal
performance comparable to a super-heterodyne counterpart. and sends its output to the preamplifier. The frequency synthe-
The dc-offset problem caused by local oscillator (LO) leakage sizer is composed of a 12-phase VCO, a fractional- prescaler,
is the most serious one. The multiphase reduced frequency a charge-pump, and a phase frequency detector. It generates a
conversion scheme was proposed as one of the candidates set of 700-MHz 12-phase LO signals (LO[0:11]) for the selected
to solve the dc-offset problem and to alleviate difficulty in channel frequency. LO and (LO ) signals are separated
obtaining the required phase noise level [1]. The multiphase by in time. A fractional- architecture is used
reduced frequency conversion scheme is incorporated in the to obtain a bandwidth large enough for fast lock time and low
design of a single-chip wide-band code division multiple access phase noise. A multiphase voltage-controlled oscillator (VCO)
(WCDMA) transmitter and a receiver and their experimental with a low center frequency is easier to design to meet the per-
results indicate conformity to the required commercial 2.0-GHz formance requirement of a high carrier frequency application.
WCDMA specification. Fig. 2 shows the architecture of the receiver which uses the
same multiphase reduced frequency conversion architecture.
The receiver is composed of a CMOS low-noise amplifier
Manuscript received February 19, 2002; revised July 17, 2002. (LNA), a quadrature downconverter, a frequency synthesizer,
K.-Y. Lee is with the Inter-University Semiconductor Research Center a VGA, a baseband filter with a tuning circuit, and two 6-b
(ISRC), Seoul National University, Seoul 151-742, Korea (e-mail:
kylee@griffin.snu.ac.kr). ADCs operating at the 32.768-Msps sampling rate. The 6-b
S.-W. Lee, J.-W. Lee, and K. Lee are with GCT Semiconductor, Inc., San analog-to-digital converters (ADCs) give enough precision
Jose, CA 95131 USA. headroom for efficient digital signal processing. The frequency
Y. Koo, H.-K. Huh, H.-Y. Nam, D.-K. Jeong, and W. Kim are with the School
of Electrical Engineering, Seoul National University, Seoul 151-742, Korea. synthesizer, like the one in the transmitter, generates 12-phase
Digital Object Identifier 10.1109/JSSC.2002.806280 LO signals (LO[0:11]) for different channel frequencies. The
0018-9200/03$17.00 © 2003 IEEE

Fig. 1. Transmitter architecture.

Fig. 2. Receiver architecture.

quadrature downconverter which is composed of two six-phase caused by the power/ground fluctuation and layout coupling,
mixers receives 700-MHz 12-phase LO signals. The baseband can generate a large amount of dc-offset on the output node
structure is composed of five stages of VGAs, two third-order of the downconversion mixer. However, in the multiphase
active-RC elliptic filters, a fifth-order elliptic filter, reduced frequency conversion receiver architecture, the VCO
and a fifth-order elliptic equalizer. frequency is far below the carrier frequency. As a result,
Fig. 3 shows the circuit diagram and explains how the the main power of LO leakage is not located at the carrier
dc-offset is suppressed in the multiphase reduced frequency frequency and the amount of dc-offset can be reduced. As
direct conversion receiver architecture. In the conventional shown in Fig. 3, the amount of dc-offset which appears as
architecture, the VCO frequency is equal to the carrier fre- in the multiphase reduced
quency. As a result, LO leakage terms , , and , frequency architecture, when high-frequency components

Fig. 3. DC-offset suppression in multiphase reduced frequency conversion receiver architecture.

are filtered, is significantly less than that of the conventional and RF_out and between VDD_INT and RF_outb. The gain
architecture, . control blocks in parallel with resonator loads use 20 PMOS
transistors used as programmable resistors which respond to
III. BUILDING BLOCKS 20-level gain control signals. The I and Q mixers are designed
to have high IIP3 in order not to degrade the adjacent channel
In the transmitter RF parts, the upconversion mixer and the power rejection ratio (ACPR). Since direct upconversion is
preamplifier convert and amplify the signal from the baseband used, side-band suppression is less important. This simplifies
block. The LNA and the quadrature mixers amplify and con- RF filtering and thus helps to reduce off-chip components.
vert the signal for the baseband block in the receiver. Baseband Nonetheless, great care has been taken to reduce I/Q LO signal
blocks include quadrature paths for filtering and controlled gain mismatches. The baseband I and Q signals and LO signals
in a merged manner. The digitally controllable analog front-end are closely matched to suppress the carrier leakage below the
allows flexibility in the overall radio system design [2]. The specification. The dc-offset which causes the carrier leakage is
tradeoff between noise and linearity in the baseband signal pro- also removed by a dc-offset correction circuit and a high-pass
cessing has been optimized using a merged filtering and con- filter (HPF).
trolled gain scheme before upconversion in the transmitter and Fig. 5 shows the gain-controlled pre-amplifier which drives
after the downconversion in the receiver. an external power amplifier. Because the output of the pream-
plifier is open-drain, the preamplifier requires an external RF
A. RF Blocks choke as a load. An external inductor with high Q is used as
1) Upconversion Mixer and Preamplifier: Fig. 4 shows a load. The preamplifier is designed to have high IIP3 to mini-
the circuit diagram of the quadrature upconverter using two mize the spurious components in the transmitter output and thus
six-phase double-balanced mixers, one for the I-channel and achieve high ACPR. The input signal level of Txin coming from
the other for the Q-channel. The baseband I and Q signals are the upconversion mixer is 8 dBm. The total gain control range
upconverted to RF differential signals, RF_out and RF_outb, is 34 dB with the gain step of 1 dB. Gain is controlled by pre-am-
by the quadrature mixer performing single-sideband modu- plifier gain control signals (Pre-amp gain ctrl1—Pre-amp gain
lation. The level of input signals from the baseband block, ctrl34) from the Tx gain control block. The total dc current is
Mixer_In_I, Mixer_Inb_I, Mixer_In_Q, and Mixer_Inb_Q, is 58 mA and the maximum output level is 6 dBm. To reduce gain
about 12 dBm and the common-mode dc level is 1.6 V. The step variation and improve linearity, gain control is allocated
total dc current consumed in this block is 13 mA. The total evenly between the upconversion mixer and the preamplifier.
gain control range is 20 dB and the gain step is 1 dB. The That is, to increase the overall gain, the preamplifier and upcon-
resonator load consists of , , , , and resistors. Gain version mixer gains are increased alternately until that of the
control is done by changing the resistance between VDD_INT upconversion mixer is saturated.

Fig. 4. Upconversion mixer.

Fig. 6 shows the circuit diagram of the LNA. The relationship

between and gain is described by

The LNA has a gain control step of 2 dB and the total gain
is 22 dB. This fine control of the LNA gain is advantageous
since the design margin for the following stages becomes re-
laxed. The LNA requires an external matching circuit composed
of and . Since the noise figure is quite sensitive to the
input matching circuit and loss in the input trace, the LNA input
matching should be carefully optimized for both desired noise
Fig. 5. Preamplifier.
figure and gain. However, since sensitivity is generally more
critical, the noise matching is preferred over the gain matching.
2) LNA and Downconversion Mixer: The LNA plays a key The LNA gain is controlled by the baseband modem according
role in determining the SNR of the overall system. Although to the RF input signal power to simultaneously meet the noise
high gain is desirable for better sensitivity under weak signal and linearity requirements of the system. The LNA in Fig. 6 uses
conditions, it is not desirable under strong signal conditions be- bond wire inductance for matching and cascode transistor
cause of intermodulation. In particular, in WCDMA applica- to isolate the resonator load from the input. The on-chip
tions, a high peak-to-average power ratio (PAR) requires an resonator load consists of a 1.95-nH inductor and a 2.5-pF
LNA with high linearity. The intermodulated signal is also re- capacitor . Because the LC load bandwidth has very narrow
garded as a noise and thus its level should be kept small so as not bandwidth, they are de-Qed with a 300- parallel resistor
to degrade the SNR. The LNA has a gain-control function to op- to achieve over the 600-MHz bandwidth with negligible degra-
timize both the noise and linearity under any signal conditions. dation in noise performance. Two 60-MHz frequency bands at

Fig. 6. LNA.

190-MHz duplex separation can be covered with this arrange-

ment and process variations have only a minor effect on the
low-Q resonator load [2]. The ac-coupling circuit composed
of and blocks the low-frequency noise and distortion
from the RF section and the LO inputs of the mixers. Hence
the low-frequency leakage into the mixer output comes mainly
from internal sources.
The output of the LNA is downconverted to baseband I and Q
signals by the quadrature mixer. The baseband signal is filtered
and amplified at the baseband rather than at the intermediate fre-
quency. This eliminates the need for an external image rejection
filter and the channel selection filter such as a bandpass SAW
filter. The image rejection filter and the costly SAW filter are re-
placed with an on-chip low-pass filter. The 12-phase quadrature
downconverter shown in Fig. 7 is composed of two six-phase
single balanced mixers, one for the I-channel and the other for Fig. 7. Downconversion mixer.
the Q-channel. Quadrature differential signals, I_out, I_outb,
Q_out, and Q_outb, are passed to the baseband through the HPF. and step size of each stage are shown in Fig. 8. The VGAs are
In a direct conversion receiver, most of the filtering is done after merged with the filters. Power detectors detect the power levels
downconversion and thus the mixer should have high linearity. of the output of the VGA and compare them with the reference
The low noise figure is also important in the mixer design since level. The gain control block receives the power detect signals
the overall noise figure is raised if the mixer noise is too high. (PD) and sets the gain control signals with the help of the base-
The I and Q mixers are designed to have high IIP3 so as not to band modem. Fine gain control is achieved with a resolution of
degrade SNR. The conversion gain is 7.6 dB and IIP3 is 4 dB. To 0.5 dB. The gain step of each VGA stage is 2 dB except for the
prevent output common-mode deviation, common-mode feed- final stage.
back formed by PMOS transistors – and resistors – a) Power detector and variable gain amplifier: Fig. 9
are added. The dc-offset problem in the direct conversion ar- shows the power detector circuit. The I channel signal is
chitecture is alleviated by the dc-offset correction method and represented as and the Q channel signal
careful LO distribution. The NMOS input devices M and M is represented as . The power detector
are designed to have high linearity and sufficient gain with the circuit squares the I and Q channel signals, I_out, I_outb,
total mixer core current of 3.7 mA. On the other hand, the sizes Q_out, and Q_outb and adds the two terms with the output
of the transistors used for commutating switches should be op- being its amplitude , regardless of the phase and time. Its
timized to reduce the critical flicker noise. output is compared with the reference level and the resulting
PD signal is sent to the gain control block.
B. Baseband Blocks Accurate gain control is important in designing WCDMA
1) Receiver: The receiver baseband architecture is shown in systems. The receiver chain has the specified required dynamic
Fig. 8. It is composed of a five-stage VGAs, two third-order ac- range of greater than 80 dB. The actual gain or system gain is
tive-RC elliptic filters, a elliptic filter, and a more than 140 dB to cover all signal conditions. The gain control
equalizer. The active-RC filter implementation offers high lin- loop is carefully designed to achieve high adjacent channel se-
earity and insensitivity to parasitic effects. The merged filtering lectivity (ACS) and adequate SNR. At the maximum gain of the
and controlled gain stages optimize the noise and linearity per- baseband VGAs, SNR is a very important design issue. The cir-
formance of an active-RC filter and minimize the number of cuits have complex gain distribution to achieve enough overall
amplifiers in the baseband circuitry. The 114-dB gain control SNR under any signaling conditions. Although the gain distri-
range can be adjusted digitally in 0.5-dB steps. The gain range bution is quite complex, the actual gain control is very simply

Fig. 8. Receiver baseband architecture.

Fig. 9. Power detector.

done by the baseband modem and the built-in gain control al- The proper mode can be selected by the baseband modem with
gorithm. Because the gain is controlled in a discrete manner, a three-wire serial interface. Fig. 10 shows the VGA with the
a new interface optimized for the digital gain control is used. dc-offset correction circuit. Gain is determined by the ratio

Fig. 10. VGA.

of and , so is composed of resistors and switches to ACS, the filter stages are optimally distributed. In WCDMA,
be programmable. The switch control signals ctrl[1: ] are con- a highly linear baseband circuit is needed for high PAR. Thus,
trolled by the gain control block based on the power detect sig- the channel filter circuits must have high linearity and low noise
nals. The number of switch and resistor sets is determined by performance. The outputs of the baseband filter are connected to
the gain control step and the total gain. The variable-gain ampli- the ADCs. The I/Q signals are differential and fully balanced for
fier is merged with the dc-offset cancellation circuits. To prevent high linearity and high common-mode rejection ratio (CMRR).
saturation of the signal, the dc-offset compensation loop filters Design of an analog channel filter is always a compromise be-
out the dc component in the input and compensates the internal tween adjacent channel rejection and intersymbol interference.
offset of the VGAs. The dc-offset canceling circuit does not re- The two third-order active-RC and fifth-order elliptic
quire any external components and occupies a small area. The filters offer sufficient attenuation at the adjacent channel and
dc-offset between and is detected and stored at less than 105-ns group delay variation at the passband edge,
and as and , respectively. The latter signals are which can be equalized digitally at the baseband modem.
added back to and to nullify the dc-offset. However, Fig. 11 shows the circuit diagram of a third-order active-RC
if the dc-offset corner frequency is too large, it seriously de- elliptic filter. To reduce the noise contribution, filters are com-
grades the spectral efficiency, so the high-pass pole is located at posed of two-stage active-RC filters, a one-stage filter,
1 kHz with the highest gain setting and moves toward the lower and an equalizer. Resistors and capacitors usually vary by about
frequency when the baseband gain is decreased. DC-offset up to 15 because of process variation, and, accordingly, the cutoff
300 mV at the input of the baseband circuitry can be tolerated frequency can vary. To tune the cutoff frequency, variable ca-
over all gain settings. pacitors – are used and they are controlled by the tuning
b) Filter: The complex baseband filters carry out channel block. The on-chip tuning circuits for frequency response are
selection and image-free operation. Because it is easier to de- needed for the active-RC and filters. The variable ca-
sign low-pass filters (LPFs) than bandpass filters (BPFs), the pacitor consists of a main capacitor and tuning capacitors
direct conversion receivers can meet the strict requirements for – . The tuning capacitors are controlled by the signals
adjacent channel selection and image rejection compared with [ ] from the tuning circuit. When the cutoff frequency
super-heterodyne receivers. The baseband filter provides supe- is too high, the total capacitance value is increased, and vice
rior performance in the presence of strong adjacent interferers. versa. The reference for the tuning comes from an accurate
To meet the stringent requirements of both the gain setting and external clock. When tuning is done discretely, it requires a

active-RC elliptic filters, and a one-stage VGA. The input

level from the DAC is 0 dBm. The level shifter attenuates the
signal level to 5 dBm to improve the linearity of the upcon-
version mixer and filter noise. The transmitter filter is rather
simple compared to the receiver filter. The cutoff frequency
is maximized within the attenuation specification in order to
meet the group delay requirement easily. Gains of the first
stage and second stage filters are 0 and 7 dBm, respectively.
Therefore, input to the upconversion mixer is 12 dBm. The
VGA receives the 18-level control signal, Gain1(1:18), for gain
control. Its gain range is 36 dB with the gain step of 2 dB.

C. Frequency Synthesizer
The transmitter and receiver incorporate a frequency synthe-
Fig. 11. Active-RC third-order elliptic filter. sizer to support all carrier signal generation with the specified
channel spacing. The channel spacing is 5 MHz and the raster
frequency is 200 kHz. The reference clock frequency can be any
multiple of 200 kHz. Thus, the industry standard 13-, 19.2-. and
19.8-MHz crystal oscillators can be used. This flexibility is in-
tended for the future multimode design of the circuit. All the
information needed to set the channel frequency is provided by
the baseband modem with a programmable three-wire serial in-
terface and is used by the prescaler. The loop filter is also inte-
grated in the circuit to minimize the coupling from the external
noise sources. The included prescaler can operate either in in-
teger- or fractional- mode. The operating mode can be set
by the serial interface. While the integer- mode shows poten-
tially lower spur levels, the fractional- mode offers lower rms
phase error because of the larger loop bandwidth. Since the total
integrated phase error measured in the desired channel band-
width affects the SNR, it should be far below the specification.
The high spur and high phase noise outside the desired channel
also degrade the SNR because of the mixing. The bandwidth of
Fig. 12. Active-RC third-order elliptic filter tuning circuit. the frequency synthesizer is designed to be 20 kHz. The on-chip
VCO is used to minimize the overall system size and noise cou-
pling. The integrated RF oscillator provides a low phase noise
number of capacitors and switches. The proposed tuning cir-
characteristics compatible with an off-chip VCO. The operating
cuit for the active-RC elliptic filter is shown in Fig. 12. Tuning
range of the VCO is internally trimmed by a dedicated coarse
is done in two steps. First, coarse tuning capacitors are selected
tuning algorithm whenever it is activated, and thus no manual
by tuning [ ]. The tuning controls are determined on
trimming is needed. This automatic tuning enables the exact and
power-up depending on which coarse reference range falls
stable LO signal generation against process variation during the
into. Second, after coarse_lock is asserted, the cutoff frequency
manufacturing stage and environmental variation during the op-
is tuned finely. is compared with the reference ranges and
eration. The coarse tuning function of the VCO is fast and ac-
the fine_bias voltage from the fine-tuning block determines the
curate and helps to achieve a fast lock.
bias voltage of the op-amp. Thus, with the two-step tuning, the
number of capacitances can be greatly reduced. In Fig. 12,
is the exact replica of in Fig. 11. When clk0 and clk1 are both IV. EXPERIMENTAL RESULTS
high, node X and are equal to . When clk0 is changed The transmitter and the receiver have been implemented sep-
to low and clk1 remains high, changes according to arately using a 0.35- m 1-poly 5-metal CMOS process. Fig. 14
shows the chip microphotographs. The chip area of both trans-
(2) mitter and receiver is 4.0 mm 5.0 mm. The bond wires are
used for input matching, and several bonding pads are used for
In (2), is determined by an exact external reference clock. If supply and ground to keep the parasitic inductance to an accept-
is too large, goes low, causing to be reduced. On able level. The transmitter is characterized at the output of the
the other hand, if is too small, goes high, causing pre-amplifier and the receiver is characterized at the output of
to be increased. the 6-b ADC for the 4.096-Mcps channel. The received data bits
2) Transmitter: The transmitter baseband structure is shown are captured from the ADC with a logic analyzer and analyzed
in Fig. 13. It is composed of a level shifter, two third-order in the frequency domain with a fast Fourier transform (FFT) [2].

Fig. 13. Transmitter baseband architecture.

Fig. 15. LO phase noise and rms jitter.

is 0.47 . Fig. 16(a) shows the 10-b DAC output spectrum and
(a) Fig. 16(b) shows the output of the VGA in the transmitter when
the external 80 dBm signal is applied to the DAC output. The
resolution bandwidth is 100 kHz. The gain control range of the
transmitter VGA is about 35 dB. Fig. 17(a) shows the output
spectrum of the transmitter preamplifier and the upconversion
mixer. The dynamic range of the preamplifier and transmitter
VGA are 15 and 35 dB, respectively, which results in a 50-dB
overall transmitter dynamic range. The additional variable gain
power amplifier has a 25-dB dynamic range. Hence, the overall
dynamic range including the external power amplifier and the
implemented transmitter is 75 dB. The maximum output power
of the preamplifier is 6 dBm. As Fig. 17(a) shows, the ACPR of
the transmitter output is 38 dB at 1.92 MHz.
The RF input frequency range of the receiver is from 2110
to 2170 MHz. Measurement results show that overall noise
figure of the receiver is 4.0 dB and its dynamic range is 80 dB.
Fig. 17(b) shows the output CDMA spectrum measured at the
(b) output of the I/Q channel selection filter when a 30-dBm
Fig. 14. Chip microphotograph. (a) Transmitter. (b) Receiver. CDMA signal of 4 MHz bandwidth at 2140 MHz is applied.
The measured SNR is 40 dB and the I/Q gain mismatch is
The frequency range covered by the transmitter is from 1920 0.9 dB. The measured IIP3, IIP2, and 1-dB compression of the
to 1980 MHz. Fig. 15 shows the measured LO phase noise, receiver are 9 dBm, 40 dBm, and 25 dBm, respectively.
indicating 100 dBc/Hz at a 1-kHz offset and 115 dBc/Hz at The LO-to-RF isolation is better than 66 dB at all frequencies.
a 1-MHz offset with 720 MHz center frequency. The rms jitter I/Q phase and amplitude imbalance of less than 1 and 0.9 dB



Fig. 16. Transmitter. (a) DAC output spectrum. (b) VGA output spectrum.

Fig. 17. (a) Transmitter preamplifier output spectrum. (b) Receiver I/Q
channel output spectrum.

receiver are 363 and 396 mW, respectively. Table I summarizes

the measured performance of the transmitter and the receiver.

In this paper, we presented a prototype full-CMOS trans-
mitter and receiver based on the direct conversion architecture
for use in a complete 2.0-GHz WCDMA RF system with an ad-
ditional power amplifier for third-generation cellular commu-
nications. The use of external components are limited to input
matching and supply decoupling for RF and ground stabiliza-
tion. A multiphase reduced frequency mixer and the dc-offset
cancellation technique are used in the direct conversion archi-
tecture to solve the problems associated with the direct conver-
sion. Gain control is merged into the baseband filters and VGAs
to optimize the linearity of the system, reduce the noise, and im-
prove the sensitivity. VGAs with a dc-offset cancellation loop
eliminate the dc-offset in each stage. An overall dynamic range
of 50 dB in the transmitter, an overall noise figure of 4.0 dB, and
meets the requirements of the receiver. The sensitivity can be a dynamic range of 80 dB in the receiver are measured.
calculated for the receiver from the thermal noise floor at the
RF band, receiver noise figure, processing gain at the desired
bit rate, and the minimum required SNR for a given bit error
rate. When QPSK signals are detected, 6.7 dB SNR is required [1] K. Lee et al., “A single-chip 2.4 GHz direct-conversion CMOS receiver
for wireless local loop using multiphase reduced frequency conversion
for 10 BER [2]. The measured sensitivity is, therefore, technique,” IEEE J. Solid-State Circuits, vol. 36, pp. 800–809, May
115.4 dBm. The power dissipation of the transmitter and the 2001.

[2] A. Parssinen et al., “A wide-band direct conversion receiver for Jeong-Woo Lee received the B.S. and M.S. degrees
WCDMA applications,” IEEE J. Solid-State Circuits, vol. 34, pp. in electronics engineering and the Ph.D. degree in
1893–1903, Dec. 1999. electrical engineering from Seoul National Univer-
[3] A. Rofougaran et al., “A single-chip 900-MHz spread-spectrum wireless sity, Seoul, Korea, in 1994, 1996, and 2000, respec-
transceiver in 1-m CMOS—Part I & II,” IEEE J. Solid-State Circuits, tively.
vol. 33, no. 4, pp. 515–547, Apr. 1998. He is currently a Manager with the WCDMA team
[4] A. A. Abidi, “Direct-conversion radio transceivers for digital commu- of GCT Semiconductor Inc., San Jose, CA. His cur-
nications,” IEEE J. Solid-State Circuits, vol. 30, pp. 1399–1410, Dec. rent research interests include CMOS transceiver cir-
1995. cuitry for highly integrated radio applications.
[5] B. Razavi, “Design considerations for direct-conversion communica-
tions,” IEEE Trans. Circuits Syst. II, vol. 44, pp. 428–435, June 1997.
[6] J. Crols et al., “A single-chip 900 MHz CMOS receiver front-end with
a high-performance low-IF topology,” IEEE J. Solid-State Circuits, vol.
30, pp. 1483–1492, Dec. 1995.
[7] D. K. Shaeffer et al., “A 115-mW, 0.5 m CMOS GPS receiver with Joonbae Park received the B.S. and M.S. degrees
wide dynamic range active filters,” IEEE J. Solid-State Circuits, vol. 33, in electronics engineering and the Ph.D. degree in
pp. 2219–2231, Dec. 1998. electrical engineering from Seoul National Univer-
sity, Seoul, Korea, in 1993, 1995, and 2000, respec-
In 1998, he joined GCT Semiconductor Inc., San
Kang-Yoon Lee was born in Jeongup, Korea, in Jose, CA, as Director of the Analog Division. He is
1972. He received the B.S. and M.S. degrees from currently involved in the development of CMOS RF
Seoul National University, Seoul, Korea, in 1996 chip sets for WLL, WCDMA, and wireless LAN. His
and 1998, respectively. He is currently working other research interests include data converters and
toward the Ph.D. degree in electrical engineering at high-speed communication interfaces.
the same university. Dr. Park received the Best Paper Award of VLSI Design’99, Goa, India.
His research interests include high-speed serial bus
for data communications and RF circuit and system
design for wireless communication.
Kyeongho Lee was born in Seoul, Korea, in 1969. He
received the B.S., M.S., and Ph.D. degrees in elec-
tronics engineering from Seoul National University,
Seoul, Korea, in 1993, 1995, and 2000, respectively.
Seung-Wook Lee was born in Seoul, Korea, in 1971. He was with Silicon Image, Inc., Sunnyvale, CA,
He received the B.S. and M.S. degrees in electronics as a Member of Technical Staff, where he worked on
engineering from Seoul National University, Seoul, CMOS high-bandwidth low-EMI transceivers. He is
Korea, in 1995 and 1997, respectively. He is currently currently with GCT Semiconductor Inc., San Jose,
working toward the Ph.D. degree in electrical engi- CA, as a Chief Executive Officer. His research in-
neering at the same university. terests include various CMOS high-speed circuits for
His research interests include CMOS RF circuit wire/wireless communication systems and integrated
design and high-speed communication interface. CMOS RF systems.
Mr. Lee is the winner of the bronze prize of the
IC design contest held by the Federation of Korean
Industries in 1995.
Deog-Kyoon Jeong received the B.S. and M.S. de-
grees in electronics engineering from Seoul National
University, Seoul, Korea, in 1981 and 1984, respec-
Yido Koo was born in Seoul, Korea, in 1973. He re- tively, and the Ph.D. degree in electrical engineering
ceived the B.S. and M.S. degrees from Seoul National and computer sciences from the University of Cali-
University, Seoul, Korea, in 1996 and 1998, respec- fornia, Berkeley, in 1989.
tively. He is currently working toward the Ph.D. de- From 1989 to 1991, he was with Texas Instruments
gree at the same university. Inc., Dallas, TX, where he was a Member of Tech-
His research interests include RF building blocks nical Staff and worked on the modeling and design
and systems for wireless communication and high of BiCMOS gates and the single-chip implementa-
speed interface for data communications. Currently, tion of the SPARC architecture. He joined the faculty
he is developing a low-noise frequency synthesizer of the Department of Electronics Engineering and Inter-University Semicon-
for CDMA and GSM applications. ductor Research Center, Seoul National University, as an Assistant Professor in
1991. He is currently a Professor of the School of Electrical Engineering, Seoul
National University. His main research interests include high-speed I/O circuits,
VLSI systems design, microprocessor architectures, and memory systems.
Hyoung-Ki Huh was born in Seoul, Korea. He
received the B.S. and M.S. degrees in electrical
engineering from Seoul National University, Seoul,
Korea, in 1998 and 2001, respectively. He is cur- Wonchan Kim was born in Seoul, Korea, on De-
rently working toward the Ph.D. degree in electrical cember 11, 1945. He received the B.S. degree in elec-
engineering at the same university. tronics engineering from Seoul National University,
His research interests are in the area of RF cir- Korea, in 1972 and the Dip.-Ing. and Dr.-Ing. De-
cuits and systems with emphasis on the fractional fre- grees in electrical engineering from the Technische
quency synthesizer. Hochschule Aachen, Germany, in 1976 and 1981, re-
In 1972, he was with Fairchild Semiconductor
Korea as a Process Engineer. From 1976 to 1982, he
was with the Institut fur Theoretische Electrotecnik
Hee-Young Nam received the B.S. degree from the Korea Advanced Institute RWTH Aachen. Since 1982, he has been with the
of Science and Technology, Taejeon, in 1998 and the M.S. degree from Seoul School of Electrical Engineering, Seoul National University, where he is cur-
National University, Seoul, Korea, in 2001, both in electrical engineering. rently a Professor. His research interests include development of semiconductor
Her research interests are in the area of RF circuits and systems. devices and design of analog/digital circuits.