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A B C D E Compal Confidential Model Name : Q1VZC File Name :LA-8943P ZZZ1
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B
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Compal Confidential
Model Name : Q1VZC
File Name :LA-8943P
ZZZ1
ZZZ1
ZZZ2
ZZZ2
ZZZ3
ZZZ3
ZZZ4
ZZZ4
ZZZ5
ZZZ5
1
1
BOM P/N:43
LA-8943P
LA-8943P
LS-8941P
LS-8941P
LS-8942P
LS-8942P
LS-8943P
LS-8943P
PCB
PCB
DA2@
DA2@
DA2@
DA2@
DA2@
DA2@
DA2@
DA2@
DAZ@
DAZ@
Compal Confidential
2
2
CHROME M/B Schematics Document
Intel Sandy Bridge ULV Processor + Panther Point PCH
2012-08-10
3
3
REV:1.0
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Page
Cover Page
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
Sheet
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A B C D E Compal Confidential Model Name : Q1VZC File Name :LA-8943P 1
A
B
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D
E
Compal Confidential
Model Name : Q1VZC
File Name :LA-8943P
1
Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
1
Intel
Sandy Bridge ULV
page 11,12
Dual Channel
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333
Processor
eDP(UMA)
BGA1023
17W
page 4~10
FDI x8
DMI x4
USB 2.0
conn x1(Option for USB3.0)
USB 2.0
CMOS
CRT Conn
HDMI Conn.
LVDS/eDP Conn.
CLK=100MHz
CLK=100MHz
conn x2
Camera
page 24
page 23
page 22
2.7GT/s
2.5GB/s x4
page 34
page 30
page 22
2
LVDS(UMA)
USBx14
Port 1
Port 2,3
Port 10
2
3.3V 48MHz
Port 8
TMDS(UMA)
Intel
LAN(GbE)/CardReader
MINI Card
RGB(UMA)
Broadcom
WLAN
Panther Point-M
57785 page 25
page 36
HD Audio
Port 3
Port 2
PCI-Express x 8
3.3V 24MHz
PCH
(PCIE2.0 5GT/s)
100MHz
SPI
HDA Codec
SATA x 6 (GEN2 3.0GT/S ,GEN3 6GT/S)
ALC271X-VB6
100MHz
989pin BGA
GEN3
Port 0
page 31
SM Bus
SATA HDD
page 13~21
3
Conn.
3
page 24
Int. Speaker
SPI ROM x1
Touch Pad
LPC BUS
page 31
page 13
page 30
CLK=33MHz
LS-8941P
ENE
LED/B
KB932
page 30
RTC CKT.
page 29
page 13
LS-8942P
IO/B
page 28
Power On/Off CKT.
SPI ROM x1
Int.KBD
TPM
page 36
LS-8943P
page 29
page 30
page 30
HDD/B
DC/DC Interface CKT.
page 24
4
4
page 33
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Power Circuit DC/DC
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Block Diagrams
Block Diagrams
Block Diagrams
page 34~43
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
Sheet
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A B C D E SIGNAL STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
A
B
C
D
E
SIGNAL
STATE
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
+VALW
+V
+VS
Clock
Voltage Rails
Full ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
Power Plane
Description
S1
S3
S5
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
VIN
Adapter power supply (19V)
N/A
N/A
N/A
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
1
1
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
Board ID / SKU ID Table for AD channel
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.05VS_VTT
+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU
ON
OFF
OFF
Vcc
3.3V +/- 5%
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
Ra/Rc/Re
100K +/- 5%
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
Board ID
Rb / Rd / Rf
V
min
V
typ
AD_BID
AD_BID
V AD_BID max
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
ON
OFF
OFF
0
0
0 V
0 V
0 V
+3VALW
+3VALW always on power rail
ON
ON
ON
1
8.2K +/- 5%
0.216
V
0.250
V
0.289
V
+VCCSUS3_3
+3VALW to +VCCSUS3_3 power rail for PCH (Short Jump)
ON
ON
OFF
2
18K +/- 5%
0.436
V
0.503
V
0.538
V
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
3
33K +/- 5%
0.712
V
0.819
V
0.875
V
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON
4
56K +/- 5%
1.036
V
1.185
V
1.264
V
+5VREF_SUS
+5VALW to +5VREF_SUS power rail for PCH (Short resister)
ON
ON
OFF
5
100K +/- 5%
1.453
V
1.650
V
1.759
V
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
6
200K +/- 5%
1.935
V
2.200
V
2.341
V
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
7
NC
2.500
V
3.300
V
3.300
V
+RTCVCC
RTC power
ON
ON
ON
BOARD ID Table
2
2
BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID
PCB Revision
0
0.1
BTO Item
BOM Structure
1
Celeron 867
C867@
2
Celeron 877
C877@
3
Unpop
@
4
eDP Panel
EDP@
EC SM Bus1 address
5
LVDS Panel
LVDS@
6
Connector
CONN@
Device
Address
7
USB3 Only
USB3@
Smart Battery
0001 011X b
Deep S3
DS3@
PCH SM Bus address
USB Port Table
Normal S3
S3@
3 External
Intel i5/i7 CPU only
I57@
Device
Address
USB 2.0
USB 1.1
Port
USB Port
Celeron/Pentium/i3
ChannelA
DIMM0
A0
1010 000X
JDIMM1(STD)
CP3@
ChannelB
DIMM0
B0
1010 010X
JDIMM2(REV)
0
CPU only
UHCI0
1
USB 2.0(Options for USB3.0)
3
3
2
USB port(Left 2.0)
UHCI1
3
USB Port(Left 2.0)
EHCI1
4
UHCI2
5
USB 3.0
Port
6
UHCI3
1
7
2
USB Port(Right 3.0)
8
Mini Card(WLAN)
XHCI
UHCI4
3
9
4
10
Camera
EHCI2
UHCI5
11
12
UHCI6
13
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Notes List
Notes List
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, August 15, 2012
Wednesday, August 15, 2012
Wednesday, August 15, 2012
Sheet
Sheet
Sheet
3
3
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45
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B
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A B C D E +1.05VS_VTT R1 R1 24.9_0402_1% 24.9_0402_1% PEG_ICOMPI and RCOMPO signals should
A
B
C
D
E
+1.05VS_VTT
R1
R1
24.9_0402_1%
24.9_0402_1%
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
- typical impedance = 14.5 mohms
W=12mil L=500mil S=15mil
UCPU1A
UCPU1A
G3
PEG_COMP
1
1
PEG_ICOMPI
G1
PEG_ICOMPO
M2
G4
<15>
DMI_CRX_PTX_N0
DMI_RX#[0]
PEG_RCOMPO
P6
<15>
DMI_CRX_PTX_N1
DMI_RX#[1]
P1
<15>
DMI_CRX_PTX_N2
DMI_RX#[2]
P10
H22
<15>
DMI_CRX_PTX_N3
DMI_RX#[3]
PEG_RX#[0]
J21
PEG_RX#[1]
N3
B22
<15>
DMI_CRX_PTX_P0
DMI_RX[0]
PEG_RX#[2]
P7
D21
<15>
DMI_CRX_PTX_P1
DMI_RX[1]
PEG_RX#[3]
P3
A19
<15>
DMI_CRX_PTX_P2
DMI_RX[2]
PEG_RX#[4]
P11
D17
C867@
Celeron 867
HR
1.3G
SA00005BH40(S IC AV8062701148901 SR0FK J1 1.3G ABO!)
<15>
DMI_CRX_PTX_P3
DMI_RX[3]
PEG_RX#[5]
B14
PEG_RX#[6]
K1
D13
C877@
Celeron 877
HR
1.4G
SA00005QI10(S IC AV8062701148001 QB35 J1 1.4G ABO!)
<15>
DMI_CTX_PRX_N0
DMI_TX#[0]
PEG_RX#[7]
M8
A11
<15>
DMI_CTX_PRX_N1
DMI_TX#[1]
PEG_RX#[8]
N4
B10
<15>
DMI_CTX_PRX_N2
DMI_TX#[2]
PEG_RX#[9]
R2
G8
<15>
DMI_CTX_PRX_N3
DMI_TX#[3]
PEG_RX#[10]
A8
UCPU1
UCPU1
UCPU1
UCPU1
PEG_RX#[11]
K3
B6
<15>
DMI_CTX_PRX_P0
DMI_TX[0]
PEG_RX#[12]
M7
H8
<15>
DMI_CTX_PRX_P1
DMI_TX[1]
PEG_RX#[13]
P4
E5
<15>
DMI_CTX_PRX_P2
DMI_TX[2]
PEG_RX#[14]
T3
K7
<15>
DMI_CTX_PRX_P3
DMI_TX[3]
PEG_RX#[15]
K22
AV8062701148001
AV8062701148001
AV8062700852800
AV8062700852800
PEG_RX[0]
K19
C877@
C877@
C847@
C847@
PEG_RX[1]
C21
PEG_RX[2]
U7
D19
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
SA00005QI10
SA00005VK20
<15>
FDI_CTX_PRX_N0
FDI0_TX#[0]
PEG_RX[3]
W11
C19
<15>
FDI_CTX_PRX_N1
FDI0_TX#[1]
PEG_RX[4]
W1
D16
<15>
FDI_CTX_PRX_N2
FDI0_TX#[2]
PEG_RX[5]
AA6
C13
<15>
FDI_CTX_PRX_N3
FDI0_TX#[3]
PEG_RX[6]
2
W6
D12
2
<15>
FDI_CTX_PRX_N4
FDI1_TX#[0]
PEG_RX[7]
V4
C11
<15>
FDI_CTX_PRX_N5
FDI1_TX#[1]
PEG_RX[8]
Y2
C9
<15>
FDI_CTX_PRX_N6
FDI1_TX#[2]
PEG_RX[9]
AC9
F8
<15>
FDI_CTX_PRX_N7
FDI1_TX#[3]
PEG_RX[10]
C8
PEG_RX[11]
C5
PEG_RX[12]
U6
H6
<15>
FDI_CTX_PRX_P0
FDI0_TX[0]
PEG_RX[13]
W10
F6
<15>
FDI_CTX_PRX_P1
FDI0_TX[1]
PEG_RX[14]
W3
K6
<15>
FDI_CTX_PRX_P2
FDI0_TX[2]
PEG_RX[15]
AA7
<15>
FDI_CTX_PRX_P3
FDI0_TX[3]
W7
G22
<15>
FDI_CTX_PRX_P4
FDI1_TX[0]
PEG_TX#[0]
T4
C23
<15>
FDI_CTX_PRX_P5
FDI1_TX[1]
PEG_TX#[1]
AA3
D23
<15>
FDI_CTX_PRX_P6
FDI1_TX[2]
PEG_TX#[2]
AC8
F21
<15>
FDI_CTX_PRX_P7
FDI1_TX[3]
PEG_TX#[3]
H19
PEG_TX#[4]
+1.05VS_VTT
AA11
C17
<15>
FDI_FSYNC0
FDI0_FSYNC
PEG_TX#[5]
eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function
AC12
K15
<15>
FDI_FSYNC1
FDI1_FSYNC
PEG_TX#[6]
F17
PEG_TX#[7]
U11
F14
<15>
FDI_INT
FDI_INT
PEG_TX#[8]
A15
PEG_TX#[9]
AA10
J14
<15>
FDI_LSYNC0
FDI0_LSYNC
PEG_TX#[10]
R2
R2
AG8
H13
<15>
FDI_LSYNC1
FDI1_LSYNC
PEG_TX#[11]
M10
24.9_0402_1%
24.9_0402_1%
PEG_TX#[12]
F10
PEG_TX#[13]
W=12mil L=500mil S=15mil
D9
PEG_TX#[14]
J4
PEG_TX#[15]
EDP_COMP
AF3
eDP_COMPIO
AD2
F22
eDP_ICOMPO
PEG_TX[0]
EDP_HPD#
AG11
A23
eDP_HPD#
PEG_TX[1]
3
3
D24
PEG_TX[2]
E21
PEG_TX[3]
AG4
G19
<22>
EDP_AUXN
eDP_AUX#
PEG_TX[4]
AF4
B18
<22>
EDP_AUXP
eDP_AUX
PEG_TX[5]
K17
PEG_TX[6]
G17
PEG_TX[7]
+1.05VS_VTT
AC3
E14
<22>
EDP_TXN0
eDP_TX#[0]
PEG_TX[8]
AC4
C15
<22>
EDP_TXN1
eDP_TX#[1]
PEG_TX[9]
AE11
K13
eDP_TX#[2]
PEG_TX[10]
AE7
G13
eDP_TX#[3]
PEG_TX[11]
R3
R3
K10
PEG_TX[12]
1K_0402_5%
1K_0402_5%
AC1
G10
<22>
EDP_TXP0
eDP_TX[0]
PEG_TX[13]
EDP@
EDP@
AA4
D8
<22>
EDP_TXP1
eDP_TX[1]
PEG_TX[14]
AE10
K4
eDP_TX[2]
PEG_TX[15]
AE6
eDP_TX[3]
EDP_HPD#
<22>
EDP_HPD#
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
Sheet
Sheet
Sheet
4
4
4
of
of
of
45
45
45
A
B
C
D
E
12
12
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
12
A B C D E 0921 LVDS@->@ +1.05VS_VTT LVDS@ LVDS@ CLK_CPU_DPLL# R4 R4 2 1
A
B
C
D
E
0921 LVDS@->@
+1.05VS_VTT
LVDS@
LVDS@
CLK_CPU_DPLL#
R4
R4
2
1
1K_0402_5%
1K_0402_5%
MISC
MISC
THERMAL
THERMAL
PWR MANAGEMENT
PWR MANAGEMENT
CLK_CPU_DPLL
R5
R5
2
LVDS@
LVDS@
1
1K_0402_5%
1K_0402_5%
Checklist1.5 P.67 Graphis Disable Guide
eDP disable:
1
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PU 1K_5% to +1.05VS_VTT
1
UCPU1B
UCPU1B
PCH->CPU
UNCOREPWRGOOD:非非非非CORE外外外外外外外外外外外外OK
SM_DRAMPWROK:DRAM power ok
RESET#:都都都都ok後後後後後後後後CPU做做做做reset
PROC_SELECT#
PH VCPLL and connect to PCH DF_TVS
J3
BCLK
CLK_CPU_DMI
<14>
H2
BCLK#
CLK_CPU_DMI#
<14>
F49
<17>
H_SNB_IVB#
PROC_SELECT#
AG3
CLK_CPU_DPLL
DPLL_REF_CLK
CLK_CPU_DPLL
<14>
AG1
CLK_CPU_DPLL#
DPLL_REF_CLK#
CLK_CPU_DPLL#
<14>
C57
PROC_DETECT#
偵偵偵偵偵偵偵偵CPU有有有有有有有有有有有有有有有有
SM_RCOMP0,SM_RCOMP1
W=20mil L=500mil S=13mil
Follow DG 1.5& Tacoma_Fall2 1.0
reserve
T1T1
PADPAD @@
H_CATERR#
C49
XBOX 三三三三 三三三三三三三三三三三三
SM_RCOMP2
CATERR#
W=15mil L=500mil S=13mil
@
@
C65
C65
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H_CPUPWRGD
follow Checklist 1.5
H_PECI
A48
AT30
SM_DRAMRST#
<18,29>
H_PECI
SM_DRAMRST#
<6>
PECI
SM_DRAMRST#
R6R6
2
1
10K_0402_5%10K_0402_5%
R7R7
2
1
62_0402_5%62_0402_5%
R8
R8
+1.05VS_VTT
56_0402_5%
56_0402_5%
BF44
SM_RCOMP0
R9R9
2
1
140_0402_1%140_0402_1%
SM_RCOMP[0]
H_PROCHOT#
1
2
H_PROCHOT#_R
C45
BE43
SM_RCOMP1
R10R10
2
1
25.5_0402_1%25.5_0402_1%
<29,35>
H_PROCHOT#
PROCHOT#
SM_RCOMP[1]
BG43
SM_RCOMP2
R11R11
2
1
200_0402_1%200_0402_1%
SM_RCOMP[2]
DDR3 Compensation Signals
2
2
D45
<18>
H_THRMTRIP#
THERMTRIP#
Follow DG 1.5 & Tacoma_Fall2 1.0
Use open drain logic gate:
N53
PRDY#
Buffered reset to CPU
N55
PREQ#
+3VS
+1.05VS_VTT PU pop 75ohm
series resister pop 43ohm
L56
XDP_TCK
@@
PADPAD T2T2
TCK
L55
XDP_TMS
@@
PADPAD T3T3
TMS
+1.05VS_VTT
J58
XDP_TRST#
@@
PADPAD T4T4
TRST#
1
C66
C66
C48
M60
XDP_TDI
@@
PADPAD T5T5
<15>
H_PM_SYNC
PM_SYNC
TDI
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L59
XDP_TDO
@@
PADPAD T6T6
TDO
R12
R12
2
75_0402_5%
75_0402_5%
R14
R14
1
2
H_CPUPWRGD_R
B46
<18>
H_CPUPWRGD
UNCOREPWRGOOD
0_0402_5%
0_0402_5%
U1
U1
R15
R15
R13R13
0_0402_5%0_0402_5%
K58
XDP_DBRESET#
XDP_DBRESET#
<15,28>
DBR#
1
@
@
2
1
43_0402_1%
43_0402_1%
UNCOREPWRGOOD:非非非非CORE外外外外外外外外外外外外OK
NC
4
BUFO_CPU_RST#
1
2
BUF_CPU_RST#
Y
PLT_RST#
2
PM_DRAM_PWRGD_R
BE45
G58
<17>
PLT_RST#
A
SM_DRAMPWROK
BPM#[0]
E55
BPM#[1]
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
E59
BPM#[2]
SM_DRAMPWROK:DRAM power ok
G55
BPM#[3]
G59
BPM#[4]
BUF_CPU_RST#
D44
H60
RESET#
BPM#[5]
RESET#:都都都都ok後後後後後後後後CPU做做做做reset
J59
BPM#[6]
J61
BPM#[7]
Follow DG 1.5 & Tacoma_Fall2 1.0
Use open drain logic gate:
3
+3VALW
3
C476
C476
+1.5V_CPU_VDDQ PU pop 200ohm
@
@
+1.5V_CPU_VDDQ
2
1
H_CPUPWRGD_R
series resister pop 130ohm
+3VS
1
C67
C67
180P_0402_50V8J
180P_0402_50V8J
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C867@
C867@
XDP_DBRESET#
R17R17
2
1 1K_0402_5%1K_0402_5%
R16
R16
12/22 Add(ESD request)
2
200_0402_5%
200_0402_5%
U2
U2
Tacoma_Fall2 1.0 PU 1K +3VS
Check list 1.5 PU 1K +3VS
Debug port DG1.1-1.3 50~5K ohm
1
<15>
SYS_PWROK
B
4
PM_SYS_PWRGD_BUF
1
2
PM_DRAM_PWRGD_R
Y
2
R18R18
130_0402_5%130_0402_5%
<15>
PM_DRAM_PWRGD
A
MC74VHC1G09DFT2G_SC70-5
MC74VHC1G09DFT2G_SC70-5
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
Sheet
Sheet
Sheet
5
5
5
of
of
of
45
45
45
A
B
C
D
E
3
5
G VCC
3
5
G
P
12
12
JTAG & BPM
JTAG & BPM
DDR3
DDR3
CLOCKS
CLOCKS
MISC
MISC
 

A

UCPU1C

UCPU1C

B

C

UCPU1D

UCPU1D

D

E

 
 

<11>

DDR_A_D[0 63]

     

<12>

DDR_B_D[0 63]

   
 
DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AG6

SA_DQ[0]

 
DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AL4

AL1

AN3

AR4

AK4

AK3

AN4

AR1

AU4

AT2

AV4

BA4

AU3

AR3

AY2

BA3

BE9

BD9

BD13

BF12

BF8

BD10

BD14

BE13

BF16

BE17

BE18

BE21

BE14

BG14

BG18

BF19

BD50

BF48

BD53

BF52

BD49

BE49

BD54

BE53

BF56

BE57

BC59

AY60

BE54

BG54

BA58

AW59

AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58

AG58

AG59

AM60

AL59

AF61

AH60

BG39

SB_DQ[0]

AJ6

AP11

AL6

AJ10

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

AU36

AV36

AY26

 

SA_CLK_DDR0

SA_CLK_DDR#0

DDRA_CKE0_DIMMA

<11>

<11>

<11>

SB_DQ[1]

SB_DQ[2]

SB_DQ[3]

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

BA34

AY34

AR22

BA34 AY34 AR22 SB_CLK_DDR0 SB_CLK_DDR#0 DDRB_CKE0_DIMMB <12> <12> <12>

SB_CLK_DDR0

SB_CLK_DDR#0

DDRB_CKE0_DIMMB

<12>

<12>

<12>

 

1

AJ8

AL8

AL7

AR11

SA_DQ[4]

SA_DQ[5]

SA_DQ[6]

SA_DQ[7]

SA_DQ[8]

 

SB_DQ[4]

SB_DQ[5]

SB_DQ[6]

SB_DQ[7]

SB_DQ[8]

 

1

AP6

AU6

AV9

AR6

SA_DQ[9]

SA_DQ[10]

SA_DQ[11]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

AT40

AU40

BB26

 

SA_CLK_DDR1

SA_CLK_DDR#1

DDRA_CKE1_DIMMA

<11>

<11>

<11>

SB_DQ[9]

SB_DQ[10]

SB_DQ[11]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

BA36

BB36

BF27

BA36 BB36 BF27 SB_CLK_DDR1 SB_CLK_DDR#1 DDRB_CKE1_DIMMB <12> <12> <12>

SB_CLK_DDR1

SB_CLK_DDR#1

DDRB_CKE1_DIMMB

<12>

<12>

<12>

 

AP8

AT13

AU13

BC7

BB7

BA13

BB11

BA7

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_DQ[19]

SA_CS#[0]

SA_CS#[1]

BB40 BC41
BB40
BC41

DDRA_CS0_DIMMA#

DDRA_CS1_DIMMA#

<11>

<11>

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

SB_DQ[16]

SB_DQ[17]

SB_DQ[18]

SB_DQ[19]

SB_CS#[0]

SB_CS#[1]

BE41 BE47
BE41
BE47

DDRB_CS0_DIMMB#

DDRB_CS1_DIMMB#

<12>

<12>

BA9

BB9

AY13

AV14

AR14

AY17

AR19

BA14

AU14

SA_DQ[20]

SA_DQ[21]

SA_DQ[22]

SA_DQ[23]

SA_DQ[24]

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

SA_DQ[28]

SA_DQ[29]

SA_ODT[0]

SA_ODT[1]

AY40

BA41

SA_DQ[28] SA_DQ[29] SA_ODT[0] SA_ODT[1] AY40 BA41 SA_ODT0 SA_ODT1 <11> <11>  

SA_ODT0

SA_ODT1

<11>

<11>

 

SB_DQ[20]

SB_DQ[21]

SB_DQ[22]

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_ODT[0]

SB_ODT[1]

AT43

BG47

AT43 BG47 SB_ODT0 SB_ODT1

SB_ODT0

SB_ODT1

 

<12>

<12>

 

BB14

BB17

BA45

AR43

AW48

BC48

BC45

SA_DQ[30]

SA_DQ[31]

SA_DQ[32]

SA_DQ[33]

SA_DQ[34]

SA_DQ[35]

SA_DQS#[0]

SA_DQS#[1]

SA_DQS#[2]

SA_DQS#[3]

SA_DQS#[4]

AL11

AR8

AV11

AT17

AV45

AY51

DDR_A_DQS#0

DDR_A_DQS#1

DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5

 

DDR_A_DQS#[0

7]

<11>

SB_DQ[30]

SB_DQ[31]

SB_DQ[32]

SB_DQ[33]

SB_DQ[34]

SB_DQ[35]

SB_DQS#[0]

SB_DQS#[1]

SB_DQS#[2]

SB_DQS#[3]

SB_DQS#[4]

AL3

AV3

BG11

BD17

BG51

BA59

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5

DDR_B_DQS#[0

7]

<12>

2

AR45

AT48

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_DQ[36]

SA_DQ[37]

SA_DQ[38]

SA_DQ[39]

SA_DQ[40]

SA_DQ[41]

SA_DQ[42]

SA_DQ[43]

SA_DQ[44]

SA_DQ[45]

SA_DQ[46]

SA_DQ[47]

SA_DQ[48]

SA_DQ[49]

SA_DQ[50]

SA_DQ[51]

SA_DQ[52]

SA_DQ[53]

SA_DQ[54]

SA_DQ[55]

SA_DQ[56]

SA_DQ[57]

SA_DQ[58]

SA_DQ[59]

SA_DQ[60]

SA_DQ[61]

SA_DQ[62]

SA_DQ[63]

SA_DQS#[5]

SA_DQS#[6]

AT55

AK55

DDR_A_DQS#6

DDR_A_DQS#7

 

SB_DQ[36]

SB_DQ[37]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_DQS#[5]

SB_DQS#[6]

SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

AT60

AK59

DDR_B_DQS#6

DDR_B_DQS#7

 

2

AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 SA_DQS#[7]

AY48

BA49

AV49

BB51

AY53

BB49

AU49

BA53

BB55

BA55

AV56

AP50

AP53

AV54

SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

AJ11

AR10

AY11

AU17

AW45

AV51

AT56

AK54

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS[0

7]

<11>

SB_DQ[38]

SB_DQ[39]

SB_DQ[40]

SB_DQ[41]

SB_DQ[42]

SB_DQ[43]

SB_DQ[44]

SB_DQ[45]

SB_DQ[46]

SB_DQ[47]

SB_DQ[48]

SB_DQ[49]

SB_DQ[50]

SB_DQ[51]

AM2

AV1

BE11

BD18

BE51

BA61

AR59

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS[0

7]

<12>

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS[0 7] <12>

AT54

AP56

AP52

AN57

AN53

AG56

AG53

AN55

AN52

AG55

AK56

BD37

SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

BG35

BB34

BE35

BD35

AT34

AU34

BB32

AT32

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_MA[0

15]

<11>

SB_DQ[52]

SB_DQ[53]

SB_DQ[54]

SB_DQ[55]

SB_DQ[56]

SB_DQ[57]

SB_DQ[58]

SB_DQ[59]

SB_DQ[60]

SB_DQ[61]

SB_DQ[62]

SB_DQ[63]

AK61

DDR_B_DQS7

BF32

BE33

BD33

AU30

BD30

AV30

BG30

BD29

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7

DDR_B_MA[0

15]

<12>

 

3

<11>

<11>

<11>

DDR_A_BS0

DDR_A_BS1

DDR_A_BS2

 

BF36

BA28

SA_BS[0]

SA_BS[1]

SA_BS[2]

SA_MA[7]

SA_MA[8]

SA_MA[9]

AY32

AV32

BE37

 

<12>

<12>

<12>

DDR_B_BS0

DDR_B_BS1

DDR_B_BS2

BD42 AT22

BD42

AT22

SB_BS[0]

SB_BS[1]

SB_BS[2]

SB_MA[7]

SB_MA[8]

SB_MA[9]

BE30

BE28

BD43

AT28

AV28

BD46

AT26

AU22

DDR_B_MA8

DDR_B_MA9

DDR_B_MA10

DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14

DDR_B_MA15

 

3

 

SA_MA[10]

SA_MA[11]

SA_MA[12]

BA30

BC30

 

SB_MA[10]

SB_MA[11]

SB_MA[12]

 

<11>

<11>

<11>

DDR_A_CAS#

DDR_A_RAS#

DDR_A_WE#

 

BE39

BD39

AT41

SA_CAS#

SA_RAS#

SA_WE#

SA_MA[13]

SA_MA[14]

SA_MA[15]

AW41

AY28

AU26

 

<12>

<12>

<12>

DDR_B_CAS#

DDR_B_RAS#

DDR_B_WE#

 

AV43

BF40

BD45

SB_CAS#

SB_RAS#

SB_WE#

SB_MA[13]

SB_MA[14]

SB_MA[15]

 

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

C867@

C867@

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

C867@

C867@

 
   

12

Follow CRB1.0

R19

R19

0_0402_5%

0_0402_5%

1

2

+1.5V

R20

R20

1K_0402_5%

1K_0402_5%

     

CPU通通 DIMMreset

<5>

SM_DRAMRST#

S

S

2

G G

2

1

SM_DRAMRST#

R22

R22

3

4.99K_0402_1%

4.99K_0402_1%

D D @ @ 1 DIMM_DRAMRST#_R 1 Q1 Q1 R21R21 BSS138_NL_SOT23-3 BSS138_NL_SOT23-3 S0
D
D
@
@
1
DIMM_DRAMRST#_R
1
Q1
Q1
R21R21
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
S0
2 1K_0402_5%1K_0402_5%
2
1K_0402_5%1K_0402_5%

DIMM_DRAMRST#

DRAMRST_CNTRL_PCH hgih ,MOS ON

<11,12>

4

 

R23

R23

0_0402_5%

0_0402_5%

RST_GATE_R

SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset

 

4

 

<14>

RST_GATE

 

1

2

RST_GATE_R <11,12> S3

RST_GATE_R

<11,12>

S3

 
 

DS3@

DS3@

R24

R24

0_0402_5%

0_0402_5%

DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# HIGH

 

<29>

EC_RST_GATE

 

1

DS3@

DS3@

2

1
1

Dimm not reset

   

Security Classification

Security Classification

Security Classification

 

Compal Secret Data

Compal Secret Data

Compal Secret Data

   

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

 
 

C68

C68

0.047U_0402_16V7K

0.047U_0402_16V7K

2

C68 C68 0.047U_0402_16V7K 0.047U_0402_16V7K 2 S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# low Dimm
C68 C68 0.047U_0402_16V7K 0.047U_0402_16V7K 2 S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# low Dimm

S4,5

DRAMRST_CNTRL_PCH Low ,MOS OFF

SM_DRAMRST# lo,DDR3 DRAMRST# low Dimm reset

 

Issued Date

Issued Date

Issued Date

2012/03/21

2012/03/21

2012/03/21

 

Deciphered Date

Deciphered Date

Deciphered Date

2013/03/21

2013/03/21

2013/03/21

Title

Title

Title

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

 
   

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

CHROME M/B LA-8943P Schematic

CHROME M/B LA-8943P Schematic

CHROME M/B LA-8943P Schematic

Rev

Rev

Rev

0.1

0.1

0.1

     

Date:

Date:

Date:

Friday, August 10, 2012

Friday, August 10, 2012

Friday, August 10, 2012

Sheet

Sheet

Sheet

6

6

6

of

of

of

45

45

45

 

A

 

B

 

C

 

D

 

E

A B C D E CFG Straps for Processor CFG2 UCPU1E UCPU1E R25 R25 T7T7
A
B
C
D
E
CFG Straps for Processor
CFG2
UCPU1E
UCPU1E
R25
R25
T7T7
PADPAD @@
CFG0
B50
N59
1K_0402_1%
1K_0402_1%
CFG[0]
BCLK_ITP
C51
N58
@
@
CFG[1]
BCLK_ITP#
CFG2
B54
CFG[2]
D53
CFG[3]
CFG4
A51
N42
1
1
CFG[4]
RSVD30
CFG5
C53
L42
PEG Static Lane Reversal - CFG2 is for the 16x
CFG[5]
RSVD31
CFG6
C55
L45
CFG[6]
RSVD32
CFG7
H49
L47
CFG[7]
RSVD33
A55
CFG[8]
1: Normal Operation; Lane # definition matches
socket pin map definition
H51
CFG2
CFG[9]
K49
M13
CFG[10]
RSVD34
K53
M14
0:Lane Reversed
CFG[11]
RSVD35
F53
U14
*
CFG[12]
RSVD36
G53
W14
CFG[13]
RSVD37
L51
P13
CFG[14]
RSVD38
F51
CFG[15]
D52
CFG4
CFG[16]
L53
AT49
CFG[17]
RSVD39
UMA,Optimus eDP啟啟啟啟 啟啟啟啟
DISO eDP關關關關關關關關
K24
RSVD40
T37T37
PADPAD @@
VCC_VAL_SENSE
H43
EDP@
EDP@
R28
R28
VCC_VAL_SENSE
T38T38
PADPAD @@
VSS_VAL_SENSE
K43
AH2
1K_0402_1%
1K_0402_1%
VSS_VAL_SENSE
RSVD41
AG13
RSVD42
AM14
RSVD43
T39T39
PADPAD @@
VAXG_VAL_SENSE
H45
AM15
VAXG_VAL_SENSE
RSVD44
T40T40
PADPAD @@
VSSAXG_VAL_SENSE
K45
VSSAXG_VAL_SENSE
N50
eDP enable
RSVD45
T8T8
PADPAD @@
F48
VCC_DIE_SENSE
1:Disable
H48
*
CFG4
RSVD6
K48
0:Enable
RSVD7
2
A4
2
DC_TEST_A4
C4
DC_TEST_C4
BA19
D3
DC_TEST_C4_D3
CFG6
RSVD8
DC_TEST_D3
AV19
D1
CFG5
RSVD9
DC_TEST_D1
AT21
A58
RSVD10
DC_TEST_A58
BB21
A59
These pins are for solder joint
reliability and non-critical to
function. For BGA only.
RSVD11
DC_TEST_A59
BB19
C59
DC_TEST_A59_C59
RSVD12
DC_TEST_C59
AY21
A61
R31
R31
R32
R32
RSVD13
DC_TEST_A61
BA22
C61
DC_TEST_A61_C61
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
RSVD14
DC_TEST_C61
AY22
D61
@
@
@
@
RSVD15
DC_TEST_D61
AU19
BD61
RSVD16
DC_TEST_BD61
AU21
BE61
RSVD17
DC_TEST_BE61
BD21
BE59
DC_TEST_BE59_BE61
RSVD18
DC_TEST_BE59
BD22
BG61
RSVD19
DC_TEST_BG61
BD25
BG59
DC_TEST_BG59_BG61
RSVD20
DC_TEST_BG59
BD26
BG58
RSVD21
DC_TEST_BG58
BG22
BG4
RSVD22
DC_TEST_BG4
BE22
BG3
RSVD23
DC_TEST_BG3
BG26
BE3
DC_TEST_BE3_BG3
PCIE Port Bifurcation Straps
RSVD24
DC_TEST_BE3
BE26
BG1
RSVD25
DC_TEST_BG1
BF23
BE1
DC_TEST_BE1_BG1
RSVD26
DC_TEST_BE1
BE24
BD1
11: (Default) 1x16 PCI Express
RSVD27
DC_TEST_BD1
CFG[6:5]
10: 2x8 PCI Express
*
01: Reserved
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
00: 1x8,2x4 PCI Express
3
3
CFG7
R33
R33
@
@
1K_0402_1%
1K_0402_1%
PEG DEFER TRAINING
Tacoma_Fall2 1.0 P.12
CFG7
1: (Default) PEG Train immediately following
xxRESETB de assertion
0: PEG Wait for BIOS for training
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
Sheet
Sheet
Sheet
7
7
7
of
of
of
45
45
45
A
B
C
D
E
RESERVED
RESERVED
12
12
12
12
12
A B C D E POWER POWER UCPU1F UCPU1F 8.5A ULV type +1.05VS_VTT DC 33A
A
B
C
D
E
POWER
POWER
UCPU1F
UCPU1F
8.5A
ULV type
+1.05VS_VTT
DC 33A
AF46
+CPU_CORE
VCCIO[1]
AG48
VCCIO[3]
AG50
For DDR
VCCIO[4]
A26
AG51
VCC[1]
VCCIO[5]
A29
AJ17
VCC[2]
VCCIO[6]
A31
AJ21
VCC[3]
VCCIO[7]
A34
AJ25
VCC[4]
VCCIO[8]
A35
AJ43
INTEL Recommend VCC
VCC[5]
VCCIO[9]
A38
AJ47
VCC[6]
VCCIO[10]
A39
AK50
INTEL Recommend VCCIO
2*330UF,10*10uF(0603) and 26*1uF(0402)
1
4*470UF,12*22uF(0805) and 35*2.2uF(0402)
VCC[7]
VCCIO[11]
1
A42
AK51
VCC[8]
VCCIO[12]
C26
AL14
PD0.8
VCC[9]
VCCIO[13]
PD0.8
C27
AL15
VCC[10]
VCCIO[14]
C32
AL16
CAP at P.51
VCC[11]
VCCIO[15]
CAP at P.51
C34
AL20
VCC[12]
VCCIO[16]
C37
AL22
VCC[13]
VCCIO[17]
C39
AL26
VCC[14]
VCCIO[18]
C42
AL45
VCC[15]
VCCIO[19]
D27
AL48
VCC[16]
VCCIO[20]
D32
AM16
VCC[17]
VCCIO[21]
D34
AM17
VCC[18]
VCCIO[22]
D37
AM21
VCC[19]
VCCIO[23]
D39
AM43
VCC[20]
VCCIO[24]
D42
AM47
VCC[21]
VCCIO[25]
E26
AN20
VCC[22]
VCCIO[26]
E28
AN42
VCC[23]
VCCIO[27]
E32
AN45
VCC[24]
VCCIO[28]
E34
AN48
VCC[25]
VCCIO[29]
E37
VCC[26]
E38
VCC[27]
F25
VCC[28]
F26
VCC[29]
F28
VCC[30]
F32
VCC[31]
F34
VCC[32]
F37
AA14
VCC[33]
VCCIO[30]
F38
AA15
For PEG
VCC[34]
VCCIO[31]
F42
AB17
VCC[35]
VCCIO[32]
G42
AB20
VCC[36]
VCCIO[33]
H25
AC13
VCC[37]
VCCIO[34]
H26
AD16
VCC[38]
VCCIO[35]
H28
AD18
VCC[39]
VCCIO[36]
H29
AD21
2
VCC[40]
VCCIO[37]
2
H32
AE14
VCC[41]
VCCIO[38]
H34
AE15
VCC[42]
VCCIO[39]
H35
AF16
VCC[43]
VCCIO[40]
H37
AF18
VCC[44]
VCCIO[41]
H38
AF20
VCC[45]
VCCIO[42]
H40
AG15
VCC[46]
VCCIO[43]
J25
AG16
VCC[47]
VCCIO[44]
+3VS
J26
AG17
VCC[48]
VCCIO[45]
J28
AG20
VCC[49]
VCCIO[46]
J29
AG21
VCC[50]
VCCIO[47]
J32
AJ14
VCC[51]
VCCIO[48]
J34
AJ15
R34
R34
VCC[52]
VCCIO[49]
J35
10K_0402_5%
10K_0402_5%
VCC[53]
J37
@
@
VCC[54]
J38
VCC[55]
+1.05VS_VTT
J40
VCC[56]
J42
VCC[57]
K26
W16
VCCIO_SEL
VCC[58]
VCCIO50
K27
W17
VCCIO_SEL after Ivy bridge ES2 Voltage support
VCC[59]
VCCIO51
K29
VCC[60]
K32
R35
R35
VCC[61]
K34
10K_0402_5%
10K_0402_5%
1/NC : (Default) +1.05VS_VTT
VCC[62]
K35
@
@
*
BC22
VCC[63]
K37
0: +1.0VS_VTT
VCC[64]
K39
VCC[66]
K42
BC22
VCCIO_SEL
VCC[67]
VCCIO_SEL
L25
VCC[68]
L28
VCC[69]
L33
VCC[70]
+1.05VS_VTT
L36
VCC[71]
L40
+1.05VS_VTT
+1.05VS_VTT
VCC[72]
N26
VCC[73]
N30
AM25
VCC[74]
VCCPQE[1]
3
N34
AN22
Place the PU
resistors close to CPU
3
VCC[75]
VCCPQE[2]
N38
R36
R36
R37
R37
VCC[76]
1
2
130_0402_5%
130_0402_5%
75_0402_5%
75_0402_5%
C69
C69
1U_0402_6.3V6K
1U_0402_6.3V6K
A44
H_CPU_SVIDALRT#
R38R38
1
2
43_0402_1%43_0402_1%
VIDALERT#
SVID_ALERT#
<41>
B43
H_CPU_SVIDCLK
R39R39
1
2
0_0402_5%0_0402_5%
VIDSCLK
SVID_CLK
<41>
C44
H_CPU_SVIDDAT
R40R40
1
2
0_0402_5%0_0402_5%
VIDSOUT
SVID_DATA
<41>
+CPU_CORE
Place the PU
resistors close to VR
R41
R41
100_0402_1%
100_0402_1%
F43
VCCSENSE_R
R42R42
1
2
0_0402_5%0_0402_5%
VCC_SENSE
VCCSENSE
<41>
G43
VSSSENSE_R
R43R43
1
2
0_0402_5%0_0402_5%
VSS_SENSE
VSSSENSE
<41>
R44R44
1
2
10_0402_5%10_0402_5%
+1.05VS_VTT
R45
R45
AN16
100_0402_1%
100_0402_1%
VCCIO_SENSE
VCCIO_SENSE
<40>
AN17
VSSIO_SENSE
VSS_SENSE_VCCIO
R46
R46
10_0402_5%
10_0402_5%
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
4
Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.
4
C867@
C867@
Check list 1.5
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
Sheet
Sheet
Sheet
8
8
8
of
of
of
45
45
45
A
B
C
D
E
CORE SUPPLY
CORE SUPPLY
PEG IO AND DDR IO
PEG IO AND DDR IO
SENSE LINES
SENSE LINES
SVID
SVID
QUIET
QUIET
RAILS
RAILS
12
12
12
12
12
12
12
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
A
B
C
D
E
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.5V_CPU_VDDQ
POWER
POWER
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
UCPU1G
UCPU1G
+V_SM_VREF should
have 20 mil trace width
R47
R47
1K_0402_5%
1K_0402_5%
+VGFX_CORE
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
DC 16A
AY43
+V_SM_VREF
SM_VREF
AA46
VAXG[1]
AB47
1
VAXG[2]
AB50
BE7
SA_DIMM_VREFDQ
C70
C70
R48
R48
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
SA_DIMM_VREFDQ
VAXG[3]
SA_DIMM_VREFDQ
SA_DIMM_VREFDQ
<11>
AB51
BG7
SB_DIMM_VREFDQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1K_0402_5%
1K_0402_5%
VAXG[4]
SB_DIMM_VREFDQ
SB_DIMM_VREFDQ
<12>
AB52
SB_DIMM_VREFDQ
1
INTEL Recommend VAXG
2*470uF,6*22uF(0805) and 6*10uF(0603)
VAXG[5]
1
2
AB53
Check list1.5 P18 M1 default M3 no stuff
VAXG[6]
AB55
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
VAXG[7]
AB56
VAXG[8]
AB58
R49
R49
R50
R50
VAXG[9]
11*1U(0402)
AB59
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
VAXG[10]
AC61
@
@
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
VAXG[11]
PD0.8
AD47
5A
VAXG[12]
AD48
INTEL Recommend VDDQ
1*330uF,8*10uF(0603) ,10*1uF(0402)
VAXG[13]
AD50
VAXG[14]
AD51
AJ28
PD0.8
1U_0402_6.3V6K
1U_0402_6.3V6K
VAXG[15]
VDDQ[1]
AD52
AJ33
VAXG[16]
VDDQ[2]
AD53
AJ36
VAXG[17]
VDDQ[3]
AD55
AJ40
+1.5V_CPU_VDDQ
+1.5VS
Place TOP IN BGA
VAXG[18]
VDDQ[4]
AD56
AL30
J1
J1
VAXG[19]
VDDQ[5]
AD58
AL34
1
2
VAXG[20]
VDDQ[6]
AD59
AL38
C71
C71
C72
C72
C73
C73
C74
C74
C75
C75
C76
C76
C77
C77
C78
C78
C79
C79
C80
C80
VAXG[21]
VDDQ[7]
AE46
AL42
JUMP_43X118
JUMP_43X118
1
VAXG[22]
VDDQ[8]
N45
AM33
@
@
VAXG[23]
VDDQ[9]
P47
AM36
+ C81
+
C81
VAXG[24]
VDDQ[10]
P48
AM40
330U_D2_2V_Y
330U_D2_2V_Y
VAXG[25]
VDDQ[11]
P50
AN30
VAXG[26]
VDDQ[12]
2
P51
AN34
VAXG[27]
VDDQ[13]
P52
AN38
VAXG[28]
VDDQ[14]
P53
AR26
VAXG[29]
VDDQ[15]
P55
AR28
VAXG[30]
VDDQ[16]
P56
AR30
Place BOT OUT BGA
VAXG[31]
VDDQ[17]
P61
AR32
VAXG[32]
VDDQ[18]
T48
AR34
VAXG[33]
VDDQ[19]
T58
AR36
VAXG[34]
VDDQ[20]
T59
AR40
C82
C82
C83
C83
C84
C84
C85
C85
C86
C86
C87
C87
C88
C88
C89
C89
VAXG[35]
VDDQ[21]
T61
AV41
VAXG[36]
VDDQ[22]
U46
AW26
VAXG[37]
VDDQ[23]
SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9
V47
BA40
2
VAXG[38]
VDDQ[24]
2
V48
BB28
VAXG[39]
VDDQ[25]
V50
BG33
VAXG[40]
VDDQ[26]
V51
VAXG[41]
V52
VAXG[42]
V53
VAXG[43]
V55
VAXG[44]
V56
VAXG[45]
V58
VAXG[46]
V59
VAXG[47]
W50
VAXG[48]
W51
VAXG[49]
W52
VAXG[50]
W53
VAXG[51]
W55
CR CheckList Rev1.5
VAXG[52]
W56
VAXG[53]
W61
+VGFX_CORE
VAXG[54]
Y48
VAXG[55]
Y61
VAXG[56]
R51
R51
+1.5V_CPU_VDDQ
100_0402_5%
100_0402_5%
INTEL Recommend VCCPLL
AM28
VCCDQ[1]
F45
AN26
C93
C93
1*330uF,2*1uF(0402)
<41>
VCC_GFXSENSE
VAXG_SENSE
VCCDQ[2]
G45
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
<41>
VSS_GFXSENSE
VSSAXG_SENSE
PD0.8
C90
C90
R52
R52
C92
C92
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1.2A
100_0402_5%
100_0402_5%
+1.8VS
Place BOT OUT Conn
BB3
VCCPLL[1]
3
BC1
3
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
VCCPLL[2]
BC4
VCCPLL[3]
1
1 1
+
+
C91
C91
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
BC43
SGA00001700 S POLY C 220U
220U 2.5V M B2 ESR35 TPE H1.9
@
@
VDDQ_SENSE
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
BA43
2
2 2
VSS_SENSE_VDDQ
6A
L17
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
VCCSA[1]
L21
VCCSA[2]
N16
VCCSA[3]
N20
VCCSA[4]
N22
VCCSA[5]
P17
VCCSA
+VCCSA
VCCSA[6]
Place TOP IN BGA
P20
U10
VCCSA[7]
VCCSA_SENSE
VCCSA_SENSE
<39>
R16
VID0
VID1
Vout
HR
CR
VCCSA[8]
+VCCSA
R18
VCCSA[9]
R21
CPU EDS1.3 P.93
VCCSA_VID0 Must PD
0
0
0.9V
V
V
VCCSA[10]
C95
C95
C96
C96
C97
C97
C98
C98
C99
C99
U15
1
VCCSA[11]
V16
0
1
0.85V
V
V
VCCSA[12]
+
+
C94
C94
V17
D48
H_VCCSA_VID0
VCCSA[13]
VCCSA_VID[0]
H_VCCSA_VID0
<39>
330U_D2_2V_Y
330U_D2_2V_Y
V18
D49
H_VCCSA_VID1
1
0
0.775V
X
V
VCCSA[14]
VCCSA_VID[1]
H_VCCSA_VID1
<39>
SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9
V21
2
VCCSA[15]
W20
1
1
0.75V
X
V
VCCSA[16]
R53
R53
0_0402_5%
0_0402_5%
@
@
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
Place BOT OUT BGA
C867@
C867@
INTEL Recommend VCCSA
1*330uF,5*10uF(0603) ,5*1uF(0402)
C100
C100
C101
C101
C102
C102
C103
C103
C104
C104
4
4
PD0.8
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2012/03/21
2012/03/21
2012/03/21
2013/03/21
2013/03/21
2013/03/21
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.1
0.1
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
CHROME M/B LA-8943P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
Sheet
Sheet
Sheet
9
9
9
of
of
of
45
45
45
A
B
C
D
E
12
12
12
12
12
12
12
12
12
12
12
12
SENSE
SENSE
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
LINES
LINES
SA RAIL
SA RAIL
VCCSA VID
VCCSA VID
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
VREF
VREF
SENSE LINES
SENSE LINES
lines
lines
QUIET RAILS
QUIET RAILS
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
A B C D E UCPU1H UCPU1H UCPU1I UCPU1I A13 AM38 VSS[1] VSS[91] A17 AM4
A
B
C
D
E
UCPU1H
UCPU1H
UCPU1I
UCPU1I
A13
AM38
VSS[1]
VSS[91]
A17
AM4
VSS[2]
VSS[92]
A21
AM42
BG17
M4
VSS[3]
VSS[93]
VSS[181]
VSS[250]
A25
AM45
VSS[4]
VSS[94]
BG21
M58
VSS[182]
VSS[251]
A28
AM48
M6
VSS[5]
VSS[95]
BG24
VSS[183]
VSS[252]
A33
AM58
N1
VSS[6]
1
VSS[96]
BG28
VSS[184]
VSS[253]
A37
AN1
VSS[7]
VSS[97]
BG37
N17
1
VSS[185]
VSS[254]
A40
AN21
VSS[8]
BG41
N21
VSS[98]
VSS[186]
VSS[255]
A45
AN25
N25
VSS[9]
VSS[99]
BG45
VSS[187]
VSS[256]
A49
AN28
VSS[100]
BG49
N28
VSS[10]
VSS[188]
VSS[257]
A53
AN33
VSS[11]
VSS[101]
BG53
N33
VSS[189]
VSS[258]
A9
AN36
N36
VSS[12]
VSS[102]
BG9
VSS[190]
VSS[259]
AA1
AN40
C29
N40
VSS[13]
VSS[103]
VSS[191]
VSS[260]
AA13
AN43
N43
VSS[14]
VSS[104]
C35
VSS[192]
VSS[261]
AA50
AN47
N47
VSS[15]
VSS[105]
C40
VSS[193]
VSS[262]
AA51
AN50
VSS[16]
VSS[106]
D10
N48
VSS[194]
VSS[263]
AA52
AN54
D14
N51
VSS[17]
VSS[107]
VSS[195]
VSS[264]
AA53
AP10
VSS[18]
VSS[108]
D18
N52
VSS[196]
VSS[265]
AA55
AP51
D22
N56
VSS[19]
VSS[109]
VSS[197]
VSS[266]
AA56
AP55
D26
N61
VSS[20]
VSS[110]
VSS[198]
VSS[267]
AA8
AP7
VSS[21]
VSS[111]
D29
P14
VSS[199]
VSS[268]
AB16
AR13
P16
VSS[22]
VSS[112]
D35
VSS[200]
VSS[269]
AB18
AR17
D4
P18
VSS[23]
VSS[113]
VSS[201]
VSS[270]
AB21
AR21
D40
P21
VSS[24]
VSS[114]
VSS[202]
VSS[271]
AB48
AR41
P58
VSS[25]
VSS[115]
D43
VSS[203]
D46
VSS
VSS
VSS[272]
AB61
AR48
P59
VSS[26]
VSS[116]
VSS[204]
VSS[273]
AC10
AR61
VSS[27]
D50
P9
VSS[117]
VSS[205]
VSS[274]
AC14
AR7
VSS[28]
VSS[118]
D54
R17
VSS[206]
VSS[275]
AC46
AT14
D58
R20
VSS[29]
VSS[119]
VSS[207]
VSS[276]
AC6
AT19
D6
R4
VSS[30]
VSS[120]
VSS[208]
VSS[277]
AD17
AT36
R46
VSS[31]
VSS[121]
E25
VSS[209]
VSS[278]
AD20
AT4
T1
VSS[32]
VSS[122]
E29
VSS[210]
VSS[279]
AD4
AT45
E3
T47
2 VSS[33]
VSS
VSS
VSS[123]
VSS[211]
VSS[280]
AD61