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Journal of Semiconductor Devices and Circuits

ISSN: 2455–3379 (Online)


Volume 5, Issue 3
www.stmjournals.com

Numerical Simulation and Modeling of Self Heating in


SOI MOSFET
Akansha Choudhary, A.D.D. Dwivedi*
Department of Electrical and Electronics Engineering, Poornima University Jaipur-303905

Abstract
As Moore’s law, the device size has been reduced and the temperature increment of high-
performance very large scale integrations (VLSIs) has become a major issue. The self-heating
effect and non-uniform power distribution in VLSIs affect the performance of device. In this
study, numerical simulation of self heating in SOI MOSFET has been performed. Poisson's
equation, continuity equation, energy balance equation and heat flow equations have been
solved self consistently using finite element method with the help of 2D device simulation
software ATLAS from Silvaco Inc. Also simulation of distribution of lattice temperature inside
the device has been performed.

Keywords: Silicon on insulator (SOI), self heating, numerical simulation, energy balance
model

*Author for Correspondence E-mail: adddwivedi@gmail.com

INTRODUCTION the saturation region [3]. The temperature rise


The technological revolution has managed the directly depends on the silicon and buried
scaling of digital electronic devices, oxide thicknesses, and channel-metal contact
dimensions and performances over the last separation [4–6].
40 years. As the spacing between adjacent
interconnect wires keeps short, it leads to an In this study, we will examine the effects of
increase in the amount of heating between self heating. In this study, we will examine Id-
interconnect wires and components due to Vd characteristics and will compare these
process technology scaling. Silicon on characteristics with self heating and without
insulator (SOI) technology has many self heating [7, 8]. In this study,
advantages, so it is more useful for VLSI. Due SILVACOTCAD will be used for simulation
to the absence of the well, SOI devices have of Id-Vd and characteristics. Silvaco, Inc. is
no latch-up and low leakage current [1]. electronic design automation (EDA) software
Silicon on insulator has many advantages over and TCAD process and device simulation
bulk silicon technology: a low parasitic software [9, 10]. Silvaco provides analog
capacitance, low power consumption, semiconductor process, device and design
resistance to latch up due to isolation of n and automation solutions in CMOS, bipolar, SiGe
p well structures and high speed performance and compound technologies. Atlas is a group
[2]. Therefore, SOI MOSFET can be used at of device simulation products used to simulate
high temperature applications. To fulfill these the electrical, optical, and thermal behavior of
conditions, there is temperature rise in silicon- semiconductor devices. It provides a physics-
on-insulator technologies, that is called self- based, modular, and extensible platform to
heating effect. The low thermal conductivity analyze DC, AC, and time domain responses
of the buried oxide compared with the Si for all semiconductor based technologies in
substrate is main cause of self heating. So, two and three dimensions.
there is a temperature increment in channel
region. At sufficiently high power levels, as In this study, numerical simulation of self
there is rise in temperature at high power, the heating in SOI MOSFET has been performed
device heats up and affects carrier mobility by solving Poisson's equation, continuity
and reduces drain saturation current and a equation, energy balance equation and heat
negative differential conductance induces in flow equations, self consistently, using finite

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Numerical Simulation of Self Heating in SOI MOSFET Dwivedi and Choudhary

element method with the help of 2D device current and energy flux densities are then
simulation software ATLAS from Silvaco Inc. expressed as:
𝐽⃗𝑛 = 𝑞𝐷𝑛 ∇𝑛 − 𝑞𝜇𝑛 n∇Φ + qn𝐷𝑛𝑇 ∇𝑇𝑛 (1)
DEVICE STRUCTURES
The schematic diagram of SOI MOSFET is 𝑘𝛿𝑛
⃗⃗⃗⃗⃗
𝑆 ⃗⃗⃗⃗
𝑛 = −𝐾𝑛 ∇𝑇𝑛 − 𝐽𝑛 𝑇𝑛 ( 𝑞 ) (2)
shown in Figure 1. The parameters of SOI
MOSFET includes channel length(Lch)=3 µm,
channel thickness(t)=0.05 µm, oxide ⃗⃗⃗⃗⃗
𝐽𝑝 = −𝑞𝐷𝑝 ∇𝑝 − 𝑞𝜇𝑝 p∇Ψ − qp𝐷𝑝𝑇 ∇𝑇𝑝 (3)
thickness=0.012 µm, gate length(Lg)=1 µm,
source length(Ls)=100 nm and drain 𝑘𝛿𝑝
⃗⃗⃗⃗⃗
𝑆 ⃗⃗⃗⃗
𝑝 = −𝐾𝑝 ∇𝑇𝑝 − 𝐽𝑝 𝑇𝑝 ( ) (4)
length(Ld)=100 nm. The source and drain are 𝑞
doped with n type doping concentration of
1×1020 cm-3 and the channel is doped with a p Where, Sn is the energy flux density associated
type doping concentration of 1.75×1017 cm-3. with electrons, Kn is the thermal conductivity,
Heat dissipation is from the channel to Wn is the energy loss rate for electrons, and T n
substrate. An electric field has been induced is the carrier temperature for electrons, Sp is
which affects p type region which is low the energy flux density associated with holes,
doped. A conducting channel is created Kp is the thermal conductivity, Wp is the
between source and drain region. The gate bias energy loss rate for holes, and Tp is the carrier
voltage for off current is 0 V and on current temperature for holes.
voltage is 1 V. When there is the heat transfer,
then energy balance equation is used to show Heat Flow Equation
the heat transformation. Giga adds the heat flow equations to primary
equations that are solved by ATLAS. The heat
A higher order solution to the general flow equations have the form:
Boltzmann transport equation consists of an 𝜕𝑇
𝑐 𝐿 =∇(𝑘∇𝑇𝐿 ) +H (5)
additional coupling of the current density to 𝜕𝑡
the carrier temperature, or energy. The current Where, C is the heat capacity per unit volume
density expressions from the drift-diffusion k is thermal conductivity. H is the heat
model are modified to include this additional generation, 𝑇𝐿 is the local lattice temperature.
physical relationship. The electron and hole
(1)(2)=H

Fig. 1: Schematic Diagram of SOI MOSFET.

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Journal of Semiconductor Devices and Circuits
Volume 5, Issue 3
ISSN: 2455–3379 (Online)

RESULT AND DISCUSSION simulation of the SOI MOSFET, first we


We study effects of self heating in SOI simulated the output characteristics of the
MOSFET. Initially, physical structure of the device with self heating and without self
SOI MOSFET has been created using ATLAS heating so that effect of self heating can be
and visualized using Tony Plot. The SOI observed. Further, simulation of distribution of
MOSFET structure along with the grid points lattice temperature inside the device has been
is shown in Figure 2. Tony Plot is a powerful performed. In this study, ID-VD characteristics
tool designed to visualize TCAD1D and 2D have been simulated at gate to source voltage
structures produced by SILVACOTCAD VGS=1.1 V, VGS=2.2 V and VGS=3.3 V
simulators. respectively with and without self heating.
Figure 3 describes ID-VD characteristics of SOI
Poisson's equation, energy balance equation, MOSFET with self heating. From Figure 3, it
continuity equation and heat flow equation is clear that at high drain voltage, drain current
have been solved self consistently at every reduces. Drain current reduction’s main reason
grid point using finite element method (FEM) is channel mobility reduction. When mobility
with the help of 2D device simulation software reduces, the thermal resistance increases.
ATLAS from Silvaco. For electro thermal

Fig. 2: Physical Structure of the SOI MOSFET.

Fig. 3: Id-Vd Characteristics with Self Heating.

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Numerical Simulation of Self Heating in SOI MOSFET Dwivedi and Choudhary

Fig. 4: Id-Vd Characteristics without Self Heating.

Fig. 5: Comparison of ID-VD Characteristics with and without Self Heating.

Figure 4 shows the ID-VD characteristics of Figure 5 shows the ID-VD characteristics with
SOI MOSFET without self heating. From and without self heating of SOI MOSFET.
Figure 4, it is clear that at high drain voltage, Figure 5 shows that drain current is reduced at
drain current is not affected too much because high voltage due to self heating. At low drain
there is no reduction in channel mobility, voltage, there is no effect of self heating, so
when we are not considering self heating. At drain current is same for simulation with self
low drain voltage, there is no change in drain heating and without self heating. At high drain
current because there is no any self heating in current and the drain voltage, there is high
the device. When we are not considering self power dissipation and the temperature is also
heating effect in SOI MOSFET device, then it high, therefore, lower is the drain current due
shows a positive channel conduction. When to the reduction of the electron mobility. So
we consider self heating in SOI MOSFET, self heating is main cause of negative ID-VD
temperature of the device increases, and as curve.
temperature increases, drain current decreases.

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Journal of Semiconductor Devices and Circuits
Volume 5, Issue 3
ISSN: 2455–3379 (Online)

Fig. 6: Distribution of Lattice Temperature inside the Device.

Fig. 7: Variation of Lattice Temperature inside the Device for Vertical Cut Line from Top Gate to
Substrate.

Figure 6 shows the lattice temperature will be affected. Figure 7 shows the variation
distribution inside the SOI MOSFET. From of lattice temperature inside the device for
the Figure 6, we can see that maximum lattice vertical cut line from top gate to substrate. It
temperature is obtained below the top gate of can be seen that maximum temperature below
the device. This region is the hottest part of the the top gate is up to 427.5 K and it is
device. If drain to source voltage will be maintained throughout the gate oxide and
further increased, more power will be slightly decreases in channel region and
dissipated and self heating will increase. sharply falls down in buried oxide region and
Therefore there is urgent need to minimize the reaches to 300 K at bottom of the substrate.
self heating; otherwise reliability of the device Since thermal conductivity of the SiO2 is very

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Numerical Simulation of Self Heating in SOI MOSFET Dwivedi and Choudhary

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